vr41xx_giu.c 16 KB

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  1. /*
  2. * Driver for NEC VR4100 series General-purpose I/O Unit.
  3. *
  4. * Copyright (C) 2002 MontaVista Software Inc.
  5. * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
  6. * Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/platform_device.h>
  23. #include <linux/errno.h>
  24. #include <linux/fs.h>
  25. #include <linux/init.h>
  26. #include <linux/irq.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/types.h>
  32. #include <asm/cpu.h>
  33. #include <asm/io.h>
  34. #include <asm/vr41xx/giu.h>
  35. #include <asm/vr41xx/irq.h>
  36. #include <asm/vr41xx/vr41xx.h>
  37. MODULE_AUTHOR("Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>");
  38. MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
  39. MODULE_LICENSE("GPL");
  40. static int major; /* default is dynamic major device number */
  41. module_param(major, int, 0);
  42. MODULE_PARM_DESC(major, "Major device number");
  43. #define GIU_TYPE1_START 0x0b000100UL
  44. #define GIU_TYPE1_SIZE 0x20UL
  45. #define GIU_TYPE2_START 0x0f000140UL
  46. #define GIU_TYPE2_SIZE 0x20UL
  47. #define GIU_TYPE3_START 0x0f000140UL
  48. #define GIU_TYPE3_SIZE 0x28UL
  49. #define GIU_PULLUPDOWN_START 0x0b0002e0UL
  50. #define GIU_PULLUPDOWN_SIZE 0x04UL
  51. #define GIUIOSELL 0x00
  52. #define GIUIOSELH 0x02
  53. #define GIUPIODL 0x04
  54. #define GIUPIODH 0x06
  55. #define GIUINTSTATL 0x08
  56. #define GIUINTSTATH 0x0a
  57. #define GIUINTENL 0x0c
  58. #define GIUINTENH 0x0e
  59. #define GIUINTTYPL 0x10
  60. #define GIUINTTYPH 0x12
  61. #define GIUINTALSELL 0x14
  62. #define GIUINTALSELH 0x16
  63. #define GIUINTHTSELL 0x18
  64. #define GIUINTHTSELH 0x1a
  65. #define GIUPODATL 0x1c
  66. #define GIUPODATEN 0x1c
  67. #define GIUPODATH 0x1e
  68. #define PIOEN0 0x0100
  69. #define PIOEN1 0x0200
  70. #define GIUPODAT 0x1e
  71. #define GIUFEDGEINHL 0x20
  72. #define GIUFEDGEINHH 0x22
  73. #define GIUREDGEINHL 0x24
  74. #define GIUREDGEINHH 0x26
  75. #define GIUUSEUPDN 0x1e0
  76. #define GIUTERMUPDN 0x1e2
  77. #define GPIO_HAS_PULLUPDOWN_IO 0x0001
  78. #define GPIO_HAS_OUTPUT_ENABLE 0x0002
  79. #define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
  80. static spinlock_t giu_lock;
  81. static struct resource *giu_resource1;
  82. static struct resource *giu_resource2;
  83. static unsigned long giu_flags;
  84. static unsigned int giu_nr_pins;
  85. static void __iomem *giu_base;
  86. #define giu_read(offset) readw(giu_base + (offset))
  87. #define giu_write(offset, value) writew((value), giu_base + (offset))
  88. #define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
  89. #define GIUINT_HIGH_OFFSET 16
  90. #define GIUINT_HIGH_MAX 32
  91. static inline uint16_t giu_set(uint16_t offset, uint16_t set)
  92. {
  93. uint16_t data;
  94. data = giu_read(offset);
  95. data |= set;
  96. giu_write(offset, data);
  97. return data;
  98. }
  99. static inline uint16_t giu_clear(uint16_t offset, uint16_t clear)
  100. {
  101. uint16_t data;
  102. data = giu_read(offset);
  103. data &= ~clear;
  104. giu_write(offset, data);
  105. return data;
  106. }
  107. static void ack_giuint_low(unsigned int irq)
  108. {
  109. giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(irq));
  110. }
  111. static void mask_giuint_low(unsigned int irq)
  112. {
  113. giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
  114. }
  115. static void mask_ack_giuint_low(unsigned int irq)
  116. {
  117. unsigned int pin;
  118. pin = GPIO_PIN_OF_IRQ(irq);
  119. giu_clear(GIUINTENL, 1 << pin);
  120. giu_write(GIUINTSTATL, 1 << pin);
  121. }
  122. static void unmask_giuint_low(unsigned int irq)
  123. {
  124. giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(irq));
  125. }
  126. static struct irq_chip giuint_low_irq_chip = {
  127. .name = "GIUINTL",
  128. .ack = ack_giuint_low,
  129. .mask = mask_giuint_low,
  130. .mask_ack = mask_ack_giuint_low,
  131. .unmask = unmask_giuint_low,
  132. };
  133. static void ack_giuint_high(unsigned int irq)
  134. {
  135. giu_write(GIUINTSTATH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
  136. }
  137. static void mask_giuint_high(unsigned int irq)
  138. {
  139. giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
  140. }
  141. static void mask_ack_giuint_high(unsigned int irq)
  142. {
  143. unsigned int pin;
  144. pin = GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET;
  145. giu_clear(GIUINTENH, 1 << pin);
  146. giu_write(GIUINTSTATH, 1 << pin);
  147. }
  148. static void unmask_giuint_high(unsigned int irq)
  149. {
  150. giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(irq) - GIUINT_HIGH_OFFSET));
  151. }
  152. static struct irq_chip giuint_high_irq_chip = {
  153. .name = "GIUINTH",
  154. .ack = ack_giuint_high,
  155. .mask = mask_giuint_high,
  156. .mask_ack = mask_ack_giuint_high,
  157. .unmask = unmask_giuint_high,
  158. };
  159. static int giu_get_irq(unsigned int irq)
  160. {
  161. uint16_t pendl, pendh, maskl, maskh;
  162. int i;
  163. pendl = giu_read(GIUINTSTATL);
  164. pendh = giu_read(GIUINTSTATH);
  165. maskl = giu_read(GIUINTENL);
  166. maskh = giu_read(GIUINTENH);
  167. maskl &= pendl;
  168. maskh &= pendh;
  169. if (maskl) {
  170. for (i = 0; i < 16; i++) {
  171. if (maskl & (1 << i))
  172. return GIU_IRQ(i);
  173. }
  174. } else if (maskh) {
  175. for (i = 0; i < 16; i++) {
  176. if (maskh & (1 << i))
  177. return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
  178. }
  179. }
  180. printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
  181. maskl, pendl, maskh, pendh);
  182. atomic_inc(&irq_err_count);
  183. return -EINVAL;
  184. }
  185. void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal)
  186. {
  187. uint16_t mask;
  188. if (pin < GIUINT_HIGH_OFFSET) {
  189. mask = 1 << pin;
  190. if (trigger != IRQ_TRIGGER_LEVEL) {
  191. giu_set(GIUINTTYPL, mask);
  192. if (signal == IRQ_SIGNAL_HOLD)
  193. giu_set(GIUINTHTSELL, mask);
  194. else
  195. giu_clear(GIUINTHTSELL, mask);
  196. if (current_cpu_data.cputype == CPU_VR4133) {
  197. switch (trigger) {
  198. case IRQ_TRIGGER_EDGE_FALLING:
  199. giu_set(GIUFEDGEINHL, mask);
  200. giu_clear(GIUREDGEINHL, mask);
  201. break;
  202. case IRQ_TRIGGER_EDGE_RISING:
  203. giu_clear(GIUFEDGEINHL, mask);
  204. giu_set(GIUREDGEINHL, mask);
  205. break;
  206. default:
  207. giu_set(GIUFEDGEINHL, mask);
  208. giu_set(GIUREDGEINHL, mask);
  209. break;
  210. }
  211. }
  212. set_irq_chip_and_handler(GIU_IRQ(pin),
  213. &giuint_low_irq_chip,
  214. handle_edge_irq);
  215. } else {
  216. giu_clear(GIUINTTYPL, mask);
  217. giu_clear(GIUINTHTSELL, mask);
  218. set_irq_chip_and_handler(GIU_IRQ(pin),
  219. &giuint_low_irq_chip,
  220. handle_level_irq);
  221. }
  222. giu_write(GIUINTSTATL, mask);
  223. } else if (pin < GIUINT_HIGH_MAX) {
  224. mask = 1 << (pin - GIUINT_HIGH_OFFSET);
  225. if (trigger != IRQ_TRIGGER_LEVEL) {
  226. giu_set(GIUINTTYPH, mask);
  227. if (signal == IRQ_SIGNAL_HOLD)
  228. giu_set(GIUINTHTSELH, mask);
  229. else
  230. giu_clear(GIUINTHTSELH, mask);
  231. if (current_cpu_data.cputype == CPU_VR4133) {
  232. switch (trigger) {
  233. case IRQ_TRIGGER_EDGE_FALLING:
  234. giu_set(GIUFEDGEINHH, mask);
  235. giu_clear(GIUREDGEINHH, mask);
  236. break;
  237. case IRQ_TRIGGER_EDGE_RISING:
  238. giu_clear(GIUFEDGEINHH, mask);
  239. giu_set(GIUREDGEINHH, mask);
  240. break;
  241. default:
  242. giu_set(GIUFEDGEINHH, mask);
  243. giu_set(GIUREDGEINHH, mask);
  244. break;
  245. }
  246. }
  247. set_irq_chip_and_handler(GIU_IRQ(pin),
  248. &giuint_high_irq_chip,
  249. handle_edge_irq);
  250. } else {
  251. giu_clear(GIUINTTYPH, mask);
  252. giu_clear(GIUINTHTSELH, mask);
  253. set_irq_chip_and_handler(GIU_IRQ(pin),
  254. &giuint_high_irq_chip,
  255. handle_level_irq);
  256. }
  257. giu_write(GIUINTSTATH, mask);
  258. }
  259. }
  260. EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
  261. void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
  262. {
  263. uint16_t mask;
  264. if (pin < GIUINT_HIGH_OFFSET) {
  265. mask = 1 << pin;
  266. if (level == IRQ_LEVEL_HIGH)
  267. giu_set(GIUINTALSELL, mask);
  268. else
  269. giu_clear(GIUINTALSELL, mask);
  270. giu_write(GIUINTSTATL, mask);
  271. } else if (pin < GIUINT_HIGH_MAX) {
  272. mask = 1 << (pin - GIUINT_HIGH_OFFSET);
  273. if (level == IRQ_LEVEL_HIGH)
  274. giu_set(GIUINTALSELH, mask);
  275. else
  276. giu_clear(GIUINTALSELH, mask);
  277. giu_write(GIUINTSTATH, mask);
  278. }
  279. }
  280. EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
  281. gpio_data_t vr41xx_gpio_get_pin(unsigned int pin)
  282. {
  283. uint16_t reg, mask;
  284. if (pin >= giu_nr_pins)
  285. return GPIO_DATA_INVAL;
  286. if (pin < 16) {
  287. reg = giu_read(GIUPIODL);
  288. mask = (uint16_t)1 << pin;
  289. } else if (pin < 32) {
  290. reg = giu_read(GIUPIODH);
  291. mask = (uint16_t)1 << (pin - 16);
  292. } else if (pin < 48) {
  293. reg = giu_read(GIUPODATL);
  294. mask = (uint16_t)1 << (pin - 32);
  295. } else {
  296. reg = giu_read(GIUPODATH);
  297. mask = (uint16_t)1 << (pin - 48);
  298. }
  299. if (reg & mask)
  300. return GPIO_DATA_HIGH;
  301. return GPIO_DATA_LOW;
  302. }
  303. EXPORT_SYMBOL_GPL(vr41xx_gpio_get_pin);
  304. int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data)
  305. {
  306. uint16_t offset, mask, reg;
  307. unsigned long flags;
  308. if (pin >= giu_nr_pins)
  309. return -EINVAL;
  310. if (pin < 16) {
  311. offset = GIUPIODL;
  312. mask = (uint16_t)1 << pin;
  313. } else if (pin < 32) {
  314. offset = GIUPIODH;
  315. mask = (uint16_t)1 << (pin - 16);
  316. } else if (pin < 48) {
  317. offset = GIUPODATL;
  318. mask = (uint16_t)1 << (pin - 32);
  319. } else {
  320. offset = GIUPODATH;
  321. mask = (uint16_t)1 << (pin - 48);
  322. }
  323. spin_lock_irqsave(&giu_lock, flags);
  324. reg = giu_read(offset);
  325. if (data == GPIO_DATA_HIGH)
  326. reg |= mask;
  327. else
  328. reg &= ~mask;
  329. giu_write(offset, reg);
  330. spin_unlock_irqrestore(&giu_lock, flags);
  331. return 0;
  332. }
  333. EXPORT_SYMBOL_GPL(vr41xx_gpio_set_pin);
  334. int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir)
  335. {
  336. uint16_t offset, mask, reg;
  337. unsigned long flags;
  338. if (pin >= giu_nr_pins)
  339. return -EINVAL;
  340. if (pin < 16) {
  341. offset = GIUIOSELL;
  342. mask = (uint16_t)1 << pin;
  343. } else if (pin < 32) {
  344. offset = GIUIOSELH;
  345. mask = (uint16_t)1 << (pin - 16);
  346. } else {
  347. if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
  348. offset = GIUPODATEN;
  349. mask = (uint16_t)1 << (pin - 32);
  350. } else {
  351. switch (pin) {
  352. case 48:
  353. offset = GIUPODATH;
  354. mask = PIOEN0;
  355. break;
  356. case 49:
  357. offset = GIUPODATH;
  358. mask = PIOEN1;
  359. break;
  360. default:
  361. return -EINVAL;
  362. }
  363. }
  364. }
  365. spin_lock_irqsave(&giu_lock, flags);
  366. reg = giu_read(offset);
  367. if (dir == GPIO_OUTPUT)
  368. reg |= mask;
  369. else
  370. reg &= ~mask;
  371. giu_write(offset, reg);
  372. spin_unlock_irqrestore(&giu_lock, flags);
  373. return 0;
  374. }
  375. EXPORT_SYMBOL_GPL(vr41xx_gpio_set_direction);
  376. int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull)
  377. {
  378. uint16_t reg, mask;
  379. unsigned long flags;
  380. if ((giu_flags & GPIO_HAS_PULLUPDOWN_IO) != GPIO_HAS_PULLUPDOWN_IO)
  381. return -EPERM;
  382. if (pin >= 15)
  383. return -EINVAL;
  384. mask = (uint16_t)1 << pin;
  385. spin_lock_irqsave(&giu_lock, flags);
  386. if (pull == GPIO_PULL_UP || pull == GPIO_PULL_DOWN) {
  387. reg = giu_read(GIUTERMUPDN);
  388. if (pull == GPIO_PULL_UP)
  389. reg |= mask;
  390. else
  391. reg &= ~mask;
  392. giu_write(GIUTERMUPDN, reg);
  393. reg = giu_read(GIUUSEUPDN);
  394. reg |= mask;
  395. giu_write(GIUUSEUPDN, reg);
  396. } else {
  397. reg = giu_read(GIUUSEUPDN);
  398. reg &= ~mask;
  399. giu_write(GIUUSEUPDN, reg);
  400. }
  401. spin_unlock_irqrestore(&giu_lock, flags);
  402. return 0;
  403. }
  404. EXPORT_SYMBOL_GPL(vr41xx_gpio_pullupdown);
  405. static ssize_t gpio_read(struct file *file, char __user *buf, size_t len,
  406. loff_t *ppos)
  407. {
  408. unsigned int pin;
  409. char value = '0';
  410. pin = iminor(file->f_path.dentry->d_inode);
  411. if (pin >= giu_nr_pins)
  412. return -EBADF;
  413. if (vr41xx_gpio_get_pin(pin) == GPIO_DATA_HIGH)
  414. value = '1';
  415. if (len <= 0)
  416. return -EFAULT;
  417. if (put_user(value, buf))
  418. return -EFAULT;
  419. return 1;
  420. }
  421. static ssize_t gpio_write(struct file *file, const char __user *data,
  422. size_t len, loff_t *ppos)
  423. {
  424. unsigned int pin;
  425. size_t i;
  426. char c;
  427. int retval = 0;
  428. pin = iminor(file->f_path.dentry->d_inode);
  429. if (pin >= giu_nr_pins)
  430. return -EBADF;
  431. for (i = 0; i < len; i++) {
  432. if (get_user(c, data + i))
  433. return -EFAULT;
  434. switch (c) {
  435. case '0':
  436. retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_LOW);
  437. break;
  438. case '1':
  439. retval = vr41xx_gpio_set_pin(pin, GPIO_DATA_HIGH);
  440. break;
  441. case 'D':
  442. printk(KERN_INFO "GPIO%d: pull down\n", pin);
  443. retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DOWN);
  444. break;
  445. case 'd':
  446. printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
  447. retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
  448. break;
  449. case 'I':
  450. printk(KERN_INFO "GPIO%d: input\n", pin);
  451. retval = vr41xx_gpio_set_direction(pin, GPIO_INPUT);
  452. break;
  453. case 'O':
  454. printk(KERN_INFO "GPIO%d: output\n", pin);
  455. retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT);
  456. break;
  457. case 'o':
  458. printk(KERN_INFO "GPIO%d: output disable\n", pin);
  459. retval = vr41xx_gpio_set_direction(pin, GPIO_OUTPUT_DISABLE);
  460. break;
  461. case 'P':
  462. printk(KERN_INFO "GPIO%d: pull up\n", pin);
  463. retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_UP);
  464. break;
  465. case 'p':
  466. printk(KERN_INFO "GPIO%d: pull up/down disable\n", pin);
  467. retval = vr41xx_gpio_pullupdown(pin, GPIO_PULL_DISABLE);
  468. break;
  469. default:
  470. break;
  471. }
  472. if (retval < 0)
  473. break;
  474. }
  475. return i;
  476. }
  477. static int gpio_open(struct inode *inode, struct file *file)
  478. {
  479. unsigned int pin;
  480. pin = iminor(inode);
  481. if (pin >= giu_nr_pins)
  482. return -EBADF;
  483. return nonseekable_open(inode, file);
  484. }
  485. static int gpio_release(struct inode *inode, struct file *file)
  486. {
  487. unsigned int pin;
  488. pin = iminor(inode);
  489. if (pin >= giu_nr_pins)
  490. return -EBADF;
  491. return 0;
  492. }
  493. static const struct file_operations gpio_fops = {
  494. .owner = THIS_MODULE,
  495. .read = gpio_read,
  496. .write = gpio_write,
  497. .open = gpio_open,
  498. .release = gpio_release,
  499. };
  500. static int __devinit giu_probe(struct platform_device *dev)
  501. {
  502. unsigned long start, size, flags = 0;
  503. unsigned int nr_pins = 0, trigger, i, pin;
  504. struct resource *res1, *res2 = NULL;
  505. void *base;
  506. struct irq_chip *chip;
  507. int retval;
  508. switch (current_cpu_data.cputype) {
  509. case CPU_VR4111:
  510. case CPU_VR4121:
  511. start = GIU_TYPE1_START;
  512. size = GIU_TYPE1_SIZE;
  513. flags = GPIO_HAS_PULLUPDOWN_IO;
  514. nr_pins = 50;
  515. break;
  516. case CPU_VR4122:
  517. case CPU_VR4131:
  518. start = GIU_TYPE2_START;
  519. size = GIU_TYPE2_SIZE;
  520. nr_pins = 36;
  521. break;
  522. case CPU_VR4133:
  523. start = GIU_TYPE3_START;
  524. size = GIU_TYPE3_SIZE;
  525. flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
  526. nr_pins = 48;
  527. break;
  528. default:
  529. return -ENODEV;
  530. }
  531. res1 = request_mem_region(start, size, "GIU");
  532. if (res1 == NULL)
  533. return -EBUSY;
  534. base = ioremap(start, size);
  535. if (base == NULL) {
  536. release_resource(res1);
  537. return -ENOMEM;
  538. }
  539. if (flags & GPIO_HAS_PULLUPDOWN_IO) {
  540. res2 = request_mem_region(GIU_PULLUPDOWN_START, GIU_PULLUPDOWN_SIZE, "GIU");
  541. if (res2 == NULL) {
  542. iounmap(base);
  543. release_resource(res1);
  544. return -EBUSY;
  545. }
  546. }
  547. retval = register_chrdev(major, "GIU", &gpio_fops);
  548. if (retval < 0) {
  549. iounmap(base);
  550. release_resource(res1);
  551. release_resource(res2);
  552. return retval;
  553. }
  554. if (major == 0) {
  555. major = retval;
  556. printk(KERN_INFO "GIU: major number %d\n", major);
  557. }
  558. spin_lock_init(&giu_lock);
  559. giu_base = base;
  560. giu_resource1 = res1;
  561. giu_resource2 = res2;
  562. giu_flags = flags;
  563. giu_nr_pins = nr_pins;
  564. giu_write(GIUINTENL, 0);
  565. giu_write(GIUINTENH, 0);
  566. trigger = giu_read(GIUINTTYPH) << 16;
  567. trigger |= giu_read(GIUINTTYPL);
  568. for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
  569. pin = GPIO_PIN_OF_IRQ(i);
  570. if (pin < GIUINT_HIGH_OFFSET)
  571. chip = &giuint_low_irq_chip;
  572. else
  573. chip = &giuint_high_irq_chip;
  574. if (trigger & (1 << pin))
  575. set_irq_chip_and_handler(i, chip, handle_edge_irq);
  576. else
  577. set_irq_chip_and_handler(i, chip, handle_level_irq);
  578. }
  579. return cascade_irq(GIUINT_IRQ, giu_get_irq);
  580. }
  581. static int __devexit giu_remove(struct platform_device *dev)
  582. {
  583. iounmap(giu_base);
  584. release_resource(giu_resource1);
  585. if (giu_flags & GPIO_HAS_PULLUPDOWN_IO)
  586. release_resource(giu_resource2);
  587. return 0;
  588. }
  589. static struct platform_device *giu_platform_device;
  590. static struct platform_driver giu_device_driver = {
  591. .probe = giu_probe,
  592. .remove = __devexit_p(giu_remove),
  593. .driver = {
  594. .name = "GIU",
  595. .owner = THIS_MODULE,
  596. },
  597. };
  598. static int __init vr41xx_giu_init(void)
  599. {
  600. int retval;
  601. giu_platform_device = platform_device_alloc("GIU", -1);
  602. if (!giu_platform_device)
  603. return -ENOMEM;
  604. retval = platform_device_add(giu_platform_device);
  605. if (retval < 0) {
  606. platform_device_put(giu_platform_device);
  607. return retval;
  608. }
  609. retval = platform_driver_register(&giu_device_driver);
  610. if (retval < 0)
  611. platform_device_unregister(giu_platform_device);
  612. return retval;
  613. }
  614. static void __exit vr41xx_giu_exit(void)
  615. {
  616. platform_driver_unregister(&giu_device_driver);
  617. platform_device_unregister(giu_platform_device);
  618. }
  619. module_init(vr41xx_giu_init);
  620. module_exit(vr41xx_giu_exit);