synclinkmp.c 148 KB

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  1. /*
  2. * $Id: synclinkmp.c,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  3. *
  4. * Device driver for Microgate SyncLink Multiport
  5. * high speed multiprotocol serial adapter.
  6. *
  7. * written by Paul Fulghum for Microgate Corporation
  8. * paulkf@microgate.com
  9. *
  10. * Microgate and SyncLink are trademarks of Microgate Corporation
  11. *
  12. * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13. * This code is released under the GNU General Public License (GPL)
  14. *
  15. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25. * OF THE POSSIBILITY OF SUCH DAMAGE.
  26. */
  27. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  28. #if defined(__i386__)
  29. # define BREAKPOINT() asm(" int $3");
  30. #else
  31. # define BREAKPOINT() { }
  32. #endif
  33. #define MAX_DEVICES 12
  34. #include <linux/module.h>
  35. #include <linux/errno.h>
  36. #include <linux/signal.h>
  37. #include <linux/sched.h>
  38. #include <linux/timer.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/pci.h>
  41. #include <linux/tty.h>
  42. #include <linux/tty_flip.h>
  43. #include <linux/serial.h>
  44. #include <linux/major.h>
  45. #include <linux/string.h>
  46. #include <linux/fcntl.h>
  47. #include <linux/ptrace.h>
  48. #include <linux/ioport.h>
  49. #include <linux/mm.h>
  50. #include <linux/slab.h>
  51. #include <linux/netdevice.h>
  52. #include <linux/vmalloc.h>
  53. #include <linux/init.h>
  54. #include <linux/delay.h>
  55. #include <linux/ioctl.h>
  56. #include <asm/system.h>
  57. #include <asm/io.h>
  58. #include <asm/irq.h>
  59. #include <asm/dma.h>
  60. #include <linux/bitops.h>
  61. #include <asm/types.h>
  62. #include <linux/termios.h>
  63. #include <linux/workqueue.h>
  64. #include <linux/hdlc.h>
  65. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  66. #define SYNCLINK_GENERIC_HDLC 1
  67. #else
  68. #define SYNCLINK_GENERIC_HDLC 0
  69. #endif
  70. #define GET_USER(error,value,addr) error = get_user(value,addr)
  71. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  72. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  73. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  74. #include <asm/uaccess.h>
  75. #include "linux/synclink.h"
  76. static MGSL_PARAMS default_params = {
  77. MGSL_MODE_HDLC, /* unsigned long mode */
  78. 0, /* unsigned char loopback; */
  79. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  80. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  81. 0, /* unsigned long clock_speed; */
  82. 0xff, /* unsigned char addr_filter; */
  83. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  84. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  85. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  86. 9600, /* unsigned long data_rate; */
  87. 8, /* unsigned char data_bits; */
  88. 1, /* unsigned char stop_bits; */
  89. ASYNC_PARITY_NONE /* unsigned char parity; */
  90. };
  91. /* size in bytes of DMA data buffers */
  92. #define SCABUFSIZE 1024
  93. #define SCA_MEM_SIZE 0x40000
  94. #define SCA_BASE_SIZE 512
  95. #define SCA_REG_SIZE 16
  96. #define SCA_MAX_PORTS 4
  97. #define SCAMAXDESC 128
  98. #define BUFFERLISTSIZE 4096
  99. /* SCA-I style DMA buffer descriptor */
  100. typedef struct _SCADESC
  101. {
  102. u16 next; /* lower l6 bits of next descriptor addr */
  103. u16 buf_ptr; /* lower 16 bits of buffer addr */
  104. u8 buf_base; /* upper 8 bits of buffer addr */
  105. u8 pad1;
  106. u16 length; /* length of buffer */
  107. u8 status; /* status of buffer */
  108. u8 pad2;
  109. } SCADESC, *PSCADESC;
  110. typedef struct _SCADESC_EX
  111. {
  112. /* device driver bookkeeping section */
  113. char *virt_addr; /* virtual address of data buffer */
  114. u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
  115. } SCADESC_EX, *PSCADESC_EX;
  116. /* The queue of BH actions to be performed */
  117. #define BH_RECEIVE 1
  118. #define BH_TRANSMIT 2
  119. #define BH_STATUS 4
  120. #define IO_PIN_SHUTDOWN_LIMIT 100
  121. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  122. struct _input_signal_events {
  123. int ri_up;
  124. int ri_down;
  125. int dsr_up;
  126. int dsr_down;
  127. int dcd_up;
  128. int dcd_down;
  129. int cts_up;
  130. int cts_down;
  131. };
  132. /*
  133. * Device instance data structure
  134. */
  135. typedef struct _synclinkmp_info {
  136. void *if_ptr; /* General purpose pointer (used by SPPP) */
  137. int magic;
  138. int flags;
  139. int count; /* count of opens */
  140. int line;
  141. unsigned short close_delay;
  142. unsigned short closing_wait; /* time to wait before closing */
  143. struct mgsl_icount icount;
  144. struct tty_struct *tty;
  145. int timeout;
  146. int x_char; /* xon/xoff character */
  147. int blocked_open; /* # of blocked opens */
  148. u16 read_status_mask1; /* break detection (SR1 indications) */
  149. u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
  150. unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
  151. unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
  152. unsigned char *tx_buf;
  153. int tx_put;
  154. int tx_get;
  155. int tx_count;
  156. wait_queue_head_t open_wait;
  157. wait_queue_head_t close_wait;
  158. wait_queue_head_t status_event_wait_q;
  159. wait_queue_head_t event_wait_q;
  160. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  161. struct _synclinkmp_info *next_device; /* device list link */
  162. struct timer_list status_timer; /* input signal status check timer */
  163. spinlock_t lock; /* spinlock for synchronizing with ISR */
  164. struct work_struct task; /* task structure for scheduling bh */
  165. u32 max_frame_size; /* as set by device config */
  166. u32 pending_bh;
  167. int bh_running; /* Protection from multiple */
  168. int isr_overflow;
  169. int bh_requested;
  170. int dcd_chkcount; /* check counts to prevent */
  171. int cts_chkcount; /* too many IRQs if a signal */
  172. int dsr_chkcount; /* is floating */
  173. int ri_chkcount;
  174. char *buffer_list; /* virtual address of Rx & Tx buffer lists */
  175. unsigned long buffer_list_phys;
  176. unsigned int rx_buf_count; /* count of total allocated Rx buffers */
  177. SCADESC *rx_buf_list; /* list of receive buffer entries */
  178. SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
  179. unsigned int current_rx_buf;
  180. unsigned int tx_buf_count; /* count of total allocated Tx buffers */
  181. SCADESC *tx_buf_list; /* list of transmit buffer entries */
  182. SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
  183. unsigned int last_tx_buf;
  184. unsigned char *tmp_rx_buf;
  185. unsigned int tmp_rx_buf_count;
  186. int rx_enabled;
  187. int rx_overflow;
  188. int tx_enabled;
  189. int tx_active;
  190. u32 idle_mode;
  191. unsigned char ie0_value;
  192. unsigned char ie1_value;
  193. unsigned char ie2_value;
  194. unsigned char ctrlreg_value;
  195. unsigned char old_signals;
  196. char device_name[25]; /* device instance name */
  197. int port_count;
  198. int adapter_num;
  199. int port_num;
  200. struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
  201. unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
  202. unsigned int irq_level; /* interrupt level */
  203. unsigned long irq_flags;
  204. int irq_requested; /* nonzero if IRQ requested */
  205. MGSL_PARAMS params; /* communications parameters */
  206. unsigned char serial_signals; /* current serial signal states */
  207. int irq_occurred; /* for diagnostics use */
  208. unsigned int init_error; /* Initialization startup error */
  209. u32 last_mem_alloc;
  210. unsigned char* memory_base; /* shared memory address (PCI only) */
  211. u32 phys_memory_base;
  212. int shared_mem_requested;
  213. unsigned char* sca_base; /* HD64570 SCA Memory address */
  214. u32 phys_sca_base;
  215. u32 sca_offset;
  216. int sca_base_requested;
  217. unsigned char* lcr_base; /* local config registers (PCI only) */
  218. u32 phys_lcr_base;
  219. u32 lcr_offset;
  220. int lcr_mem_requested;
  221. unsigned char* statctrl_base; /* status/control register memory */
  222. u32 phys_statctrl_base;
  223. u32 statctrl_offset;
  224. int sca_statctrl_requested;
  225. u32 misc_ctrl_value;
  226. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  227. char char_buf[MAX_ASYNC_BUFFER_SIZE];
  228. BOOLEAN drop_rts_on_tx_done;
  229. struct _input_signal_events input_signal_events;
  230. /* SPPP/Cisco HDLC device parts */
  231. int netcount;
  232. int dosyncppp;
  233. spinlock_t netlock;
  234. #if SYNCLINK_GENERIC_HDLC
  235. struct net_device *netdev;
  236. #endif
  237. } SLMP_INFO;
  238. #define MGSL_MAGIC 0x5401
  239. /*
  240. * define serial signal status change macros
  241. */
  242. #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
  243. #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
  244. #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
  245. #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
  246. /* Common Register macros */
  247. #define LPR 0x00
  248. #define PABR0 0x02
  249. #define PABR1 0x03
  250. #define WCRL 0x04
  251. #define WCRM 0x05
  252. #define WCRH 0x06
  253. #define DPCR 0x08
  254. #define DMER 0x09
  255. #define ISR0 0x10
  256. #define ISR1 0x11
  257. #define ISR2 0x12
  258. #define IER0 0x14
  259. #define IER1 0x15
  260. #define IER2 0x16
  261. #define ITCR 0x18
  262. #define INTVR 0x1a
  263. #define IMVR 0x1c
  264. /* MSCI Register macros */
  265. #define TRB 0x20
  266. #define TRBL 0x20
  267. #define TRBH 0x21
  268. #define SR0 0x22
  269. #define SR1 0x23
  270. #define SR2 0x24
  271. #define SR3 0x25
  272. #define FST 0x26
  273. #define IE0 0x28
  274. #define IE1 0x29
  275. #define IE2 0x2a
  276. #define FIE 0x2b
  277. #define CMD 0x2c
  278. #define MD0 0x2e
  279. #define MD1 0x2f
  280. #define MD2 0x30
  281. #define CTL 0x31
  282. #define SA0 0x32
  283. #define SA1 0x33
  284. #define IDL 0x34
  285. #define TMC 0x35
  286. #define RXS 0x36
  287. #define TXS 0x37
  288. #define TRC0 0x38
  289. #define TRC1 0x39
  290. #define RRC 0x3a
  291. #define CST0 0x3c
  292. #define CST1 0x3d
  293. /* Timer Register Macros */
  294. #define TCNT 0x60
  295. #define TCNTL 0x60
  296. #define TCNTH 0x61
  297. #define TCONR 0x62
  298. #define TCONRL 0x62
  299. #define TCONRH 0x63
  300. #define TMCS 0x64
  301. #define TEPR 0x65
  302. /* DMA Controller Register macros */
  303. #define DARL 0x80
  304. #define DARH 0x81
  305. #define DARB 0x82
  306. #define BAR 0x80
  307. #define BARL 0x80
  308. #define BARH 0x81
  309. #define BARB 0x82
  310. #define SAR 0x84
  311. #define SARL 0x84
  312. #define SARH 0x85
  313. #define SARB 0x86
  314. #define CPB 0x86
  315. #define CDA 0x88
  316. #define CDAL 0x88
  317. #define CDAH 0x89
  318. #define EDA 0x8a
  319. #define EDAL 0x8a
  320. #define EDAH 0x8b
  321. #define BFL 0x8c
  322. #define BFLL 0x8c
  323. #define BFLH 0x8d
  324. #define BCR 0x8e
  325. #define BCRL 0x8e
  326. #define BCRH 0x8f
  327. #define DSR 0x90
  328. #define DMR 0x91
  329. #define FCT 0x93
  330. #define DIR 0x94
  331. #define DCMD 0x95
  332. /* combine with timer or DMA register address */
  333. #define TIMER0 0x00
  334. #define TIMER1 0x08
  335. #define TIMER2 0x10
  336. #define TIMER3 0x18
  337. #define RXDMA 0x00
  338. #define TXDMA 0x20
  339. /* SCA Command Codes */
  340. #define NOOP 0x00
  341. #define TXRESET 0x01
  342. #define TXENABLE 0x02
  343. #define TXDISABLE 0x03
  344. #define TXCRCINIT 0x04
  345. #define TXCRCEXCL 0x05
  346. #define TXEOM 0x06
  347. #define TXABORT 0x07
  348. #define MPON 0x08
  349. #define TXBUFCLR 0x09
  350. #define RXRESET 0x11
  351. #define RXENABLE 0x12
  352. #define RXDISABLE 0x13
  353. #define RXCRCINIT 0x14
  354. #define RXREJECT 0x15
  355. #define SEARCHMP 0x16
  356. #define RXCRCEXCL 0x17
  357. #define RXCRCCALC 0x18
  358. #define CHRESET 0x21
  359. #define HUNT 0x31
  360. /* DMA command codes */
  361. #define SWABORT 0x01
  362. #define FEICLEAR 0x02
  363. /* IE0 */
  364. #define TXINTE BIT7
  365. #define RXINTE BIT6
  366. #define TXRDYE BIT1
  367. #define RXRDYE BIT0
  368. /* IE1 & SR1 */
  369. #define UDRN BIT7
  370. #define IDLE BIT6
  371. #define SYNCD BIT4
  372. #define FLGD BIT4
  373. #define CCTS BIT3
  374. #define CDCD BIT2
  375. #define BRKD BIT1
  376. #define ABTD BIT1
  377. #define GAPD BIT1
  378. #define BRKE BIT0
  379. #define IDLD BIT0
  380. /* IE2 & SR2 */
  381. #define EOM BIT7
  382. #define PMP BIT6
  383. #define SHRT BIT6
  384. #define PE BIT5
  385. #define ABT BIT5
  386. #define FRME BIT4
  387. #define RBIT BIT4
  388. #define OVRN BIT3
  389. #define CRCE BIT2
  390. /*
  391. * Global linked list of SyncLink devices
  392. */
  393. static SLMP_INFO *synclinkmp_device_list = NULL;
  394. static int synclinkmp_adapter_count = -1;
  395. static int synclinkmp_device_count = 0;
  396. /*
  397. * Set this param to non-zero to load eax with the
  398. * .text section address and breakpoint on module load.
  399. * This is useful for use with gdb and add-symbol-file command.
  400. */
  401. static int break_on_load=0;
  402. /*
  403. * Driver major number, defaults to zero to get auto
  404. * assigned major number. May be forced as module parameter.
  405. */
  406. static int ttymajor=0;
  407. /*
  408. * Array of user specified options for ISA adapters.
  409. */
  410. static int debug_level = 0;
  411. static int maxframe[MAX_DEVICES] = {0,};
  412. static int dosyncppp[MAX_DEVICES] = {0,};
  413. module_param(break_on_load, bool, 0);
  414. module_param(ttymajor, int, 0);
  415. module_param(debug_level, int, 0);
  416. module_param_array(maxframe, int, NULL, 0);
  417. module_param_array(dosyncppp, int, NULL, 0);
  418. static char *driver_name = "SyncLink MultiPort driver";
  419. static char *driver_version = "$Revision: 1.1.1.1 $";
  420. static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
  421. static void synclinkmp_remove_one(struct pci_dev *dev);
  422. static struct pci_device_id synclinkmp_pci_tbl[] = {
  423. { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
  424. { 0, }, /* terminate list */
  425. };
  426. MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
  427. MODULE_LICENSE("GPL");
  428. static struct pci_driver synclinkmp_pci_driver = {
  429. .name = "synclinkmp",
  430. .id_table = synclinkmp_pci_tbl,
  431. .probe = synclinkmp_init_one,
  432. .remove = __devexit_p(synclinkmp_remove_one),
  433. };
  434. static struct tty_driver *serial_driver;
  435. /* number of characters left in xmit buffer before we ask for more */
  436. #define WAKEUP_CHARS 256
  437. /* tty callbacks */
  438. static int open(struct tty_struct *tty, struct file * filp);
  439. static void close(struct tty_struct *tty, struct file * filp);
  440. static void hangup(struct tty_struct *tty);
  441. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
  442. static int write(struct tty_struct *tty, const unsigned char *buf, int count);
  443. static void put_char(struct tty_struct *tty, unsigned char ch);
  444. static void send_xchar(struct tty_struct *tty, char ch);
  445. static void wait_until_sent(struct tty_struct *tty, int timeout);
  446. static int write_room(struct tty_struct *tty);
  447. static void flush_chars(struct tty_struct *tty);
  448. static void flush_buffer(struct tty_struct *tty);
  449. static void tx_hold(struct tty_struct *tty);
  450. static void tx_release(struct tty_struct *tty);
  451. static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
  452. static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
  453. static int chars_in_buffer(struct tty_struct *tty);
  454. static void throttle(struct tty_struct * tty);
  455. static void unthrottle(struct tty_struct * tty);
  456. static void set_break(struct tty_struct *tty, int break_state);
  457. #if SYNCLINK_GENERIC_HDLC
  458. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  459. static void hdlcdev_tx_done(SLMP_INFO *info);
  460. static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
  461. static int hdlcdev_init(SLMP_INFO *info);
  462. static void hdlcdev_exit(SLMP_INFO *info);
  463. #endif
  464. /* ioctl handlers */
  465. static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
  466. static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
  467. static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
  468. static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
  469. static int set_txidle(SLMP_INFO *info, int idle_mode);
  470. static int tx_enable(SLMP_INFO *info, int enable);
  471. static int tx_abort(SLMP_INFO *info);
  472. static int rx_enable(SLMP_INFO *info, int enable);
  473. static int modem_input_wait(SLMP_INFO *info,int arg);
  474. static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
  475. static int tiocmget(struct tty_struct *tty, struct file *file);
  476. static int tiocmset(struct tty_struct *tty, struct file *file,
  477. unsigned int set, unsigned int clear);
  478. static void set_break(struct tty_struct *tty, int break_state);
  479. static void add_device(SLMP_INFO *info);
  480. static void device_init(int adapter_num, struct pci_dev *pdev);
  481. static int claim_resources(SLMP_INFO *info);
  482. static void release_resources(SLMP_INFO *info);
  483. static int startup(SLMP_INFO *info);
  484. static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
  485. static void shutdown(SLMP_INFO *info);
  486. static void program_hw(SLMP_INFO *info);
  487. static void change_params(SLMP_INFO *info);
  488. static int init_adapter(SLMP_INFO *info);
  489. static int register_test(SLMP_INFO *info);
  490. static int irq_test(SLMP_INFO *info);
  491. static int loopback_test(SLMP_INFO *info);
  492. static int adapter_test(SLMP_INFO *info);
  493. static int memory_test(SLMP_INFO *info);
  494. static void reset_adapter(SLMP_INFO *info);
  495. static void reset_port(SLMP_INFO *info);
  496. static void async_mode(SLMP_INFO *info);
  497. static void hdlc_mode(SLMP_INFO *info);
  498. static void rx_stop(SLMP_INFO *info);
  499. static void rx_start(SLMP_INFO *info);
  500. static void rx_reset_buffers(SLMP_INFO *info);
  501. static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
  502. static int rx_get_frame(SLMP_INFO *info);
  503. static void tx_start(SLMP_INFO *info);
  504. static void tx_stop(SLMP_INFO *info);
  505. static void tx_load_fifo(SLMP_INFO *info);
  506. static void tx_set_idle(SLMP_INFO *info);
  507. static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
  508. static void get_signals(SLMP_INFO *info);
  509. static void set_signals(SLMP_INFO *info);
  510. static void enable_loopback(SLMP_INFO *info, int enable);
  511. static void set_rate(SLMP_INFO *info, u32 data_rate);
  512. static int bh_action(SLMP_INFO *info);
  513. static void bh_handler(struct work_struct *work);
  514. static void bh_receive(SLMP_INFO *info);
  515. static void bh_transmit(SLMP_INFO *info);
  516. static void bh_status(SLMP_INFO *info);
  517. static void isr_timer(SLMP_INFO *info);
  518. static void isr_rxint(SLMP_INFO *info);
  519. static void isr_rxrdy(SLMP_INFO *info);
  520. static void isr_txint(SLMP_INFO *info);
  521. static void isr_txrdy(SLMP_INFO *info);
  522. static void isr_rxdmaok(SLMP_INFO *info);
  523. static void isr_rxdmaerror(SLMP_INFO *info);
  524. static void isr_txdmaok(SLMP_INFO *info);
  525. static void isr_txdmaerror(SLMP_INFO *info);
  526. static void isr_io_pin(SLMP_INFO *info, u16 status);
  527. static int alloc_dma_bufs(SLMP_INFO *info);
  528. static void free_dma_bufs(SLMP_INFO *info);
  529. static int alloc_buf_list(SLMP_INFO *info);
  530. static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
  531. static int alloc_tmp_rx_buf(SLMP_INFO *info);
  532. static void free_tmp_rx_buf(SLMP_INFO *info);
  533. static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
  534. static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
  535. static void tx_timeout(unsigned long context);
  536. static void status_timeout(unsigned long context);
  537. static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
  538. static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
  539. static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
  540. static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
  541. static unsigned char read_status_reg(SLMP_INFO * info);
  542. static void write_control_reg(SLMP_INFO * info);
  543. static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
  544. static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
  545. static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
  546. static u32 misc_ctrl_value = 0x007e4040;
  547. static u32 lcr1_brdr_value = 0x00800028;
  548. static u32 read_ahead_count = 8;
  549. /* DPCR, DMA Priority Control
  550. *
  551. * 07..05 Not used, must be 0
  552. * 04 BRC, bus release condition: 0=all transfers complete
  553. * 1=release after 1 xfer on all channels
  554. * 03 CCC, channel change condition: 0=every cycle
  555. * 1=after each channel completes all xfers
  556. * 02..00 PR<2..0>, priority 100=round robin
  557. *
  558. * 00000100 = 0x00
  559. */
  560. static unsigned char dma_priority = 0x04;
  561. // Number of bytes that can be written to shared RAM
  562. // in a single write operation
  563. static u32 sca_pci_load_interval = 64;
  564. /*
  565. * 1st function defined in .text section. Calling this function in
  566. * init_module() followed by a breakpoint allows a remote debugger
  567. * (gdb) to get the .text address for the add-symbol-file command.
  568. * This allows remote debugging of dynamically loadable modules.
  569. */
  570. static void* synclinkmp_get_text_ptr(void);
  571. static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
  572. static inline int sanity_check(SLMP_INFO *info,
  573. char *name, const char *routine)
  574. {
  575. #ifdef SANITY_CHECK
  576. static const char *badmagic =
  577. "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
  578. static const char *badinfo =
  579. "Warning: null synclinkmp_struct for (%s) in %s\n";
  580. if (!info) {
  581. printk(badinfo, name, routine);
  582. return 1;
  583. }
  584. if (info->magic != MGSL_MAGIC) {
  585. printk(badmagic, name, routine);
  586. return 1;
  587. }
  588. #else
  589. if (!info)
  590. return 1;
  591. #endif
  592. return 0;
  593. }
  594. /**
  595. * line discipline callback wrappers
  596. *
  597. * The wrappers maintain line discipline references
  598. * while calling into the line discipline.
  599. *
  600. * ldisc_receive_buf - pass receive data to line discipline
  601. */
  602. static void ldisc_receive_buf(struct tty_struct *tty,
  603. const __u8 *data, char *flags, int count)
  604. {
  605. struct tty_ldisc *ld;
  606. if (!tty)
  607. return;
  608. ld = tty_ldisc_ref(tty);
  609. if (ld) {
  610. if (ld->receive_buf)
  611. ld->receive_buf(tty, data, flags, count);
  612. tty_ldisc_deref(ld);
  613. }
  614. }
  615. /* tty callbacks */
  616. /* Called when a port is opened. Init and enable port.
  617. */
  618. static int open(struct tty_struct *tty, struct file *filp)
  619. {
  620. SLMP_INFO *info;
  621. int retval, line;
  622. unsigned long flags;
  623. line = tty->index;
  624. if ((line < 0) || (line >= synclinkmp_device_count)) {
  625. printk("%s(%d): open with invalid line #%d.\n",
  626. __FILE__,__LINE__,line);
  627. return -ENODEV;
  628. }
  629. info = synclinkmp_device_list;
  630. while(info && info->line != line)
  631. info = info->next_device;
  632. if (sanity_check(info, tty->name, "open"))
  633. return -ENODEV;
  634. if ( info->init_error ) {
  635. printk("%s(%d):%s device is not allocated, init error=%d\n",
  636. __FILE__,__LINE__,info->device_name,info->init_error);
  637. return -ENODEV;
  638. }
  639. tty->driver_data = info;
  640. info->tty = tty;
  641. if (debug_level >= DEBUG_LEVEL_INFO)
  642. printk("%s(%d):%s open(), old ref count = %d\n",
  643. __FILE__,__LINE__,tty->driver->name, info->count);
  644. /* If port is closing, signal caller to try again */
  645. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  646. if (info->flags & ASYNC_CLOSING)
  647. interruptible_sleep_on(&info->close_wait);
  648. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  649. -EAGAIN : -ERESTARTSYS);
  650. goto cleanup;
  651. }
  652. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  653. spin_lock_irqsave(&info->netlock, flags);
  654. if (info->netcount) {
  655. retval = -EBUSY;
  656. spin_unlock_irqrestore(&info->netlock, flags);
  657. goto cleanup;
  658. }
  659. info->count++;
  660. spin_unlock_irqrestore(&info->netlock, flags);
  661. if (info->count == 1) {
  662. /* 1st open on this device, init hardware */
  663. retval = startup(info);
  664. if (retval < 0)
  665. goto cleanup;
  666. }
  667. retval = block_til_ready(tty, filp, info);
  668. if (retval) {
  669. if (debug_level >= DEBUG_LEVEL_INFO)
  670. printk("%s(%d):%s block_til_ready() returned %d\n",
  671. __FILE__,__LINE__, info->device_name, retval);
  672. goto cleanup;
  673. }
  674. if (debug_level >= DEBUG_LEVEL_INFO)
  675. printk("%s(%d):%s open() success\n",
  676. __FILE__,__LINE__, info->device_name);
  677. retval = 0;
  678. cleanup:
  679. if (retval) {
  680. if (tty->count == 1)
  681. info->tty = NULL; /* tty layer will release tty struct */
  682. if(info->count)
  683. info->count--;
  684. }
  685. return retval;
  686. }
  687. /* Called when port is closed. Wait for remaining data to be
  688. * sent. Disable port and free resources.
  689. */
  690. static void close(struct tty_struct *tty, struct file *filp)
  691. {
  692. SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
  693. if (sanity_check(info, tty->name, "close"))
  694. return;
  695. if (debug_level >= DEBUG_LEVEL_INFO)
  696. printk("%s(%d):%s close() entry, count=%d\n",
  697. __FILE__,__LINE__, info->device_name, info->count);
  698. if (!info->count)
  699. return;
  700. if (tty_hung_up_p(filp))
  701. goto cleanup;
  702. if ((tty->count == 1) && (info->count != 1)) {
  703. /*
  704. * tty->count is 1 and the tty structure will be freed.
  705. * info->count should be one in this case.
  706. * if it's not, correct it so that the port is shutdown.
  707. */
  708. printk("%s(%d):%s close: bad refcount; tty->count is 1, "
  709. "info->count is %d\n",
  710. __FILE__,__LINE__, info->device_name, info->count);
  711. info->count = 1;
  712. }
  713. info->count--;
  714. /* if at least one open remaining, leave hardware active */
  715. if (info->count)
  716. goto cleanup;
  717. info->flags |= ASYNC_CLOSING;
  718. /* set tty->closing to notify line discipline to
  719. * only process XON/XOFF characters. Only the N_TTY
  720. * discipline appears to use this (ppp does not).
  721. */
  722. tty->closing = 1;
  723. /* wait for transmit data to clear all layers */
  724. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  725. if (debug_level >= DEBUG_LEVEL_INFO)
  726. printk("%s(%d):%s close() calling tty_wait_until_sent\n",
  727. __FILE__,__LINE__, info->device_name );
  728. tty_wait_until_sent(tty, info->closing_wait);
  729. }
  730. if (info->flags & ASYNC_INITIALIZED)
  731. wait_until_sent(tty, info->timeout);
  732. if (tty->driver->flush_buffer)
  733. tty->driver->flush_buffer(tty);
  734. tty_ldisc_flush(tty);
  735. shutdown(info);
  736. tty->closing = 0;
  737. info->tty = NULL;
  738. if (info->blocked_open) {
  739. if (info->close_delay) {
  740. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  741. }
  742. wake_up_interruptible(&info->open_wait);
  743. }
  744. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  745. wake_up_interruptible(&info->close_wait);
  746. cleanup:
  747. if (debug_level >= DEBUG_LEVEL_INFO)
  748. printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
  749. tty->driver->name, info->count);
  750. }
  751. /* Called by tty_hangup() when a hangup is signaled.
  752. * This is the same as closing all open descriptors for the port.
  753. */
  754. static void hangup(struct tty_struct *tty)
  755. {
  756. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  757. if (debug_level >= DEBUG_LEVEL_INFO)
  758. printk("%s(%d):%s hangup()\n",
  759. __FILE__,__LINE__, info->device_name );
  760. if (sanity_check(info, tty->name, "hangup"))
  761. return;
  762. flush_buffer(tty);
  763. shutdown(info);
  764. info->count = 0;
  765. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  766. info->tty = NULL;
  767. wake_up_interruptible(&info->open_wait);
  768. }
  769. /* Set new termios settings
  770. */
  771. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  772. {
  773. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  774. unsigned long flags;
  775. if (debug_level >= DEBUG_LEVEL_INFO)
  776. printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
  777. tty->driver->name );
  778. /* just return if nothing has changed */
  779. if ((tty->termios->c_cflag == old_termios->c_cflag)
  780. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  781. == RELEVANT_IFLAG(old_termios->c_iflag)))
  782. return;
  783. change_params(info);
  784. /* Handle transition to B0 status */
  785. if (old_termios->c_cflag & CBAUD &&
  786. !(tty->termios->c_cflag & CBAUD)) {
  787. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  788. spin_lock_irqsave(&info->lock,flags);
  789. set_signals(info);
  790. spin_unlock_irqrestore(&info->lock,flags);
  791. }
  792. /* Handle transition away from B0 status */
  793. if (!(old_termios->c_cflag & CBAUD) &&
  794. tty->termios->c_cflag & CBAUD) {
  795. info->serial_signals |= SerialSignal_DTR;
  796. if (!(tty->termios->c_cflag & CRTSCTS) ||
  797. !test_bit(TTY_THROTTLED, &tty->flags)) {
  798. info->serial_signals |= SerialSignal_RTS;
  799. }
  800. spin_lock_irqsave(&info->lock,flags);
  801. set_signals(info);
  802. spin_unlock_irqrestore(&info->lock,flags);
  803. }
  804. /* Handle turning off CRTSCTS */
  805. if (old_termios->c_cflag & CRTSCTS &&
  806. !(tty->termios->c_cflag & CRTSCTS)) {
  807. tty->hw_stopped = 0;
  808. tx_release(tty);
  809. }
  810. }
  811. /* Send a block of data
  812. *
  813. * Arguments:
  814. *
  815. * tty pointer to tty information structure
  816. * buf pointer to buffer containing send data
  817. * count size of send data in bytes
  818. *
  819. * Return Value: number of characters written
  820. */
  821. static int write(struct tty_struct *tty,
  822. const unsigned char *buf, int count)
  823. {
  824. int c, ret = 0;
  825. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  826. unsigned long flags;
  827. if (debug_level >= DEBUG_LEVEL_INFO)
  828. printk("%s(%d):%s write() count=%d\n",
  829. __FILE__,__LINE__,info->device_name,count);
  830. if (sanity_check(info, tty->name, "write"))
  831. goto cleanup;
  832. if (!info->tx_buf)
  833. goto cleanup;
  834. if (info->params.mode == MGSL_MODE_HDLC) {
  835. if (count > info->max_frame_size) {
  836. ret = -EIO;
  837. goto cleanup;
  838. }
  839. if (info->tx_active)
  840. goto cleanup;
  841. if (info->tx_count) {
  842. /* send accumulated data from send_char() calls */
  843. /* as frame and wait before accepting more data. */
  844. tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
  845. goto start;
  846. }
  847. ret = info->tx_count = count;
  848. tx_load_dma_buffer(info, buf, count);
  849. goto start;
  850. }
  851. for (;;) {
  852. c = min_t(int, count,
  853. min(info->max_frame_size - info->tx_count - 1,
  854. info->max_frame_size - info->tx_put));
  855. if (c <= 0)
  856. break;
  857. memcpy(info->tx_buf + info->tx_put, buf, c);
  858. spin_lock_irqsave(&info->lock,flags);
  859. info->tx_put += c;
  860. if (info->tx_put >= info->max_frame_size)
  861. info->tx_put -= info->max_frame_size;
  862. info->tx_count += c;
  863. spin_unlock_irqrestore(&info->lock,flags);
  864. buf += c;
  865. count -= c;
  866. ret += c;
  867. }
  868. if (info->params.mode == MGSL_MODE_HDLC) {
  869. if (count) {
  870. ret = info->tx_count = 0;
  871. goto cleanup;
  872. }
  873. tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
  874. }
  875. start:
  876. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  877. spin_lock_irqsave(&info->lock,flags);
  878. if (!info->tx_active)
  879. tx_start(info);
  880. spin_unlock_irqrestore(&info->lock,flags);
  881. }
  882. cleanup:
  883. if (debug_level >= DEBUG_LEVEL_INFO)
  884. printk( "%s(%d):%s write() returning=%d\n",
  885. __FILE__,__LINE__,info->device_name,ret);
  886. return ret;
  887. }
  888. /* Add a character to the transmit buffer.
  889. */
  890. static void put_char(struct tty_struct *tty, unsigned char ch)
  891. {
  892. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  893. unsigned long flags;
  894. if ( debug_level >= DEBUG_LEVEL_INFO ) {
  895. printk( "%s(%d):%s put_char(%d)\n",
  896. __FILE__,__LINE__,info->device_name,ch);
  897. }
  898. if (sanity_check(info, tty->name, "put_char"))
  899. return;
  900. if (!info->tx_buf)
  901. return;
  902. spin_lock_irqsave(&info->lock,flags);
  903. if ( (info->params.mode != MGSL_MODE_HDLC) ||
  904. !info->tx_active ) {
  905. if (info->tx_count < info->max_frame_size - 1) {
  906. info->tx_buf[info->tx_put++] = ch;
  907. if (info->tx_put >= info->max_frame_size)
  908. info->tx_put -= info->max_frame_size;
  909. info->tx_count++;
  910. }
  911. }
  912. spin_unlock_irqrestore(&info->lock,flags);
  913. }
  914. /* Send a high-priority XON/XOFF character
  915. */
  916. static void send_xchar(struct tty_struct *tty, char ch)
  917. {
  918. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  919. unsigned long flags;
  920. if (debug_level >= DEBUG_LEVEL_INFO)
  921. printk("%s(%d):%s send_xchar(%d)\n",
  922. __FILE__,__LINE__, info->device_name, ch );
  923. if (sanity_check(info, tty->name, "send_xchar"))
  924. return;
  925. info->x_char = ch;
  926. if (ch) {
  927. /* Make sure transmit interrupts are on */
  928. spin_lock_irqsave(&info->lock,flags);
  929. if (!info->tx_enabled)
  930. tx_start(info);
  931. spin_unlock_irqrestore(&info->lock,flags);
  932. }
  933. }
  934. /* Wait until the transmitter is empty.
  935. */
  936. static void wait_until_sent(struct tty_struct *tty, int timeout)
  937. {
  938. SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
  939. unsigned long orig_jiffies, char_time;
  940. if (!info )
  941. return;
  942. if (debug_level >= DEBUG_LEVEL_INFO)
  943. printk("%s(%d):%s wait_until_sent() entry\n",
  944. __FILE__,__LINE__, info->device_name );
  945. if (sanity_check(info, tty->name, "wait_until_sent"))
  946. return;
  947. if (!(info->flags & ASYNC_INITIALIZED))
  948. goto exit;
  949. orig_jiffies = jiffies;
  950. /* Set check interval to 1/5 of estimated time to
  951. * send a character, and make it at least 1. The check
  952. * interval should also be less than the timeout.
  953. * Note: use tight timings here to satisfy the NIST-PCTS.
  954. */
  955. if ( info->params.data_rate ) {
  956. char_time = info->timeout/(32 * 5);
  957. if (!char_time)
  958. char_time++;
  959. } else
  960. char_time = 1;
  961. if (timeout)
  962. char_time = min_t(unsigned long, char_time, timeout);
  963. if ( info->params.mode == MGSL_MODE_HDLC ) {
  964. while (info->tx_active) {
  965. msleep_interruptible(jiffies_to_msecs(char_time));
  966. if (signal_pending(current))
  967. break;
  968. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  969. break;
  970. }
  971. } else {
  972. //TODO: determine if there is something similar to USC16C32
  973. // TXSTATUS_ALL_SENT status
  974. while ( info->tx_active && info->tx_enabled) {
  975. msleep_interruptible(jiffies_to_msecs(char_time));
  976. if (signal_pending(current))
  977. break;
  978. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  979. break;
  980. }
  981. }
  982. exit:
  983. if (debug_level >= DEBUG_LEVEL_INFO)
  984. printk("%s(%d):%s wait_until_sent() exit\n",
  985. __FILE__,__LINE__, info->device_name );
  986. }
  987. /* Return the count of free bytes in transmit buffer
  988. */
  989. static int write_room(struct tty_struct *tty)
  990. {
  991. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  992. int ret;
  993. if (sanity_check(info, tty->name, "write_room"))
  994. return 0;
  995. if (info->params.mode == MGSL_MODE_HDLC) {
  996. ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
  997. } else {
  998. ret = info->max_frame_size - info->tx_count - 1;
  999. if (ret < 0)
  1000. ret = 0;
  1001. }
  1002. if (debug_level >= DEBUG_LEVEL_INFO)
  1003. printk("%s(%d):%s write_room()=%d\n",
  1004. __FILE__, __LINE__, info->device_name, ret);
  1005. return ret;
  1006. }
  1007. /* enable transmitter and send remaining buffered characters
  1008. */
  1009. static void flush_chars(struct tty_struct *tty)
  1010. {
  1011. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1012. unsigned long flags;
  1013. if ( debug_level >= DEBUG_LEVEL_INFO )
  1014. printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
  1015. __FILE__,__LINE__,info->device_name,info->tx_count);
  1016. if (sanity_check(info, tty->name, "flush_chars"))
  1017. return;
  1018. if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
  1019. !info->tx_buf)
  1020. return;
  1021. if ( debug_level >= DEBUG_LEVEL_INFO )
  1022. printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
  1023. __FILE__,__LINE__,info->device_name );
  1024. spin_lock_irqsave(&info->lock,flags);
  1025. if (!info->tx_active) {
  1026. if ( (info->params.mode == MGSL_MODE_HDLC) &&
  1027. info->tx_count ) {
  1028. /* operating in synchronous (frame oriented) mode */
  1029. /* copy data from circular tx_buf to */
  1030. /* transmit DMA buffer. */
  1031. tx_load_dma_buffer(info,
  1032. info->tx_buf,info->tx_count);
  1033. }
  1034. tx_start(info);
  1035. }
  1036. spin_unlock_irqrestore(&info->lock,flags);
  1037. }
  1038. /* Discard all data in the send buffer
  1039. */
  1040. static void flush_buffer(struct tty_struct *tty)
  1041. {
  1042. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1043. unsigned long flags;
  1044. if (debug_level >= DEBUG_LEVEL_INFO)
  1045. printk("%s(%d):%s flush_buffer() entry\n",
  1046. __FILE__,__LINE__, info->device_name );
  1047. if (sanity_check(info, tty->name, "flush_buffer"))
  1048. return;
  1049. spin_lock_irqsave(&info->lock,flags);
  1050. info->tx_count = info->tx_put = info->tx_get = 0;
  1051. del_timer(&info->tx_timer);
  1052. spin_unlock_irqrestore(&info->lock,flags);
  1053. tty_wakeup(tty);
  1054. }
  1055. /* throttle (stop) transmitter
  1056. */
  1057. static void tx_hold(struct tty_struct *tty)
  1058. {
  1059. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1060. unsigned long flags;
  1061. if (sanity_check(info, tty->name, "tx_hold"))
  1062. return;
  1063. if ( debug_level >= DEBUG_LEVEL_INFO )
  1064. printk("%s(%d):%s tx_hold()\n",
  1065. __FILE__,__LINE__,info->device_name);
  1066. spin_lock_irqsave(&info->lock,flags);
  1067. if (info->tx_enabled)
  1068. tx_stop(info);
  1069. spin_unlock_irqrestore(&info->lock,flags);
  1070. }
  1071. /* release (start) transmitter
  1072. */
  1073. static void tx_release(struct tty_struct *tty)
  1074. {
  1075. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1076. unsigned long flags;
  1077. if (sanity_check(info, tty->name, "tx_release"))
  1078. return;
  1079. if ( debug_level >= DEBUG_LEVEL_INFO )
  1080. printk("%s(%d):%s tx_release()\n",
  1081. __FILE__,__LINE__,info->device_name);
  1082. spin_lock_irqsave(&info->lock,flags);
  1083. if (!info->tx_enabled)
  1084. tx_start(info);
  1085. spin_unlock_irqrestore(&info->lock,flags);
  1086. }
  1087. /* Service an IOCTL request
  1088. *
  1089. * Arguments:
  1090. *
  1091. * tty pointer to tty instance data
  1092. * file pointer to associated file object for device
  1093. * cmd IOCTL command code
  1094. * arg command argument/context
  1095. *
  1096. * Return Value: 0 if success, otherwise error code
  1097. */
  1098. static int ioctl(struct tty_struct *tty, struct file *file,
  1099. unsigned int cmd, unsigned long arg)
  1100. {
  1101. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1102. int error;
  1103. struct mgsl_icount cnow; /* kernel counter temps */
  1104. struct serial_icounter_struct __user *p_cuser; /* user space */
  1105. unsigned long flags;
  1106. void __user *argp = (void __user *)arg;
  1107. if (debug_level >= DEBUG_LEVEL_INFO)
  1108. printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
  1109. info->device_name, cmd );
  1110. if (sanity_check(info, tty->name, "ioctl"))
  1111. return -ENODEV;
  1112. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1113. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1114. if (tty->flags & (1 << TTY_IO_ERROR))
  1115. return -EIO;
  1116. }
  1117. switch (cmd) {
  1118. case MGSL_IOCGPARAMS:
  1119. return get_params(info, argp);
  1120. case MGSL_IOCSPARAMS:
  1121. return set_params(info, argp);
  1122. case MGSL_IOCGTXIDLE:
  1123. return get_txidle(info, argp);
  1124. case MGSL_IOCSTXIDLE:
  1125. return set_txidle(info, (int)arg);
  1126. case MGSL_IOCTXENABLE:
  1127. return tx_enable(info, (int)arg);
  1128. case MGSL_IOCRXENABLE:
  1129. return rx_enable(info, (int)arg);
  1130. case MGSL_IOCTXABORT:
  1131. return tx_abort(info);
  1132. case MGSL_IOCGSTATS:
  1133. return get_stats(info, argp);
  1134. case MGSL_IOCWAITEVENT:
  1135. return wait_mgsl_event(info, argp);
  1136. case MGSL_IOCLOOPTXDONE:
  1137. return 0; // TODO: Not supported, need to document
  1138. /* Wait for modem input (DCD,RI,DSR,CTS) change
  1139. * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
  1140. */
  1141. case TIOCMIWAIT:
  1142. return modem_input_wait(info,(int)arg);
  1143. /*
  1144. * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
  1145. * Return: write counters to the user passed counter struct
  1146. * NB: both 1->0 and 0->1 transitions are counted except for
  1147. * RI where only 0->1 is counted.
  1148. */
  1149. case TIOCGICOUNT:
  1150. spin_lock_irqsave(&info->lock,flags);
  1151. cnow = info->icount;
  1152. spin_unlock_irqrestore(&info->lock,flags);
  1153. p_cuser = argp;
  1154. PUT_USER(error,cnow.cts, &p_cuser->cts);
  1155. if (error) return error;
  1156. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  1157. if (error) return error;
  1158. PUT_USER(error,cnow.rng, &p_cuser->rng);
  1159. if (error) return error;
  1160. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  1161. if (error) return error;
  1162. PUT_USER(error,cnow.rx, &p_cuser->rx);
  1163. if (error) return error;
  1164. PUT_USER(error,cnow.tx, &p_cuser->tx);
  1165. if (error) return error;
  1166. PUT_USER(error,cnow.frame, &p_cuser->frame);
  1167. if (error) return error;
  1168. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  1169. if (error) return error;
  1170. PUT_USER(error,cnow.parity, &p_cuser->parity);
  1171. if (error) return error;
  1172. PUT_USER(error,cnow.brk, &p_cuser->brk);
  1173. if (error) return error;
  1174. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  1175. if (error) return error;
  1176. return 0;
  1177. default:
  1178. return -ENOIOCTLCMD;
  1179. }
  1180. return 0;
  1181. }
  1182. /*
  1183. * /proc fs routines....
  1184. */
  1185. static inline int line_info(char *buf, SLMP_INFO *info)
  1186. {
  1187. char stat_buf[30];
  1188. int ret;
  1189. unsigned long flags;
  1190. ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
  1191. "\tIRQ=%d MaxFrameSize=%u\n",
  1192. info->device_name,
  1193. info->phys_sca_base,
  1194. info->phys_memory_base,
  1195. info->phys_statctrl_base,
  1196. info->phys_lcr_base,
  1197. info->irq_level,
  1198. info->max_frame_size );
  1199. /* output current serial signal states */
  1200. spin_lock_irqsave(&info->lock,flags);
  1201. get_signals(info);
  1202. spin_unlock_irqrestore(&info->lock,flags);
  1203. stat_buf[0] = 0;
  1204. stat_buf[1] = 0;
  1205. if (info->serial_signals & SerialSignal_RTS)
  1206. strcat(stat_buf, "|RTS");
  1207. if (info->serial_signals & SerialSignal_CTS)
  1208. strcat(stat_buf, "|CTS");
  1209. if (info->serial_signals & SerialSignal_DTR)
  1210. strcat(stat_buf, "|DTR");
  1211. if (info->serial_signals & SerialSignal_DSR)
  1212. strcat(stat_buf, "|DSR");
  1213. if (info->serial_signals & SerialSignal_DCD)
  1214. strcat(stat_buf, "|CD");
  1215. if (info->serial_signals & SerialSignal_RI)
  1216. strcat(stat_buf, "|RI");
  1217. if (info->params.mode == MGSL_MODE_HDLC) {
  1218. ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
  1219. info->icount.txok, info->icount.rxok);
  1220. if (info->icount.txunder)
  1221. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  1222. if (info->icount.txabort)
  1223. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  1224. if (info->icount.rxshort)
  1225. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  1226. if (info->icount.rxlong)
  1227. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  1228. if (info->icount.rxover)
  1229. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  1230. if (info->icount.rxcrc)
  1231. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
  1232. } else {
  1233. ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
  1234. info->icount.tx, info->icount.rx);
  1235. if (info->icount.frame)
  1236. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  1237. if (info->icount.parity)
  1238. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  1239. if (info->icount.brk)
  1240. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  1241. if (info->icount.overrun)
  1242. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  1243. }
  1244. /* Append serial signal status to end */
  1245. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  1246. ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  1247. info->tx_active,info->bh_requested,info->bh_running,
  1248. info->pending_bh);
  1249. return ret;
  1250. }
  1251. /* Called to print information about devices
  1252. */
  1253. int read_proc(char *page, char **start, off_t off, int count,
  1254. int *eof, void *data)
  1255. {
  1256. int len = 0, l;
  1257. off_t begin = 0;
  1258. SLMP_INFO *info;
  1259. len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
  1260. info = synclinkmp_device_list;
  1261. while( info ) {
  1262. l = line_info(page + len, info);
  1263. len += l;
  1264. if (len+begin > off+count)
  1265. goto done;
  1266. if (len+begin < off) {
  1267. begin += len;
  1268. len = 0;
  1269. }
  1270. info = info->next_device;
  1271. }
  1272. *eof = 1;
  1273. done:
  1274. if (off >= len+begin)
  1275. return 0;
  1276. *start = page + (off-begin);
  1277. return ((count < begin+len-off) ? count : begin+len-off);
  1278. }
  1279. /* Return the count of bytes in transmit buffer
  1280. */
  1281. static int chars_in_buffer(struct tty_struct *tty)
  1282. {
  1283. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1284. if (sanity_check(info, tty->name, "chars_in_buffer"))
  1285. return 0;
  1286. if (debug_level >= DEBUG_LEVEL_INFO)
  1287. printk("%s(%d):%s chars_in_buffer()=%d\n",
  1288. __FILE__, __LINE__, info->device_name, info->tx_count);
  1289. return info->tx_count;
  1290. }
  1291. /* Signal remote device to throttle send data (our receive data)
  1292. */
  1293. static void throttle(struct tty_struct * tty)
  1294. {
  1295. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1296. unsigned long flags;
  1297. if (debug_level >= DEBUG_LEVEL_INFO)
  1298. printk("%s(%d):%s throttle() entry\n",
  1299. __FILE__,__LINE__, info->device_name );
  1300. if (sanity_check(info, tty->name, "throttle"))
  1301. return;
  1302. if (I_IXOFF(tty))
  1303. send_xchar(tty, STOP_CHAR(tty));
  1304. if (tty->termios->c_cflag & CRTSCTS) {
  1305. spin_lock_irqsave(&info->lock,flags);
  1306. info->serial_signals &= ~SerialSignal_RTS;
  1307. set_signals(info);
  1308. spin_unlock_irqrestore(&info->lock,flags);
  1309. }
  1310. }
  1311. /* Signal remote device to stop throttling send data (our receive data)
  1312. */
  1313. static void unthrottle(struct tty_struct * tty)
  1314. {
  1315. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  1316. unsigned long flags;
  1317. if (debug_level >= DEBUG_LEVEL_INFO)
  1318. printk("%s(%d):%s unthrottle() entry\n",
  1319. __FILE__,__LINE__, info->device_name );
  1320. if (sanity_check(info, tty->name, "unthrottle"))
  1321. return;
  1322. if (I_IXOFF(tty)) {
  1323. if (info->x_char)
  1324. info->x_char = 0;
  1325. else
  1326. send_xchar(tty, START_CHAR(tty));
  1327. }
  1328. if (tty->termios->c_cflag & CRTSCTS) {
  1329. spin_lock_irqsave(&info->lock,flags);
  1330. info->serial_signals |= SerialSignal_RTS;
  1331. set_signals(info);
  1332. spin_unlock_irqrestore(&info->lock,flags);
  1333. }
  1334. }
  1335. /* set or clear transmit break condition
  1336. * break_state -1=set break condition, 0=clear
  1337. */
  1338. static void set_break(struct tty_struct *tty, int break_state)
  1339. {
  1340. unsigned char RegValue;
  1341. SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
  1342. unsigned long flags;
  1343. if (debug_level >= DEBUG_LEVEL_INFO)
  1344. printk("%s(%d):%s set_break(%d)\n",
  1345. __FILE__,__LINE__, info->device_name, break_state);
  1346. if (sanity_check(info, tty->name, "set_break"))
  1347. return;
  1348. spin_lock_irqsave(&info->lock,flags);
  1349. RegValue = read_reg(info, CTL);
  1350. if (break_state == -1)
  1351. RegValue |= BIT3;
  1352. else
  1353. RegValue &= ~BIT3;
  1354. write_reg(info, CTL, RegValue);
  1355. spin_unlock_irqrestore(&info->lock,flags);
  1356. }
  1357. #if SYNCLINK_GENERIC_HDLC
  1358. /**
  1359. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  1360. * set encoding and frame check sequence (FCS) options
  1361. *
  1362. * dev pointer to network device structure
  1363. * encoding serial encoding setting
  1364. * parity FCS setting
  1365. *
  1366. * returns 0 if success, otherwise error code
  1367. */
  1368. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  1369. unsigned short parity)
  1370. {
  1371. SLMP_INFO *info = dev_to_port(dev);
  1372. unsigned char new_encoding;
  1373. unsigned short new_crctype;
  1374. /* return error if TTY interface open */
  1375. if (info->count)
  1376. return -EBUSY;
  1377. switch (encoding)
  1378. {
  1379. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  1380. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  1381. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  1382. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  1383. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  1384. default: return -EINVAL;
  1385. }
  1386. switch (parity)
  1387. {
  1388. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  1389. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  1390. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  1391. default: return -EINVAL;
  1392. }
  1393. info->params.encoding = new_encoding;
  1394. info->params.crc_type = new_crctype;
  1395. /* if network interface up, reprogram hardware */
  1396. if (info->netcount)
  1397. program_hw(info);
  1398. return 0;
  1399. }
  1400. /**
  1401. * called by generic HDLC layer to send frame
  1402. *
  1403. * skb socket buffer containing HDLC frame
  1404. * dev pointer to network device structure
  1405. *
  1406. * returns 0 if success, otherwise error code
  1407. */
  1408. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  1409. {
  1410. SLMP_INFO *info = dev_to_port(dev);
  1411. struct net_device_stats *stats = hdlc_stats(dev);
  1412. unsigned long flags;
  1413. if (debug_level >= DEBUG_LEVEL_INFO)
  1414. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  1415. /* stop sending until this frame completes */
  1416. netif_stop_queue(dev);
  1417. /* copy data to device buffers */
  1418. info->tx_count = skb->len;
  1419. tx_load_dma_buffer(info, skb->data, skb->len);
  1420. /* update network statistics */
  1421. stats->tx_packets++;
  1422. stats->tx_bytes += skb->len;
  1423. /* done with socket buffer, so free it */
  1424. dev_kfree_skb(skb);
  1425. /* save start time for transmit timeout detection */
  1426. dev->trans_start = jiffies;
  1427. /* start hardware transmitter if necessary */
  1428. spin_lock_irqsave(&info->lock,flags);
  1429. if (!info->tx_active)
  1430. tx_start(info);
  1431. spin_unlock_irqrestore(&info->lock,flags);
  1432. return 0;
  1433. }
  1434. /**
  1435. * called by network layer when interface enabled
  1436. * claim resources and initialize hardware
  1437. *
  1438. * dev pointer to network device structure
  1439. *
  1440. * returns 0 if success, otherwise error code
  1441. */
  1442. static int hdlcdev_open(struct net_device *dev)
  1443. {
  1444. SLMP_INFO *info = dev_to_port(dev);
  1445. int rc;
  1446. unsigned long flags;
  1447. if (debug_level >= DEBUG_LEVEL_INFO)
  1448. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  1449. /* generic HDLC layer open processing */
  1450. if ((rc = hdlc_open(dev)))
  1451. return rc;
  1452. /* arbitrate between network and tty opens */
  1453. spin_lock_irqsave(&info->netlock, flags);
  1454. if (info->count != 0 || info->netcount != 0) {
  1455. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  1456. spin_unlock_irqrestore(&info->netlock, flags);
  1457. return -EBUSY;
  1458. }
  1459. info->netcount=1;
  1460. spin_unlock_irqrestore(&info->netlock, flags);
  1461. /* claim resources and init adapter */
  1462. if ((rc = startup(info)) != 0) {
  1463. spin_lock_irqsave(&info->netlock, flags);
  1464. info->netcount=0;
  1465. spin_unlock_irqrestore(&info->netlock, flags);
  1466. return rc;
  1467. }
  1468. /* assert DTR and RTS, apply hardware settings */
  1469. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1470. program_hw(info);
  1471. /* enable network layer transmit */
  1472. dev->trans_start = jiffies;
  1473. netif_start_queue(dev);
  1474. /* inform generic HDLC layer of current DCD status */
  1475. spin_lock_irqsave(&info->lock, flags);
  1476. get_signals(info);
  1477. spin_unlock_irqrestore(&info->lock, flags);
  1478. if (info->serial_signals & SerialSignal_DCD)
  1479. netif_carrier_on(dev);
  1480. else
  1481. netif_carrier_off(dev);
  1482. return 0;
  1483. }
  1484. /**
  1485. * called by network layer when interface is disabled
  1486. * shutdown hardware and release resources
  1487. *
  1488. * dev pointer to network device structure
  1489. *
  1490. * returns 0 if success, otherwise error code
  1491. */
  1492. static int hdlcdev_close(struct net_device *dev)
  1493. {
  1494. SLMP_INFO *info = dev_to_port(dev);
  1495. unsigned long flags;
  1496. if (debug_level >= DEBUG_LEVEL_INFO)
  1497. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  1498. netif_stop_queue(dev);
  1499. /* shutdown adapter and release resources */
  1500. shutdown(info);
  1501. hdlc_close(dev);
  1502. spin_lock_irqsave(&info->netlock, flags);
  1503. info->netcount=0;
  1504. spin_unlock_irqrestore(&info->netlock, flags);
  1505. return 0;
  1506. }
  1507. /**
  1508. * called by network layer to process IOCTL call to network device
  1509. *
  1510. * dev pointer to network device structure
  1511. * ifr pointer to network interface request structure
  1512. * cmd IOCTL command code
  1513. *
  1514. * returns 0 if success, otherwise error code
  1515. */
  1516. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1517. {
  1518. const size_t size = sizeof(sync_serial_settings);
  1519. sync_serial_settings new_line;
  1520. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  1521. SLMP_INFO *info = dev_to_port(dev);
  1522. unsigned int flags;
  1523. if (debug_level >= DEBUG_LEVEL_INFO)
  1524. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  1525. /* return error if TTY interface open */
  1526. if (info->count)
  1527. return -EBUSY;
  1528. if (cmd != SIOCWANDEV)
  1529. return hdlc_ioctl(dev, ifr, cmd);
  1530. switch(ifr->ifr_settings.type) {
  1531. case IF_GET_IFACE: /* return current sync_serial_settings */
  1532. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  1533. if (ifr->ifr_settings.size < size) {
  1534. ifr->ifr_settings.size = size; /* data size wanted */
  1535. return -ENOBUFS;
  1536. }
  1537. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1538. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1539. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1540. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1541. switch (flags){
  1542. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  1543. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  1544. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  1545. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  1546. default: new_line.clock_type = CLOCK_DEFAULT;
  1547. }
  1548. new_line.clock_rate = info->params.clock_speed;
  1549. new_line.loopback = info->params.loopback ? 1:0;
  1550. if (copy_to_user(line, &new_line, size))
  1551. return -EFAULT;
  1552. return 0;
  1553. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  1554. if(!capable(CAP_NET_ADMIN))
  1555. return -EPERM;
  1556. if (copy_from_user(&new_line, line, size))
  1557. return -EFAULT;
  1558. switch (new_line.clock_type)
  1559. {
  1560. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  1561. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  1562. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  1563. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  1564. case CLOCK_DEFAULT: flags = info->params.flags &
  1565. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1566. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1567. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1568. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  1569. default: return -EINVAL;
  1570. }
  1571. if (new_line.loopback != 0 && new_line.loopback != 1)
  1572. return -EINVAL;
  1573. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1574. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1575. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1576. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1577. info->params.flags |= flags;
  1578. info->params.loopback = new_line.loopback;
  1579. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  1580. info->params.clock_speed = new_line.clock_rate;
  1581. else
  1582. info->params.clock_speed = 0;
  1583. /* if network interface up, reprogram hardware */
  1584. if (info->netcount)
  1585. program_hw(info);
  1586. return 0;
  1587. default:
  1588. return hdlc_ioctl(dev, ifr, cmd);
  1589. }
  1590. }
  1591. /**
  1592. * called by network layer when transmit timeout is detected
  1593. *
  1594. * dev pointer to network device structure
  1595. */
  1596. static void hdlcdev_tx_timeout(struct net_device *dev)
  1597. {
  1598. SLMP_INFO *info = dev_to_port(dev);
  1599. struct net_device_stats *stats = hdlc_stats(dev);
  1600. unsigned long flags;
  1601. if (debug_level >= DEBUG_LEVEL_INFO)
  1602. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  1603. stats->tx_errors++;
  1604. stats->tx_aborted_errors++;
  1605. spin_lock_irqsave(&info->lock,flags);
  1606. tx_stop(info);
  1607. spin_unlock_irqrestore(&info->lock,flags);
  1608. netif_wake_queue(dev);
  1609. }
  1610. /**
  1611. * called by device driver when transmit completes
  1612. * reenable network layer transmit if stopped
  1613. *
  1614. * info pointer to device instance information
  1615. */
  1616. static void hdlcdev_tx_done(SLMP_INFO *info)
  1617. {
  1618. if (netif_queue_stopped(info->netdev))
  1619. netif_wake_queue(info->netdev);
  1620. }
  1621. /**
  1622. * called by device driver when frame received
  1623. * pass frame to network layer
  1624. *
  1625. * info pointer to device instance information
  1626. * buf pointer to buffer contianing frame data
  1627. * size count of data bytes in buf
  1628. */
  1629. static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
  1630. {
  1631. struct sk_buff *skb = dev_alloc_skb(size);
  1632. struct net_device *dev = info->netdev;
  1633. struct net_device_stats *stats = hdlc_stats(dev);
  1634. if (debug_level >= DEBUG_LEVEL_INFO)
  1635. printk("hdlcdev_rx(%s)\n",dev->name);
  1636. if (skb == NULL) {
  1637. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  1638. stats->rx_dropped++;
  1639. return;
  1640. }
  1641. memcpy(skb_put(skb, size),buf,size);
  1642. skb->protocol = hdlc_type_trans(skb, info->netdev);
  1643. stats->rx_packets++;
  1644. stats->rx_bytes += size;
  1645. netif_rx(skb);
  1646. info->netdev->last_rx = jiffies;
  1647. }
  1648. /**
  1649. * called by device driver when adding device instance
  1650. * do generic HDLC initialization
  1651. *
  1652. * info pointer to device instance information
  1653. *
  1654. * returns 0 if success, otherwise error code
  1655. */
  1656. static int hdlcdev_init(SLMP_INFO *info)
  1657. {
  1658. int rc;
  1659. struct net_device *dev;
  1660. hdlc_device *hdlc;
  1661. /* allocate and initialize network and HDLC layer objects */
  1662. if (!(dev = alloc_hdlcdev(info))) {
  1663. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  1664. return -ENOMEM;
  1665. }
  1666. /* for network layer reporting purposes only */
  1667. dev->mem_start = info->phys_sca_base;
  1668. dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
  1669. dev->irq = info->irq_level;
  1670. /* network layer callbacks and settings */
  1671. dev->do_ioctl = hdlcdev_ioctl;
  1672. dev->open = hdlcdev_open;
  1673. dev->stop = hdlcdev_close;
  1674. dev->tx_timeout = hdlcdev_tx_timeout;
  1675. dev->watchdog_timeo = 10*HZ;
  1676. dev->tx_queue_len = 50;
  1677. /* generic HDLC layer callbacks and settings */
  1678. hdlc = dev_to_hdlc(dev);
  1679. hdlc->attach = hdlcdev_attach;
  1680. hdlc->xmit = hdlcdev_xmit;
  1681. /* register objects with HDLC layer */
  1682. if ((rc = register_hdlc_device(dev))) {
  1683. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  1684. free_netdev(dev);
  1685. return rc;
  1686. }
  1687. info->netdev = dev;
  1688. return 0;
  1689. }
  1690. /**
  1691. * called by device driver when removing device instance
  1692. * do generic HDLC cleanup
  1693. *
  1694. * info pointer to device instance information
  1695. */
  1696. static void hdlcdev_exit(SLMP_INFO *info)
  1697. {
  1698. unregister_hdlc_device(info->netdev);
  1699. free_netdev(info->netdev);
  1700. info->netdev = NULL;
  1701. }
  1702. #endif /* CONFIG_HDLC */
  1703. /* Return next bottom half action to perform.
  1704. * Return Value: BH action code or 0 if nothing to do.
  1705. */
  1706. int bh_action(SLMP_INFO *info)
  1707. {
  1708. unsigned long flags;
  1709. int rc = 0;
  1710. spin_lock_irqsave(&info->lock,flags);
  1711. if (info->pending_bh & BH_RECEIVE) {
  1712. info->pending_bh &= ~BH_RECEIVE;
  1713. rc = BH_RECEIVE;
  1714. } else if (info->pending_bh & BH_TRANSMIT) {
  1715. info->pending_bh &= ~BH_TRANSMIT;
  1716. rc = BH_TRANSMIT;
  1717. } else if (info->pending_bh & BH_STATUS) {
  1718. info->pending_bh &= ~BH_STATUS;
  1719. rc = BH_STATUS;
  1720. }
  1721. if (!rc) {
  1722. /* Mark BH routine as complete */
  1723. info->bh_running = 0;
  1724. info->bh_requested = 0;
  1725. }
  1726. spin_unlock_irqrestore(&info->lock,flags);
  1727. return rc;
  1728. }
  1729. /* Perform bottom half processing of work items queued by ISR.
  1730. */
  1731. void bh_handler(struct work_struct *work)
  1732. {
  1733. SLMP_INFO *info = container_of(work, SLMP_INFO, task);
  1734. int action;
  1735. if (!info)
  1736. return;
  1737. if ( debug_level >= DEBUG_LEVEL_BH )
  1738. printk( "%s(%d):%s bh_handler() entry\n",
  1739. __FILE__,__LINE__,info->device_name);
  1740. info->bh_running = 1;
  1741. while((action = bh_action(info)) != 0) {
  1742. /* Process work item */
  1743. if ( debug_level >= DEBUG_LEVEL_BH )
  1744. printk( "%s(%d):%s bh_handler() work item action=%d\n",
  1745. __FILE__,__LINE__,info->device_name, action);
  1746. switch (action) {
  1747. case BH_RECEIVE:
  1748. bh_receive(info);
  1749. break;
  1750. case BH_TRANSMIT:
  1751. bh_transmit(info);
  1752. break;
  1753. case BH_STATUS:
  1754. bh_status(info);
  1755. break;
  1756. default:
  1757. /* unknown work item ID */
  1758. printk("%s(%d):%s Unknown work item ID=%08X!\n",
  1759. __FILE__,__LINE__,info->device_name,action);
  1760. break;
  1761. }
  1762. }
  1763. if ( debug_level >= DEBUG_LEVEL_BH )
  1764. printk( "%s(%d):%s bh_handler() exit\n",
  1765. __FILE__,__LINE__,info->device_name);
  1766. }
  1767. void bh_receive(SLMP_INFO *info)
  1768. {
  1769. if ( debug_level >= DEBUG_LEVEL_BH )
  1770. printk( "%s(%d):%s bh_receive()\n",
  1771. __FILE__,__LINE__,info->device_name);
  1772. while( rx_get_frame(info) );
  1773. }
  1774. void bh_transmit(SLMP_INFO *info)
  1775. {
  1776. struct tty_struct *tty = info->tty;
  1777. if ( debug_level >= DEBUG_LEVEL_BH )
  1778. printk( "%s(%d):%s bh_transmit() entry\n",
  1779. __FILE__,__LINE__,info->device_name);
  1780. if (tty)
  1781. tty_wakeup(tty);
  1782. }
  1783. void bh_status(SLMP_INFO *info)
  1784. {
  1785. if ( debug_level >= DEBUG_LEVEL_BH )
  1786. printk( "%s(%d):%s bh_status() entry\n",
  1787. __FILE__,__LINE__,info->device_name);
  1788. info->ri_chkcount = 0;
  1789. info->dsr_chkcount = 0;
  1790. info->dcd_chkcount = 0;
  1791. info->cts_chkcount = 0;
  1792. }
  1793. void isr_timer(SLMP_INFO * info)
  1794. {
  1795. unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
  1796. /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
  1797. write_reg(info, IER2, 0);
  1798. /* TMCS, Timer Control/Status Register
  1799. *
  1800. * 07 CMF, Compare match flag (read only) 1=match
  1801. * 06 ECMI, CMF Interrupt Enable: 0=disabled
  1802. * 05 Reserved, must be 0
  1803. * 04 TME, Timer Enable
  1804. * 03..00 Reserved, must be 0
  1805. *
  1806. * 0000 0000
  1807. */
  1808. write_reg(info, (unsigned char)(timer + TMCS), 0);
  1809. info->irq_occurred = TRUE;
  1810. if ( debug_level >= DEBUG_LEVEL_ISR )
  1811. printk("%s(%d):%s isr_timer()\n",
  1812. __FILE__,__LINE__,info->device_name);
  1813. }
  1814. void isr_rxint(SLMP_INFO * info)
  1815. {
  1816. struct tty_struct *tty = info->tty;
  1817. struct mgsl_icount *icount = &info->icount;
  1818. unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
  1819. unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
  1820. /* clear status bits */
  1821. if (status)
  1822. write_reg(info, SR1, status);
  1823. if (status2)
  1824. write_reg(info, SR2, status2);
  1825. if ( debug_level >= DEBUG_LEVEL_ISR )
  1826. printk("%s(%d):%s isr_rxint status=%02X %02x\n",
  1827. __FILE__,__LINE__,info->device_name,status,status2);
  1828. if (info->params.mode == MGSL_MODE_ASYNC) {
  1829. if (status & BRKD) {
  1830. icount->brk++;
  1831. /* process break detection if tty control
  1832. * is not set to ignore it
  1833. */
  1834. if ( tty ) {
  1835. if (!(status & info->ignore_status_mask1)) {
  1836. if (info->read_status_mask1 & BRKD) {
  1837. tty_insert_flip_char(tty, 0, TTY_BREAK);
  1838. if (info->flags & ASYNC_SAK)
  1839. do_SAK(tty);
  1840. }
  1841. }
  1842. }
  1843. }
  1844. }
  1845. else {
  1846. if (status & (FLGD|IDLD)) {
  1847. if (status & FLGD)
  1848. info->icount.exithunt++;
  1849. else if (status & IDLD)
  1850. info->icount.rxidle++;
  1851. wake_up_interruptible(&info->event_wait_q);
  1852. }
  1853. }
  1854. if (status & CDCD) {
  1855. /* simulate a common modem status change interrupt
  1856. * for our handler
  1857. */
  1858. get_signals( info );
  1859. isr_io_pin(info,
  1860. MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
  1861. }
  1862. }
  1863. /*
  1864. * handle async rx data interrupts
  1865. */
  1866. void isr_rxrdy(SLMP_INFO * info)
  1867. {
  1868. u16 status;
  1869. unsigned char DataByte;
  1870. struct tty_struct *tty = info->tty;
  1871. struct mgsl_icount *icount = &info->icount;
  1872. if ( debug_level >= DEBUG_LEVEL_ISR )
  1873. printk("%s(%d):%s isr_rxrdy\n",
  1874. __FILE__,__LINE__,info->device_name);
  1875. while((status = read_reg(info,CST0)) & BIT0)
  1876. {
  1877. int flag = 0;
  1878. int over = 0;
  1879. DataByte = read_reg(info,TRB);
  1880. icount->rx++;
  1881. if ( status & (PE + FRME + OVRN) ) {
  1882. printk("%s(%d):%s rxerr=%04X\n",
  1883. __FILE__,__LINE__,info->device_name,status);
  1884. /* update error statistics */
  1885. if (status & PE)
  1886. icount->parity++;
  1887. else if (status & FRME)
  1888. icount->frame++;
  1889. else if (status & OVRN)
  1890. icount->overrun++;
  1891. /* discard char if tty control flags say so */
  1892. if (status & info->ignore_status_mask2)
  1893. continue;
  1894. status &= info->read_status_mask2;
  1895. if ( tty ) {
  1896. if (status & PE)
  1897. flag = TTY_PARITY;
  1898. else if (status & FRME)
  1899. flag = TTY_FRAME;
  1900. if (status & OVRN) {
  1901. /* Overrun is special, since it's
  1902. * reported immediately, and doesn't
  1903. * affect the current character
  1904. */
  1905. over = 1;
  1906. }
  1907. }
  1908. } /* end of if (error) */
  1909. if ( tty ) {
  1910. tty_insert_flip_char(tty, DataByte, flag);
  1911. if (over)
  1912. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  1913. }
  1914. }
  1915. if ( debug_level >= DEBUG_LEVEL_ISR ) {
  1916. printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  1917. __FILE__,__LINE__,info->device_name,
  1918. icount->rx,icount->brk,icount->parity,
  1919. icount->frame,icount->overrun);
  1920. }
  1921. if ( tty )
  1922. tty_flip_buffer_push(tty);
  1923. }
  1924. static void isr_txeom(SLMP_INFO * info, unsigned char status)
  1925. {
  1926. if ( debug_level >= DEBUG_LEVEL_ISR )
  1927. printk("%s(%d):%s isr_txeom status=%02x\n",
  1928. __FILE__,__LINE__,info->device_name,status);
  1929. write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
  1930. write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
  1931. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  1932. if (status & UDRN) {
  1933. write_reg(info, CMD, TXRESET);
  1934. write_reg(info, CMD, TXENABLE);
  1935. } else
  1936. write_reg(info, CMD, TXBUFCLR);
  1937. /* disable and clear tx interrupts */
  1938. info->ie0_value &= ~TXRDYE;
  1939. info->ie1_value &= ~(IDLE + UDRN);
  1940. write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
  1941. write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
  1942. if ( info->tx_active ) {
  1943. if (info->params.mode != MGSL_MODE_ASYNC) {
  1944. if (status & UDRN)
  1945. info->icount.txunder++;
  1946. else if (status & IDLE)
  1947. info->icount.txok++;
  1948. }
  1949. info->tx_active = 0;
  1950. info->tx_count = info->tx_put = info->tx_get = 0;
  1951. del_timer(&info->tx_timer);
  1952. if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
  1953. info->serial_signals &= ~SerialSignal_RTS;
  1954. info->drop_rts_on_tx_done = 0;
  1955. set_signals(info);
  1956. }
  1957. #if SYNCLINK_GENERIC_HDLC
  1958. if (info->netcount)
  1959. hdlcdev_tx_done(info);
  1960. else
  1961. #endif
  1962. {
  1963. if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
  1964. tx_stop(info);
  1965. return;
  1966. }
  1967. info->pending_bh |= BH_TRANSMIT;
  1968. }
  1969. }
  1970. }
  1971. /*
  1972. * handle tx status interrupts
  1973. */
  1974. void isr_txint(SLMP_INFO * info)
  1975. {
  1976. unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
  1977. /* clear status bits */
  1978. write_reg(info, SR1, status);
  1979. if ( debug_level >= DEBUG_LEVEL_ISR )
  1980. printk("%s(%d):%s isr_txint status=%02x\n",
  1981. __FILE__,__LINE__,info->device_name,status);
  1982. if (status & (UDRN + IDLE))
  1983. isr_txeom(info, status);
  1984. if (status & CCTS) {
  1985. /* simulate a common modem status change interrupt
  1986. * for our handler
  1987. */
  1988. get_signals( info );
  1989. isr_io_pin(info,
  1990. MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
  1991. }
  1992. }
  1993. /*
  1994. * handle async tx data interrupts
  1995. */
  1996. void isr_txrdy(SLMP_INFO * info)
  1997. {
  1998. if ( debug_level >= DEBUG_LEVEL_ISR )
  1999. printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
  2000. __FILE__,__LINE__,info->device_name,info->tx_count);
  2001. if (info->params.mode != MGSL_MODE_ASYNC) {
  2002. /* disable TXRDY IRQ, enable IDLE IRQ */
  2003. info->ie0_value &= ~TXRDYE;
  2004. info->ie1_value |= IDLE;
  2005. write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
  2006. return;
  2007. }
  2008. if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
  2009. tx_stop(info);
  2010. return;
  2011. }
  2012. if ( info->tx_count )
  2013. tx_load_fifo( info );
  2014. else {
  2015. info->tx_active = 0;
  2016. info->ie0_value &= ~TXRDYE;
  2017. write_reg(info, IE0, info->ie0_value);
  2018. }
  2019. if (info->tx_count < WAKEUP_CHARS)
  2020. info->pending_bh |= BH_TRANSMIT;
  2021. }
  2022. void isr_rxdmaok(SLMP_INFO * info)
  2023. {
  2024. /* BIT7 = EOT (end of transfer)
  2025. * BIT6 = EOM (end of message/frame)
  2026. */
  2027. unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
  2028. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  2029. write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
  2030. if ( debug_level >= DEBUG_LEVEL_ISR )
  2031. printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
  2032. __FILE__,__LINE__,info->device_name,status);
  2033. info->pending_bh |= BH_RECEIVE;
  2034. }
  2035. void isr_rxdmaerror(SLMP_INFO * info)
  2036. {
  2037. /* BIT5 = BOF (buffer overflow)
  2038. * BIT4 = COF (counter overflow)
  2039. */
  2040. unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
  2041. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  2042. write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
  2043. if ( debug_level >= DEBUG_LEVEL_ISR )
  2044. printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
  2045. __FILE__,__LINE__,info->device_name,status);
  2046. info->rx_overflow = TRUE;
  2047. info->pending_bh |= BH_RECEIVE;
  2048. }
  2049. void isr_txdmaok(SLMP_INFO * info)
  2050. {
  2051. unsigned char status_reg1 = read_reg(info, SR1);
  2052. write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
  2053. write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
  2054. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  2055. if ( debug_level >= DEBUG_LEVEL_ISR )
  2056. printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
  2057. __FILE__,__LINE__,info->device_name,status_reg1);
  2058. /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
  2059. write_reg16(info, TRC0, 0);
  2060. info->ie0_value |= TXRDYE;
  2061. write_reg(info, IE0, info->ie0_value);
  2062. }
  2063. void isr_txdmaerror(SLMP_INFO * info)
  2064. {
  2065. /* BIT5 = BOF (buffer overflow)
  2066. * BIT4 = COF (counter overflow)
  2067. */
  2068. unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
  2069. /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
  2070. write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
  2071. if ( debug_level >= DEBUG_LEVEL_ISR )
  2072. printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
  2073. __FILE__,__LINE__,info->device_name,status);
  2074. }
  2075. /* handle input serial signal changes
  2076. */
  2077. void isr_io_pin( SLMP_INFO *info, u16 status )
  2078. {
  2079. struct mgsl_icount *icount;
  2080. if ( debug_level >= DEBUG_LEVEL_ISR )
  2081. printk("%s(%d):isr_io_pin status=%04X\n",
  2082. __FILE__,__LINE__,status);
  2083. if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
  2084. MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
  2085. icount = &info->icount;
  2086. /* update input line counters */
  2087. if (status & MISCSTATUS_RI_LATCHED) {
  2088. icount->rng++;
  2089. if ( status & SerialSignal_RI )
  2090. info->input_signal_events.ri_up++;
  2091. else
  2092. info->input_signal_events.ri_down++;
  2093. }
  2094. if (status & MISCSTATUS_DSR_LATCHED) {
  2095. icount->dsr++;
  2096. if ( status & SerialSignal_DSR )
  2097. info->input_signal_events.dsr_up++;
  2098. else
  2099. info->input_signal_events.dsr_down++;
  2100. }
  2101. if (status & MISCSTATUS_DCD_LATCHED) {
  2102. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
  2103. info->ie1_value &= ~CDCD;
  2104. write_reg(info, IE1, info->ie1_value);
  2105. }
  2106. icount->dcd++;
  2107. if (status & SerialSignal_DCD) {
  2108. info->input_signal_events.dcd_up++;
  2109. } else
  2110. info->input_signal_events.dcd_down++;
  2111. #if SYNCLINK_GENERIC_HDLC
  2112. if (info->netcount) {
  2113. if (status & SerialSignal_DCD)
  2114. netif_carrier_on(info->netdev);
  2115. else
  2116. netif_carrier_off(info->netdev);
  2117. }
  2118. #endif
  2119. }
  2120. if (status & MISCSTATUS_CTS_LATCHED)
  2121. {
  2122. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
  2123. info->ie1_value &= ~CCTS;
  2124. write_reg(info, IE1, info->ie1_value);
  2125. }
  2126. icount->cts++;
  2127. if ( status & SerialSignal_CTS )
  2128. info->input_signal_events.cts_up++;
  2129. else
  2130. info->input_signal_events.cts_down++;
  2131. }
  2132. wake_up_interruptible(&info->status_event_wait_q);
  2133. wake_up_interruptible(&info->event_wait_q);
  2134. if ( (info->flags & ASYNC_CHECK_CD) &&
  2135. (status & MISCSTATUS_DCD_LATCHED) ) {
  2136. if ( debug_level >= DEBUG_LEVEL_ISR )
  2137. printk("%s CD now %s...", info->device_name,
  2138. (status & SerialSignal_DCD) ? "on" : "off");
  2139. if (status & SerialSignal_DCD)
  2140. wake_up_interruptible(&info->open_wait);
  2141. else {
  2142. if ( debug_level >= DEBUG_LEVEL_ISR )
  2143. printk("doing serial hangup...");
  2144. if (info->tty)
  2145. tty_hangup(info->tty);
  2146. }
  2147. }
  2148. if ( (info->flags & ASYNC_CTS_FLOW) &&
  2149. (status & MISCSTATUS_CTS_LATCHED) ) {
  2150. if ( info->tty ) {
  2151. if (info->tty->hw_stopped) {
  2152. if (status & SerialSignal_CTS) {
  2153. if ( debug_level >= DEBUG_LEVEL_ISR )
  2154. printk("CTS tx start...");
  2155. info->tty->hw_stopped = 0;
  2156. tx_start(info);
  2157. info->pending_bh |= BH_TRANSMIT;
  2158. return;
  2159. }
  2160. } else {
  2161. if (!(status & SerialSignal_CTS)) {
  2162. if ( debug_level >= DEBUG_LEVEL_ISR )
  2163. printk("CTS tx stop...");
  2164. info->tty->hw_stopped = 1;
  2165. tx_stop(info);
  2166. }
  2167. }
  2168. }
  2169. }
  2170. }
  2171. info->pending_bh |= BH_STATUS;
  2172. }
  2173. /* Interrupt service routine entry point.
  2174. *
  2175. * Arguments:
  2176. * irq interrupt number that caused interrupt
  2177. * dev_id device ID supplied during interrupt registration
  2178. * regs interrupted processor context
  2179. */
  2180. static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id)
  2181. {
  2182. SLMP_INFO * info;
  2183. unsigned char status, status0, status1=0;
  2184. unsigned char dmastatus, dmastatus0, dmastatus1=0;
  2185. unsigned char timerstatus0, timerstatus1=0;
  2186. unsigned char shift;
  2187. unsigned int i;
  2188. unsigned short tmp;
  2189. if ( debug_level >= DEBUG_LEVEL_ISR )
  2190. printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
  2191. __FILE__,__LINE__,irq);
  2192. info = (SLMP_INFO *)dev_id;
  2193. if (!info)
  2194. return IRQ_NONE;
  2195. spin_lock(&info->lock);
  2196. for(;;) {
  2197. /* get status for SCA0 (ports 0-1) */
  2198. tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
  2199. status0 = (unsigned char)tmp;
  2200. dmastatus0 = (unsigned char)(tmp>>8);
  2201. timerstatus0 = read_reg(info, ISR2);
  2202. if ( debug_level >= DEBUG_LEVEL_ISR )
  2203. printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
  2204. __FILE__,__LINE__,info->device_name,
  2205. status0,dmastatus0,timerstatus0);
  2206. if (info->port_count == 4) {
  2207. /* get status for SCA1 (ports 2-3) */
  2208. tmp = read_reg16(info->port_array[2], ISR0);
  2209. status1 = (unsigned char)tmp;
  2210. dmastatus1 = (unsigned char)(tmp>>8);
  2211. timerstatus1 = read_reg(info->port_array[2], ISR2);
  2212. if ( debug_level >= DEBUG_LEVEL_ISR )
  2213. printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
  2214. __FILE__,__LINE__,info->device_name,
  2215. status1,dmastatus1,timerstatus1);
  2216. }
  2217. if (!status0 && !dmastatus0 && !timerstatus0 &&
  2218. !status1 && !dmastatus1 && !timerstatus1)
  2219. break;
  2220. for(i=0; i < info->port_count ; i++) {
  2221. if (info->port_array[i] == NULL)
  2222. continue;
  2223. if (i < 2) {
  2224. status = status0;
  2225. dmastatus = dmastatus0;
  2226. } else {
  2227. status = status1;
  2228. dmastatus = dmastatus1;
  2229. }
  2230. shift = i & 1 ? 4 :0;
  2231. if (status & BIT0 << shift)
  2232. isr_rxrdy(info->port_array[i]);
  2233. if (status & BIT1 << shift)
  2234. isr_txrdy(info->port_array[i]);
  2235. if (status & BIT2 << shift)
  2236. isr_rxint(info->port_array[i]);
  2237. if (status & BIT3 << shift)
  2238. isr_txint(info->port_array[i]);
  2239. if (dmastatus & BIT0 << shift)
  2240. isr_rxdmaerror(info->port_array[i]);
  2241. if (dmastatus & BIT1 << shift)
  2242. isr_rxdmaok(info->port_array[i]);
  2243. if (dmastatus & BIT2 << shift)
  2244. isr_txdmaerror(info->port_array[i]);
  2245. if (dmastatus & BIT3 << shift)
  2246. isr_txdmaok(info->port_array[i]);
  2247. }
  2248. if (timerstatus0 & (BIT5 | BIT4))
  2249. isr_timer(info->port_array[0]);
  2250. if (timerstatus0 & (BIT7 | BIT6))
  2251. isr_timer(info->port_array[1]);
  2252. if (timerstatus1 & (BIT5 | BIT4))
  2253. isr_timer(info->port_array[2]);
  2254. if (timerstatus1 & (BIT7 | BIT6))
  2255. isr_timer(info->port_array[3]);
  2256. }
  2257. for(i=0; i < info->port_count ; i++) {
  2258. SLMP_INFO * port = info->port_array[i];
  2259. /* Request bottom half processing if there's something
  2260. * for it to do and the bh is not already running.
  2261. *
  2262. * Note: startup adapter diags require interrupts.
  2263. * do not request bottom half processing if the
  2264. * device is not open in a normal mode.
  2265. */
  2266. if ( port && (port->count || port->netcount) &&
  2267. port->pending_bh && !port->bh_running &&
  2268. !port->bh_requested ) {
  2269. if ( debug_level >= DEBUG_LEVEL_ISR )
  2270. printk("%s(%d):%s queueing bh task.\n",
  2271. __FILE__,__LINE__,port->device_name);
  2272. schedule_work(&port->task);
  2273. port->bh_requested = 1;
  2274. }
  2275. }
  2276. spin_unlock(&info->lock);
  2277. if ( debug_level >= DEBUG_LEVEL_ISR )
  2278. printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
  2279. __FILE__,__LINE__,irq);
  2280. return IRQ_HANDLED;
  2281. }
  2282. /* Initialize and start device.
  2283. */
  2284. static int startup(SLMP_INFO * info)
  2285. {
  2286. if ( debug_level >= DEBUG_LEVEL_INFO )
  2287. printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
  2288. if (info->flags & ASYNC_INITIALIZED)
  2289. return 0;
  2290. if (!info->tx_buf) {
  2291. info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2292. if (!info->tx_buf) {
  2293. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  2294. __FILE__,__LINE__,info->device_name);
  2295. return -ENOMEM;
  2296. }
  2297. }
  2298. info->pending_bh = 0;
  2299. memset(&info->icount, 0, sizeof(info->icount));
  2300. /* program hardware for current parameters */
  2301. reset_port(info);
  2302. change_params(info);
  2303. mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
  2304. if (info->tty)
  2305. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  2306. info->flags |= ASYNC_INITIALIZED;
  2307. return 0;
  2308. }
  2309. /* Called by close() and hangup() to shutdown hardware
  2310. */
  2311. static void shutdown(SLMP_INFO * info)
  2312. {
  2313. unsigned long flags;
  2314. if (!(info->flags & ASYNC_INITIALIZED))
  2315. return;
  2316. if (debug_level >= DEBUG_LEVEL_INFO)
  2317. printk("%s(%d):%s synclinkmp_shutdown()\n",
  2318. __FILE__,__LINE__, info->device_name );
  2319. /* clear status wait queue because status changes */
  2320. /* can't happen after shutting down the hardware */
  2321. wake_up_interruptible(&info->status_event_wait_q);
  2322. wake_up_interruptible(&info->event_wait_q);
  2323. del_timer(&info->tx_timer);
  2324. del_timer(&info->status_timer);
  2325. kfree(info->tx_buf);
  2326. info->tx_buf = NULL;
  2327. spin_lock_irqsave(&info->lock,flags);
  2328. reset_port(info);
  2329. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  2330. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  2331. set_signals(info);
  2332. }
  2333. spin_unlock_irqrestore(&info->lock,flags);
  2334. if (info->tty)
  2335. set_bit(TTY_IO_ERROR, &info->tty->flags);
  2336. info->flags &= ~ASYNC_INITIALIZED;
  2337. }
  2338. static void program_hw(SLMP_INFO *info)
  2339. {
  2340. unsigned long flags;
  2341. spin_lock_irqsave(&info->lock,flags);
  2342. rx_stop(info);
  2343. tx_stop(info);
  2344. info->tx_count = info->tx_put = info->tx_get = 0;
  2345. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  2346. hdlc_mode(info);
  2347. else
  2348. async_mode(info);
  2349. set_signals(info);
  2350. info->dcd_chkcount = 0;
  2351. info->cts_chkcount = 0;
  2352. info->ri_chkcount = 0;
  2353. info->dsr_chkcount = 0;
  2354. info->ie1_value |= (CDCD|CCTS);
  2355. write_reg(info, IE1, info->ie1_value);
  2356. get_signals(info);
  2357. if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
  2358. rx_start(info);
  2359. spin_unlock_irqrestore(&info->lock,flags);
  2360. }
  2361. /* Reconfigure adapter based on new parameters
  2362. */
  2363. static void change_params(SLMP_INFO *info)
  2364. {
  2365. unsigned cflag;
  2366. int bits_per_char;
  2367. if (!info->tty || !info->tty->termios)
  2368. return;
  2369. if (debug_level >= DEBUG_LEVEL_INFO)
  2370. printk("%s(%d):%s change_params()\n",
  2371. __FILE__,__LINE__, info->device_name );
  2372. cflag = info->tty->termios->c_cflag;
  2373. /* if B0 rate (hangup) specified then negate DTR and RTS */
  2374. /* otherwise assert DTR and RTS */
  2375. if (cflag & CBAUD)
  2376. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2377. else
  2378. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2379. /* byte size and parity */
  2380. switch (cflag & CSIZE) {
  2381. case CS5: info->params.data_bits = 5; break;
  2382. case CS6: info->params.data_bits = 6; break;
  2383. case CS7: info->params.data_bits = 7; break;
  2384. case CS8: info->params.data_bits = 8; break;
  2385. /* Never happens, but GCC is too dumb to figure it out */
  2386. default: info->params.data_bits = 7; break;
  2387. }
  2388. if (cflag & CSTOPB)
  2389. info->params.stop_bits = 2;
  2390. else
  2391. info->params.stop_bits = 1;
  2392. info->params.parity = ASYNC_PARITY_NONE;
  2393. if (cflag & PARENB) {
  2394. if (cflag & PARODD)
  2395. info->params.parity = ASYNC_PARITY_ODD;
  2396. else
  2397. info->params.parity = ASYNC_PARITY_EVEN;
  2398. #ifdef CMSPAR
  2399. if (cflag & CMSPAR)
  2400. info->params.parity = ASYNC_PARITY_SPACE;
  2401. #endif
  2402. }
  2403. /* calculate number of jiffies to transmit a full
  2404. * FIFO (32 bytes) at specified data rate
  2405. */
  2406. bits_per_char = info->params.data_bits +
  2407. info->params.stop_bits + 1;
  2408. /* if port data rate is set to 460800 or less then
  2409. * allow tty settings to override, otherwise keep the
  2410. * current data rate.
  2411. */
  2412. if (info->params.data_rate <= 460800) {
  2413. info->params.data_rate = tty_get_baud_rate(info->tty);
  2414. }
  2415. if ( info->params.data_rate ) {
  2416. info->timeout = (32*HZ*bits_per_char) /
  2417. info->params.data_rate;
  2418. }
  2419. info->timeout += HZ/50; /* Add .02 seconds of slop */
  2420. if (cflag & CRTSCTS)
  2421. info->flags |= ASYNC_CTS_FLOW;
  2422. else
  2423. info->flags &= ~ASYNC_CTS_FLOW;
  2424. if (cflag & CLOCAL)
  2425. info->flags &= ~ASYNC_CHECK_CD;
  2426. else
  2427. info->flags |= ASYNC_CHECK_CD;
  2428. /* process tty input control flags */
  2429. info->read_status_mask2 = OVRN;
  2430. if (I_INPCK(info->tty))
  2431. info->read_status_mask2 |= PE | FRME;
  2432. if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
  2433. info->read_status_mask1 |= BRKD;
  2434. if (I_IGNPAR(info->tty))
  2435. info->ignore_status_mask2 |= PE | FRME;
  2436. if (I_IGNBRK(info->tty)) {
  2437. info->ignore_status_mask1 |= BRKD;
  2438. /* If ignoring parity and break indicators, ignore
  2439. * overruns too. (For real raw support).
  2440. */
  2441. if (I_IGNPAR(info->tty))
  2442. info->ignore_status_mask2 |= OVRN;
  2443. }
  2444. program_hw(info);
  2445. }
  2446. static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
  2447. {
  2448. int err;
  2449. if (debug_level >= DEBUG_LEVEL_INFO)
  2450. printk("%s(%d):%s get_params()\n",
  2451. __FILE__,__LINE__, info->device_name);
  2452. if (!user_icount) {
  2453. memset(&info->icount, 0, sizeof(info->icount));
  2454. } else {
  2455. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  2456. if (err)
  2457. return -EFAULT;
  2458. }
  2459. return 0;
  2460. }
  2461. static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
  2462. {
  2463. int err;
  2464. if (debug_level >= DEBUG_LEVEL_INFO)
  2465. printk("%s(%d):%s get_params()\n",
  2466. __FILE__,__LINE__, info->device_name);
  2467. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  2468. if (err) {
  2469. if ( debug_level >= DEBUG_LEVEL_INFO )
  2470. printk( "%s(%d):%s get_params() user buffer copy failed\n",
  2471. __FILE__,__LINE__,info->device_name);
  2472. return -EFAULT;
  2473. }
  2474. return 0;
  2475. }
  2476. static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
  2477. {
  2478. unsigned long flags;
  2479. MGSL_PARAMS tmp_params;
  2480. int err;
  2481. if (debug_level >= DEBUG_LEVEL_INFO)
  2482. printk("%s(%d):%s set_params\n",
  2483. __FILE__,__LINE__,info->device_name );
  2484. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  2485. if (err) {
  2486. if ( debug_level >= DEBUG_LEVEL_INFO )
  2487. printk( "%s(%d):%s set_params() user buffer copy failed\n",
  2488. __FILE__,__LINE__,info->device_name);
  2489. return -EFAULT;
  2490. }
  2491. spin_lock_irqsave(&info->lock,flags);
  2492. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  2493. spin_unlock_irqrestore(&info->lock,flags);
  2494. change_params(info);
  2495. return 0;
  2496. }
  2497. static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
  2498. {
  2499. int err;
  2500. if (debug_level >= DEBUG_LEVEL_INFO)
  2501. printk("%s(%d):%s get_txidle()=%d\n",
  2502. __FILE__,__LINE__, info->device_name, info->idle_mode);
  2503. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  2504. if (err) {
  2505. if ( debug_level >= DEBUG_LEVEL_INFO )
  2506. printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
  2507. __FILE__,__LINE__,info->device_name);
  2508. return -EFAULT;
  2509. }
  2510. return 0;
  2511. }
  2512. static int set_txidle(SLMP_INFO * info, int idle_mode)
  2513. {
  2514. unsigned long flags;
  2515. if (debug_level >= DEBUG_LEVEL_INFO)
  2516. printk("%s(%d):%s set_txidle(%d)\n",
  2517. __FILE__,__LINE__,info->device_name, idle_mode );
  2518. spin_lock_irqsave(&info->lock,flags);
  2519. info->idle_mode = idle_mode;
  2520. tx_set_idle( info );
  2521. spin_unlock_irqrestore(&info->lock,flags);
  2522. return 0;
  2523. }
  2524. static int tx_enable(SLMP_INFO * info, int enable)
  2525. {
  2526. unsigned long flags;
  2527. if (debug_level >= DEBUG_LEVEL_INFO)
  2528. printk("%s(%d):%s tx_enable(%d)\n",
  2529. __FILE__,__LINE__,info->device_name, enable);
  2530. spin_lock_irqsave(&info->lock,flags);
  2531. if ( enable ) {
  2532. if ( !info->tx_enabled ) {
  2533. tx_start(info);
  2534. }
  2535. } else {
  2536. if ( info->tx_enabled )
  2537. tx_stop(info);
  2538. }
  2539. spin_unlock_irqrestore(&info->lock,flags);
  2540. return 0;
  2541. }
  2542. /* abort send HDLC frame
  2543. */
  2544. static int tx_abort(SLMP_INFO * info)
  2545. {
  2546. unsigned long flags;
  2547. if (debug_level >= DEBUG_LEVEL_INFO)
  2548. printk("%s(%d):%s tx_abort()\n",
  2549. __FILE__,__LINE__,info->device_name);
  2550. spin_lock_irqsave(&info->lock,flags);
  2551. if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
  2552. info->ie1_value &= ~UDRN;
  2553. info->ie1_value |= IDLE;
  2554. write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
  2555. write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
  2556. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  2557. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  2558. write_reg(info, CMD, TXABORT);
  2559. }
  2560. spin_unlock_irqrestore(&info->lock,flags);
  2561. return 0;
  2562. }
  2563. static int rx_enable(SLMP_INFO * info, int enable)
  2564. {
  2565. unsigned long flags;
  2566. if (debug_level >= DEBUG_LEVEL_INFO)
  2567. printk("%s(%d):%s rx_enable(%d)\n",
  2568. __FILE__,__LINE__,info->device_name,enable);
  2569. spin_lock_irqsave(&info->lock,flags);
  2570. if ( enable ) {
  2571. if ( !info->rx_enabled )
  2572. rx_start(info);
  2573. } else {
  2574. if ( info->rx_enabled )
  2575. rx_stop(info);
  2576. }
  2577. spin_unlock_irqrestore(&info->lock,flags);
  2578. return 0;
  2579. }
  2580. /* wait for specified event to occur
  2581. */
  2582. static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
  2583. {
  2584. unsigned long flags;
  2585. int s;
  2586. int rc=0;
  2587. struct mgsl_icount cprev, cnow;
  2588. int events;
  2589. int mask;
  2590. struct _input_signal_events oldsigs, newsigs;
  2591. DECLARE_WAITQUEUE(wait, current);
  2592. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  2593. if (rc) {
  2594. return -EFAULT;
  2595. }
  2596. if (debug_level >= DEBUG_LEVEL_INFO)
  2597. printk("%s(%d):%s wait_mgsl_event(%d)\n",
  2598. __FILE__,__LINE__,info->device_name,mask);
  2599. spin_lock_irqsave(&info->lock,flags);
  2600. /* return immediately if state matches requested events */
  2601. get_signals(info);
  2602. s = info->serial_signals;
  2603. events = mask &
  2604. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2605. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2606. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2607. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2608. if (events) {
  2609. spin_unlock_irqrestore(&info->lock,flags);
  2610. goto exit;
  2611. }
  2612. /* save current irq counts */
  2613. cprev = info->icount;
  2614. oldsigs = info->input_signal_events;
  2615. /* enable hunt and idle irqs if needed */
  2616. if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
  2617. unsigned char oldval = info->ie1_value;
  2618. unsigned char newval = oldval +
  2619. (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
  2620. (mask & MgslEvent_IdleReceived ? IDLD:0);
  2621. if ( oldval != newval ) {
  2622. info->ie1_value = newval;
  2623. write_reg(info, IE1, info->ie1_value);
  2624. }
  2625. }
  2626. set_current_state(TASK_INTERRUPTIBLE);
  2627. add_wait_queue(&info->event_wait_q, &wait);
  2628. spin_unlock_irqrestore(&info->lock,flags);
  2629. for(;;) {
  2630. schedule();
  2631. if (signal_pending(current)) {
  2632. rc = -ERESTARTSYS;
  2633. break;
  2634. }
  2635. /* get current irq counts */
  2636. spin_lock_irqsave(&info->lock,flags);
  2637. cnow = info->icount;
  2638. newsigs = info->input_signal_events;
  2639. set_current_state(TASK_INTERRUPTIBLE);
  2640. spin_unlock_irqrestore(&info->lock,flags);
  2641. /* if no change, wait aborted for some reason */
  2642. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2643. newsigs.dsr_down == oldsigs.dsr_down &&
  2644. newsigs.dcd_up == oldsigs.dcd_up &&
  2645. newsigs.dcd_down == oldsigs.dcd_down &&
  2646. newsigs.cts_up == oldsigs.cts_up &&
  2647. newsigs.cts_down == oldsigs.cts_down &&
  2648. newsigs.ri_up == oldsigs.ri_up &&
  2649. newsigs.ri_down == oldsigs.ri_down &&
  2650. cnow.exithunt == cprev.exithunt &&
  2651. cnow.rxidle == cprev.rxidle) {
  2652. rc = -EIO;
  2653. break;
  2654. }
  2655. events = mask &
  2656. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2657. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2658. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2659. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2660. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2661. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2662. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2663. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2664. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2665. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2666. if (events)
  2667. break;
  2668. cprev = cnow;
  2669. oldsigs = newsigs;
  2670. }
  2671. remove_wait_queue(&info->event_wait_q, &wait);
  2672. set_current_state(TASK_RUNNING);
  2673. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2674. spin_lock_irqsave(&info->lock,flags);
  2675. if (!waitqueue_active(&info->event_wait_q)) {
  2676. /* disable enable exit hunt mode/idle rcvd IRQs */
  2677. info->ie1_value &= ~(FLGD|IDLD);
  2678. write_reg(info, IE1, info->ie1_value);
  2679. }
  2680. spin_unlock_irqrestore(&info->lock,flags);
  2681. }
  2682. exit:
  2683. if ( rc == 0 )
  2684. PUT_USER(rc, events, mask_ptr);
  2685. return rc;
  2686. }
  2687. static int modem_input_wait(SLMP_INFO *info,int arg)
  2688. {
  2689. unsigned long flags;
  2690. int rc;
  2691. struct mgsl_icount cprev, cnow;
  2692. DECLARE_WAITQUEUE(wait, current);
  2693. /* save current irq counts */
  2694. spin_lock_irqsave(&info->lock,flags);
  2695. cprev = info->icount;
  2696. add_wait_queue(&info->status_event_wait_q, &wait);
  2697. set_current_state(TASK_INTERRUPTIBLE);
  2698. spin_unlock_irqrestore(&info->lock,flags);
  2699. for(;;) {
  2700. schedule();
  2701. if (signal_pending(current)) {
  2702. rc = -ERESTARTSYS;
  2703. break;
  2704. }
  2705. /* get new irq counts */
  2706. spin_lock_irqsave(&info->lock,flags);
  2707. cnow = info->icount;
  2708. set_current_state(TASK_INTERRUPTIBLE);
  2709. spin_unlock_irqrestore(&info->lock,flags);
  2710. /* if no change, wait aborted for some reason */
  2711. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2712. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2713. rc = -EIO;
  2714. break;
  2715. }
  2716. /* check for change in caller specified modem input */
  2717. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2718. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2719. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2720. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2721. rc = 0;
  2722. break;
  2723. }
  2724. cprev = cnow;
  2725. }
  2726. remove_wait_queue(&info->status_event_wait_q, &wait);
  2727. set_current_state(TASK_RUNNING);
  2728. return rc;
  2729. }
  2730. /* return the state of the serial control and status signals
  2731. */
  2732. static int tiocmget(struct tty_struct *tty, struct file *file)
  2733. {
  2734. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  2735. unsigned int result;
  2736. unsigned long flags;
  2737. spin_lock_irqsave(&info->lock,flags);
  2738. get_signals(info);
  2739. spin_unlock_irqrestore(&info->lock,flags);
  2740. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2741. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2742. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2743. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2744. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2745. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2746. if (debug_level >= DEBUG_LEVEL_INFO)
  2747. printk("%s(%d):%s tiocmget() value=%08X\n",
  2748. __FILE__,__LINE__, info->device_name, result );
  2749. return result;
  2750. }
  2751. /* set modem control signals (DTR/RTS)
  2752. */
  2753. static int tiocmset(struct tty_struct *tty, struct file *file,
  2754. unsigned int set, unsigned int clear)
  2755. {
  2756. SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
  2757. unsigned long flags;
  2758. if (debug_level >= DEBUG_LEVEL_INFO)
  2759. printk("%s(%d):%s tiocmset(%x,%x)\n",
  2760. __FILE__,__LINE__,info->device_name, set, clear);
  2761. if (set & TIOCM_RTS)
  2762. info->serial_signals |= SerialSignal_RTS;
  2763. if (set & TIOCM_DTR)
  2764. info->serial_signals |= SerialSignal_DTR;
  2765. if (clear & TIOCM_RTS)
  2766. info->serial_signals &= ~SerialSignal_RTS;
  2767. if (clear & TIOCM_DTR)
  2768. info->serial_signals &= ~SerialSignal_DTR;
  2769. spin_lock_irqsave(&info->lock,flags);
  2770. set_signals(info);
  2771. spin_unlock_irqrestore(&info->lock,flags);
  2772. return 0;
  2773. }
  2774. /* Block the current process until the specified port is ready to open.
  2775. */
  2776. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2777. SLMP_INFO *info)
  2778. {
  2779. DECLARE_WAITQUEUE(wait, current);
  2780. int retval;
  2781. int do_clocal = 0, extra_count = 0;
  2782. unsigned long flags;
  2783. if (debug_level >= DEBUG_LEVEL_INFO)
  2784. printk("%s(%d):%s block_til_ready()\n",
  2785. __FILE__,__LINE__, tty->driver->name );
  2786. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2787. /* nonblock mode is set or port is not enabled */
  2788. /* just verify that callout device is not active */
  2789. info->flags |= ASYNC_NORMAL_ACTIVE;
  2790. return 0;
  2791. }
  2792. if (tty->termios->c_cflag & CLOCAL)
  2793. do_clocal = 1;
  2794. /* Wait for carrier detect and the line to become
  2795. * free (i.e., not in use by the callout). While we are in
  2796. * this loop, info->count is dropped by one, so that
  2797. * close() knows when to free things. We restore it upon
  2798. * exit, either normal or abnormal.
  2799. */
  2800. retval = 0;
  2801. add_wait_queue(&info->open_wait, &wait);
  2802. if (debug_level >= DEBUG_LEVEL_INFO)
  2803. printk("%s(%d):%s block_til_ready() before block, count=%d\n",
  2804. __FILE__,__LINE__, tty->driver->name, info->count );
  2805. spin_lock_irqsave(&info->lock, flags);
  2806. if (!tty_hung_up_p(filp)) {
  2807. extra_count = 1;
  2808. info->count--;
  2809. }
  2810. spin_unlock_irqrestore(&info->lock, flags);
  2811. info->blocked_open++;
  2812. while (1) {
  2813. if ((tty->termios->c_cflag & CBAUD)) {
  2814. spin_lock_irqsave(&info->lock,flags);
  2815. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2816. set_signals(info);
  2817. spin_unlock_irqrestore(&info->lock,flags);
  2818. }
  2819. set_current_state(TASK_INTERRUPTIBLE);
  2820. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2821. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2822. -EAGAIN : -ERESTARTSYS;
  2823. break;
  2824. }
  2825. spin_lock_irqsave(&info->lock,flags);
  2826. get_signals(info);
  2827. spin_unlock_irqrestore(&info->lock,flags);
  2828. if (!(info->flags & ASYNC_CLOSING) &&
  2829. (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
  2830. break;
  2831. }
  2832. if (signal_pending(current)) {
  2833. retval = -ERESTARTSYS;
  2834. break;
  2835. }
  2836. if (debug_level >= DEBUG_LEVEL_INFO)
  2837. printk("%s(%d):%s block_til_ready() count=%d\n",
  2838. __FILE__,__LINE__, tty->driver->name, info->count );
  2839. schedule();
  2840. }
  2841. set_current_state(TASK_RUNNING);
  2842. remove_wait_queue(&info->open_wait, &wait);
  2843. if (extra_count)
  2844. info->count++;
  2845. info->blocked_open--;
  2846. if (debug_level >= DEBUG_LEVEL_INFO)
  2847. printk("%s(%d):%s block_til_ready() after, count=%d\n",
  2848. __FILE__,__LINE__, tty->driver->name, info->count );
  2849. if (!retval)
  2850. info->flags |= ASYNC_NORMAL_ACTIVE;
  2851. return retval;
  2852. }
  2853. int alloc_dma_bufs(SLMP_INFO *info)
  2854. {
  2855. unsigned short BuffersPerFrame;
  2856. unsigned short BufferCount;
  2857. // Force allocation to start at 64K boundary for each port.
  2858. // This is necessary because *all* buffer descriptors for a port
  2859. // *must* be in the same 64K block. All descriptors on a port
  2860. // share a common 'base' address (upper 8 bits of 24 bits) programmed
  2861. // into the CBP register.
  2862. info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
  2863. /* Calculate the number of DMA buffers necessary to hold the */
  2864. /* largest allowable frame size. Note: If the max frame size is */
  2865. /* not an even multiple of the DMA buffer size then we need to */
  2866. /* round the buffer count per frame up one. */
  2867. BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
  2868. if ( info->max_frame_size % SCABUFSIZE )
  2869. BuffersPerFrame++;
  2870. /* calculate total number of data buffers (SCABUFSIZE) possible
  2871. * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
  2872. * for the descriptor list (BUFFERLISTSIZE).
  2873. */
  2874. BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
  2875. /* limit number of buffers to maximum amount of descriptors */
  2876. if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
  2877. BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
  2878. /* use enough buffers to transmit one max size frame */
  2879. info->tx_buf_count = BuffersPerFrame + 1;
  2880. /* never use more than half the available buffers for transmit */
  2881. if (info->tx_buf_count > (BufferCount/2))
  2882. info->tx_buf_count = BufferCount/2;
  2883. if (info->tx_buf_count > SCAMAXDESC)
  2884. info->tx_buf_count = SCAMAXDESC;
  2885. /* use remaining buffers for receive */
  2886. info->rx_buf_count = BufferCount - info->tx_buf_count;
  2887. if (info->rx_buf_count > SCAMAXDESC)
  2888. info->rx_buf_count = SCAMAXDESC;
  2889. if ( debug_level >= DEBUG_LEVEL_INFO )
  2890. printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
  2891. __FILE__,__LINE__, info->device_name,
  2892. info->tx_buf_count,info->rx_buf_count);
  2893. if ( alloc_buf_list( info ) < 0 ||
  2894. alloc_frame_bufs(info,
  2895. info->rx_buf_list,
  2896. info->rx_buf_list_ex,
  2897. info->rx_buf_count) < 0 ||
  2898. alloc_frame_bufs(info,
  2899. info->tx_buf_list,
  2900. info->tx_buf_list_ex,
  2901. info->tx_buf_count) < 0 ||
  2902. alloc_tmp_rx_buf(info) < 0 ) {
  2903. printk("%s(%d):%s Can't allocate DMA buffer memory\n",
  2904. __FILE__,__LINE__, info->device_name);
  2905. return -ENOMEM;
  2906. }
  2907. rx_reset_buffers( info );
  2908. return 0;
  2909. }
  2910. /* Allocate DMA buffers for the transmit and receive descriptor lists.
  2911. */
  2912. int alloc_buf_list(SLMP_INFO *info)
  2913. {
  2914. unsigned int i;
  2915. /* build list in adapter shared memory */
  2916. info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
  2917. info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
  2918. info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
  2919. memset(info->buffer_list, 0, BUFFERLISTSIZE);
  2920. /* Save virtual address pointers to the receive and */
  2921. /* transmit buffer lists. (Receive 1st). These pointers will */
  2922. /* be used by the processor to access the lists. */
  2923. info->rx_buf_list = (SCADESC *)info->buffer_list;
  2924. info->tx_buf_list = (SCADESC *)info->buffer_list;
  2925. info->tx_buf_list += info->rx_buf_count;
  2926. /* Build links for circular buffer entry lists (tx and rx)
  2927. *
  2928. * Note: links are physical addresses read by the SCA device
  2929. * to determine the next buffer entry to use.
  2930. */
  2931. for ( i = 0; i < info->rx_buf_count; i++ ) {
  2932. /* calculate and store physical address of this buffer entry */
  2933. info->rx_buf_list_ex[i].phys_entry =
  2934. info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
  2935. /* calculate and store physical address of */
  2936. /* next entry in cirular list of entries */
  2937. info->rx_buf_list[i].next = info->buffer_list_phys;
  2938. if ( i < info->rx_buf_count - 1 )
  2939. info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
  2940. info->rx_buf_list[i].length = SCABUFSIZE;
  2941. }
  2942. for ( i = 0; i < info->tx_buf_count; i++ ) {
  2943. /* calculate and store physical address of this buffer entry */
  2944. info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
  2945. ((info->rx_buf_count + i) * sizeof(SCADESC));
  2946. /* calculate and store physical address of */
  2947. /* next entry in cirular list of entries */
  2948. info->tx_buf_list[i].next = info->buffer_list_phys +
  2949. info->rx_buf_count * sizeof(SCADESC);
  2950. if ( i < info->tx_buf_count - 1 )
  2951. info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
  2952. }
  2953. return 0;
  2954. }
  2955. /* Allocate the frame DMA buffers used by the specified buffer list.
  2956. */
  2957. int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
  2958. {
  2959. int i;
  2960. unsigned long phys_addr;
  2961. for ( i = 0; i < count; i++ ) {
  2962. buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
  2963. phys_addr = info->port_array[0]->last_mem_alloc;
  2964. info->port_array[0]->last_mem_alloc += SCABUFSIZE;
  2965. buf_list[i].buf_ptr = (unsigned short)phys_addr;
  2966. buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
  2967. }
  2968. return 0;
  2969. }
  2970. void free_dma_bufs(SLMP_INFO *info)
  2971. {
  2972. info->buffer_list = NULL;
  2973. info->rx_buf_list = NULL;
  2974. info->tx_buf_list = NULL;
  2975. }
  2976. /* allocate buffer large enough to hold max_frame_size.
  2977. * This buffer is used to pass an assembled frame to the line discipline.
  2978. */
  2979. int alloc_tmp_rx_buf(SLMP_INFO *info)
  2980. {
  2981. info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  2982. if (info->tmp_rx_buf == NULL)
  2983. return -ENOMEM;
  2984. return 0;
  2985. }
  2986. void free_tmp_rx_buf(SLMP_INFO *info)
  2987. {
  2988. kfree(info->tmp_rx_buf);
  2989. info->tmp_rx_buf = NULL;
  2990. }
  2991. int claim_resources(SLMP_INFO *info)
  2992. {
  2993. if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
  2994. printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
  2995. __FILE__,__LINE__,info->device_name, info->phys_memory_base);
  2996. info->init_error = DiagStatus_AddressConflict;
  2997. goto errout;
  2998. }
  2999. else
  3000. info->shared_mem_requested = 1;
  3001. if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
  3002. printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
  3003. __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
  3004. info->init_error = DiagStatus_AddressConflict;
  3005. goto errout;
  3006. }
  3007. else
  3008. info->lcr_mem_requested = 1;
  3009. if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
  3010. printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
  3011. __FILE__,__LINE__,info->device_name, info->phys_sca_base);
  3012. info->init_error = DiagStatus_AddressConflict;
  3013. goto errout;
  3014. }
  3015. else
  3016. info->sca_base_requested = 1;
  3017. if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
  3018. printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
  3019. __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
  3020. info->init_error = DiagStatus_AddressConflict;
  3021. goto errout;
  3022. }
  3023. else
  3024. info->sca_statctrl_requested = 1;
  3025. info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
  3026. if (!info->memory_base) {
  3027. printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
  3028. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3029. info->init_error = DiagStatus_CantAssignPciResources;
  3030. goto errout;
  3031. }
  3032. info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
  3033. if (!info->lcr_base) {
  3034. printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
  3035. __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
  3036. info->init_error = DiagStatus_CantAssignPciResources;
  3037. goto errout;
  3038. }
  3039. info->lcr_base += info->lcr_offset;
  3040. info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
  3041. if (!info->sca_base) {
  3042. printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
  3043. __FILE__,__LINE__,info->device_name, info->phys_sca_base );
  3044. info->init_error = DiagStatus_CantAssignPciResources;
  3045. goto errout;
  3046. }
  3047. info->sca_base += info->sca_offset;
  3048. info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
  3049. if (!info->statctrl_base) {
  3050. printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
  3051. __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
  3052. info->init_error = DiagStatus_CantAssignPciResources;
  3053. goto errout;
  3054. }
  3055. info->statctrl_base += info->statctrl_offset;
  3056. if ( !memory_test(info) ) {
  3057. printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
  3058. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3059. info->init_error = DiagStatus_MemoryError;
  3060. goto errout;
  3061. }
  3062. return 0;
  3063. errout:
  3064. release_resources( info );
  3065. return -ENODEV;
  3066. }
  3067. void release_resources(SLMP_INFO *info)
  3068. {
  3069. if ( debug_level >= DEBUG_LEVEL_INFO )
  3070. printk( "%s(%d):%s release_resources() entry\n",
  3071. __FILE__,__LINE__,info->device_name );
  3072. if ( info->irq_requested ) {
  3073. free_irq(info->irq_level, info);
  3074. info->irq_requested = 0;
  3075. }
  3076. if ( info->shared_mem_requested ) {
  3077. release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
  3078. info->shared_mem_requested = 0;
  3079. }
  3080. if ( info->lcr_mem_requested ) {
  3081. release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
  3082. info->lcr_mem_requested = 0;
  3083. }
  3084. if ( info->sca_base_requested ) {
  3085. release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
  3086. info->sca_base_requested = 0;
  3087. }
  3088. if ( info->sca_statctrl_requested ) {
  3089. release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
  3090. info->sca_statctrl_requested = 0;
  3091. }
  3092. if (info->memory_base){
  3093. iounmap(info->memory_base);
  3094. info->memory_base = NULL;
  3095. }
  3096. if (info->sca_base) {
  3097. iounmap(info->sca_base - info->sca_offset);
  3098. info->sca_base=NULL;
  3099. }
  3100. if (info->statctrl_base) {
  3101. iounmap(info->statctrl_base - info->statctrl_offset);
  3102. info->statctrl_base=NULL;
  3103. }
  3104. if (info->lcr_base){
  3105. iounmap(info->lcr_base - info->lcr_offset);
  3106. info->lcr_base = NULL;
  3107. }
  3108. if ( debug_level >= DEBUG_LEVEL_INFO )
  3109. printk( "%s(%d):%s release_resources() exit\n",
  3110. __FILE__,__LINE__,info->device_name );
  3111. }
  3112. /* Add the specified device instance data structure to the
  3113. * global linked list of devices and increment the device count.
  3114. */
  3115. void add_device(SLMP_INFO *info)
  3116. {
  3117. info->next_device = NULL;
  3118. info->line = synclinkmp_device_count;
  3119. sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
  3120. if (info->line < MAX_DEVICES) {
  3121. if (maxframe[info->line])
  3122. info->max_frame_size = maxframe[info->line];
  3123. info->dosyncppp = dosyncppp[info->line];
  3124. }
  3125. synclinkmp_device_count++;
  3126. if ( !synclinkmp_device_list )
  3127. synclinkmp_device_list = info;
  3128. else {
  3129. SLMP_INFO *current_dev = synclinkmp_device_list;
  3130. while( current_dev->next_device )
  3131. current_dev = current_dev->next_device;
  3132. current_dev->next_device = info;
  3133. }
  3134. if ( info->max_frame_size < 4096 )
  3135. info->max_frame_size = 4096;
  3136. else if ( info->max_frame_size > 65535 )
  3137. info->max_frame_size = 65535;
  3138. printk( "SyncLink MultiPort %s: "
  3139. "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
  3140. info->device_name,
  3141. info->phys_sca_base,
  3142. info->phys_memory_base,
  3143. info->phys_statctrl_base,
  3144. info->phys_lcr_base,
  3145. info->irq_level,
  3146. info->max_frame_size );
  3147. #if SYNCLINK_GENERIC_HDLC
  3148. hdlcdev_init(info);
  3149. #endif
  3150. }
  3151. /* Allocate and initialize a device instance structure
  3152. *
  3153. * Return Value: pointer to SLMP_INFO if success, otherwise NULL
  3154. */
  3155. static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
  3156. {
  3157. SLMP_INFO *info;
  3158. info = kmalloc(sizeof(SLMP_INFO),
  3159. GFP_KERNEL);
  3160. if (!info) {
  3161. printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
  3162. __FILE__,__LINE__, adapter_num, port_num);
  3163. } else {
  3164. memset(info, 0, sizeof(SLMP_INFO));
  3165. info->magic = MGSL_MAGIC;
  3166. INIT_WORK(&info->task, bh_handler);
  3167. info->max_frame_size = 4096;
  3168. info->close_delay = 5*HZ/10;
  3169. info->closing_wait = 30*HZ;
  3170. init_waitqueue_head(&info->open_wait);
  3171. init_waitqueue_head(&info->close_wait);
  3172. init_waitqueue_head(&info->status_event_wait_q);
  3173. init_waitqueue_head(&info->event_wait_q);
  3174. spin_lock_init(&info->netlock);
  3175. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  3176. info->idle_mode = HDLC_TXIDLE_FLAGS;
  3177. info->adapter_num = adapter_num;
  3178. info->port_num = port_num;
  3179. /* Copy configuration info to device instance data */
  3180. info->irq_level = pdev->irq;
  3181. info->phys_lcr_base = pci_resource_start(pdev,0);
  3182. info->phys_sca_base = pci_resource_start(pdev,2);
  3183. info->phys_memory_base = pci_resource_start(pdev,3);
  3184. info->phys_statctrl_base = pci_resource_start(pdev,4);
  3185. /* Because veremap only works on page boundaries we must map
  3186. * a larger area than is actually implemented for the LCR
  3187. * memory range. We map a full page starting at the page boundary.
  3188. */
  3189. info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
  3190. info->phys_lcr_base &= ~(PAGE_SIZE-1);
  3191. info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
  3192. info->phys_sca_base &= ~(PAGE_SIZE-1);
  3193. info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
  3194. info->phys_statctrl_base &= ~(PAGE_SIZE-1);
  3195. info->bus_type = MGSL_BUS_TYPE_PCI;
  3196. info->irq_flags = IRQF_SHARED;
  3197. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  3198. setup_timer(&info->status_timer, status_timeout,
  3199. (unsigned long)info);
  3200. /* Store the PCI9050 misc control register value because a flaw
  3201. * in the PCI9050 prevents LCR registers from being read if
  3202. * BIOS assigns an LCR base address with bit 7 set.
  3203. *
  3204. * Only the misc control register is accessed for which only
  3205. * write access is needed, so set an initial value and change
  3206. * bits to the device instance data as we write the value
  3207. * to the actual misc control register.
  3208. */
  3209. info->misc_ctrl_value = 0x087e4546;
  3210. /* initial port state is unknown - if startup errors
  3211. * occur, init_error will be set to indicate the
  3212. * problem. Once the port is fully initialized,
  3213. * this value will be set to 0 to indicate the
  3214. * port is available.
  3215. */
  3216. info->init_error = -1;
  3217. }
  3218. return info;
  3219. }
  3220. void device_init(int adapter_num, struct pci_dev *pdev)
  3221. {
  3222. SLMP_INFO *port_array[SCA_MAX_PORTS];
  3223. int port;
  3224. /* allocate device instances for up to SCA_MAX_PORTS devices */
  3225. for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
  3226. port_array[port] = alloc_dev(adapter_num,port,pdev);
  3227. if( port_array[port] == NULL ) {
  3228. for ( --port; port >= 0; --port )
  3229. kfree(port_array[port]);
  3230. return;
  3231. }
  3232. }
  3233. /* give copy of port_array to all ports and add to device list */
  3234. for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
  3235. memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
  3236. add_device( port_array[port] );
  3237. spin_lock_init(&port_array[port]->lock);
  3238. }
  3239. /* Allocate and claim adapter resources */
  3240. if ( !claim_resources(port_array[0]) ) {
  3241. alloc_dma_bufs(port_array[0]);
  3242. /* copy resource information from first port to others */
  3243. for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
  3244. port_array[port]->lock = port_array[0]->lock;
  3245. port_array[port]->irq_level = port_array[0]->irq_level;
  3246. port_array[port]->memory_base = port_array[0]->memory_base;
  3247. port_array[port]->sca_base = port_array[0]->sca_base;
  3248. port_array[port]->statctrl_base = port_array[0]->statctrl_base;
  3249. port_array[port]->lcr_base = port_array[0]->lcr_base;
  3250. alloc_dma_bufs(port_array[port]);
  3251. }
  3252. if ( request_irq(port_array[0]->irq_level,
  3253. synclinkmp_interrupt,
  3254. port_array[0]->irq_flags,
  3255. port_array[0]->device_name,
  3256. port_array[0]) < 0 ) {
  3257. printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
  3258. __FILE__,__LINE__,
  3259. port_array[0]->device_name,
  3260. port_array[0]->irq_level );
  3261. }
  3262. else {
  3263. port_array[0]->irq_requested = 1;
  3264. adapter_test(port_array[0]);
  3265. }
  3266. }
  3267. }
  3268. static const struct tty_operations ops = {
  3269. .open = open,
  3270. .close = close,
  3271. .write = write,
  3272. .put_char = put_char,
  3273. .flush_chars = flush_chars,
  3274. .write_room = write_room,
  3275. .chars_in_buffer = chars_in_buffer,
  3276. .flush_buffer = flush_buffer,
  3277. .ioctl = ioctl,
  3278. .throttle = throttle,
  3279. .unthrottle = unthrottle,
  3280. .send_xchar = send_xchar,
  3281. .break_ctl = set_break,
  3282. .wait_until_sent = wait_until_sent,
  3283. .read_proc = read_proc,
  3284. .set_termios = set_termios,
  3285. .stop = tx_hold,
  3286. .start = tx_release,
  3287. .hangup = hangup,
  3288. .tiocmget = tiocmget,
  3289. .tiocmset = tiocmset,
  3290. };
  3291. static void synclinkmp_cleanup(void)
  3292. {
  3293. int rc;
  3294. SLMP_INFO *info;
  3295. SLMP_INFO *tmp;
  3296. printk("Unloading %s %s\n", driver_name, driver_version);
  3297. if (serial_driver) {
  3298. if ((rc = tty_unregister_driver(serial_driver)))
  3299. printk("%s(%d) failed to unregister tty driver err=%d\n",
  3300. __FILE__,__LINE__,rc);
  3301. put_tty_driver(serial_driver);
  3302. }
  3303. /* reset devices */
  3304. info = synclinkmp_device_list;
  3305. while(info) {
  3306. reset_port(info);
  3307. info = info->next_device;
  3308. }
  3309. /* release devices */
  3310. info = synclinkmp_device_list;
  3311. while(info) {
  3312. #if SYNCLINK_GENERIC_HDLC
  3313. hdlcdev_exit(info);
  3314. #endif
  3315. free_dma_bufs(info);
  3316. free_tmp_rx_buf(info);
  3317. if ( info->port_num == 0 ) {
  3318. if (info->sca_base)
  3319. write_reg(info, LPR, 1); /* set low power mode */
  3320. release_resources(info);
  3321. }
  3322. tmp = info;
  3323. info = info->next_device;
  3324. kfree(tmp);
  3325. }
  3326. pci_unregister_driver(&synclinkmp_pci_driver);
  3327. }
  3328. /* Driver initialization entry point.
  3329. */
  3330. static int __init synclinkmp_init(void)
  3331. {
  3332. int rc;
  3333. if (break_on_load) {
  3334. synclinkmp_get_text_ptr();
  3335. BREAKPOINT();
  3336. }
  3337. printk("%s %s\n", driver_name, driver_version);
  3338. if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
  3339. printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
  3340. return rc;
  3341. }
  3342. serial_driver = alloc_tty_driver(128);
  3343. if (!serial_driver) {
  3344. rc = -ENOMEM;
  3345. goto error;
  3346. }
  3347. /* Initialize the tty_driver structure */
  3348. serial_driver->owner = THIS_MODULE;
  3349. serial_driver->driver_name = "synclinkmp";
  3350. serial_driver->name = "ttySLM";
  3351. serial_driver->major = ttymajor;
  3352. serial_driver->minor_start = 64;
  3353. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3354. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3355. serial_driver->init_termios = tty_std_termios;
  3356. serial_driver->init_termios.c_cflag =
  3357. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3358. serial_driver->init_termios.c_ispeed = 9600;
  3359. serial_driver->init_termios.c_ospeed = 9600;
  3360. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  3361. tty_set_operations(serial_driver, &ops);
  3362. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3363. printk("%s(%d):Couldn't register serial driver\n",
  3364. __FILE__,__LINE__);
  3365. put_tty_driver(serial_driver);
  3366. serial_driver = NULL;
  3367. goto error;
  3368. }
  3369. printk("%s %s, tty major#%d\n",
  3370. driver_name, driver_version,
  3371. serial_driver->major);
  3372. return 0;
  3373. error:
  3374. synclinkmp_cleanup();
  3375. return rc;
  3376. }
  3377. static void __exit synclinkmp_exit(void)
  3378. {
  3379. synclinkmp_cleanup();
  3380. }
  3381. module_init(synclinkmp_init);
  3382. module_exit(synclinkmp_exit);
  3383. /* Set the port for internal loopback mode.
  3384. * The TxCLK and RxCLK signals are generated from the BRG and
  3385. * the TxD is looped back to the RxD internally.
  3386. */
  3387. void enable_loopback(SLMP_INFO *info, int enable)
  3388. {
  3389. if (enable) {
  3390. /* MD2 (Mode Register 2)
  3391. * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
  3392. */
  3393. write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
  3394. /* degate external TxC clock source */
  3395. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3396. write_control_reg(info);
  3397. /* RXS/TXS (Rx/Tx clock source)
  3398. * 07 Reserved, must be 0
  3399. * 06..04 Clock Source, 100=BRG
  3400. * 03..00 Clock Divisor, 0000=1
  3401. */
  3402. write_reg(info, RXS, 0x40);
  3403. write_reg(info, TXS, 0x40);
  3404. } else {
  3405. /* MD2 (Mode Register 2)
  3406. * 01..00 CNCT<1..0> Channel connection, 0=normal
  3407. */
  3408. write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
  3409. /* RXS/TXS (Rx/Tx clock source)
  3410. * 07 Reserved, must be 0
  3411. * 06..04 Clock Source, 000=RxC/TxC Pin
  3412. * 03..00 Clock Divisor, 0000=1
  3413. */
  3414. write_reg(info, RXS, 0x00);
  3415. write_reg(info, TXS, 0x00);
  3416. }
  3417. /* set LinkSpeed if available, otherwise default to 2Mbps */
  3418. if (info->params.clock_speed)
  3419. set_rate(info, info->params.clock_speed);
  3420. else
  3421. set_rate(info, 3686400);
  3422. }
  3423. /* Set the baud rate register to the desired speed
  3424. *
  3425. * data_rate data rate of clock in bits per second
  3426. * A data rate of 0 disables the AUX clock.
  3427. */
  3428. void set_rate( SLMP_INFO *info, u32 data_rate )
  3429. {
  3430. u32 TMCValue;
  3431. unsigned char BRValue;
  3432. u32 Divisor=0;
  3433. /* fBRG = fCLK/(TMC * 2^BR)
  3434. */
  3435. if (data_rate != 0) {
  3436. Divisor = 14745600/data_rate;
  3437. if (!Divisor)
  3438. Divisor = 1;
  3439. TMCValue = Divisor;
  3440. BRValue = 0;
  3441. if (TMCValue != 1 && TMCValue != 2) {
  3442. /* BRValue of 0 provides 50/50 duty cycle *only* when
  3443. * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
  3444. * 50/50 duty cycle.
  3445. */
  3446. BRValue = 1;
  3447. TMCValue >>= 1;
  3448. }
  3449. /* while TMCValue is too big for TMC register, divide
  3450. * by 2 and increment BR exponent.
  3451. */
  3452. for(; TMCValue > 256 && BRValue < 10; BRValue++)
  3453. TMCValue >>= 1;
  3454. write_reg(info, TXS,
  3455. (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
  3456. write_reg(info, RXS,
  3457. (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
  3458. write_reg(info, TMC, (unsigned char)TMCValue);
  3459. }
  3460. else {
  3461. write_reg(info, TXS,0);
  3462. write_reg(info, RXS,0);
  3463. write_reg(info, TMC, 0);
  3464. }
  3465. }
  3466. /* Disable receiver
  3467. */
  3468. void rx_stop(SLMP_INFO *info)
  3469. {
  3470. if (debug_level >= DEBUG_LEVEL_ISR)
  3471. printk("%s(%d):%s rx_stop()\n",
  3472. __FILE__,__LINE__, info->device_name );
  3473. write_reg(info, CMD, RXRESET);
  3474. info->ie0_value &= ~RXRDYE;
  3475. write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
  3476. write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
  3477. write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
  3478. write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
  3479. info->rx_enabled = 0;
  3480. info->rx_overflow = 0;
  3481. }
  3482. /* enable the receiver
  3483. */
  3484. void rx_start(SLMP_INFO *info)
  3485. {
  3486. int i;
  3487. if (debug_level >= DEBUG_LEVEL_ISR)
  3488. printk("%s(%d):%s rx_start()\n",
  3489. __FILE__,__LINE__, info->device_name );
  3490. write_reg(info, CMD, RXRESET);
  3491. if ( info->params.mode == MGSL_MODE_HDLC ) {
  3492. /* HDLC, disabe IRQ on rxdata */
  3493. info->ie0_value &= ~RXRDYE;
  3494. write_reg(info, IE0, info->ie0_value);
  3495. /* Reset all Rx DMA buffers and program rx dma */
  3496. write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
  3497. write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
  3498. for (i = 0; i < info->rx_buf_count; i++) {
  3499. info->rx_buf_list[i].status = 0xff;
  3500. // throttle to 4 shared memory writes at a time to prevent
  3501. // hogging local bus (keep latency time for DMA requests low).
  3502. if (!(i % 4))
  3503. read_status_reg(info);
  3504. }
  3505. info->current_rx_buf = 0;
  3506. /* set current/1st descriptor address */
  3507. write_reg16(info, RXDMA + CDA,
  3508. info->rx_buf_list_ex[0].phys_entry);
  3509. /* set new last rx descriptor address */
  3510. write_reg16(info, RXDMA + EDA,
  3511. info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
  3512. /* set buffer length (shared by all rx dma data buffers) */
  3513. write_reg16(info, RXDMA + BFL, SCABUFSIZE);
  3514. write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
  3515. write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
  3516. } else {
  3517. /* async, enable IRQ on rxdata */
  3518. info->ie0_value |= RXRDYE;
  3519. write_reg(info, IE0, info->ie0_value);
  3520. }
  3521. write_reg(info, CMD, RXENABLE);
  3522. info->rx_overflow = FALSE;
  3523. info->rx_enabled = 1;
  3524. }
  3525. /* Enable the transmitter and send a transmit frame if
  3526. * one is loaded in the DMA buffers.
  3527. */
  3528. void tx_start(SLMP_INFO *info)
  3529. {
  3530. if (debug_level >= DEBUG_LEVEL_ISR)
  3531. printk("%s(%d):%s tx_start() tx_count=%d\n",
  3532. __FILE__,__LINE__, info->device_name,info->tx_count );
  3533. if (!info->tx_enabled ) {
  3534. write_reg(info, CMD, TXRESET);
  3535. write_reg(info, CMD, TXENABLE);
  3536. info->tx_enabled = TRUE;
  3537. }
  3538. if ( info->tx_count ) {
  3539. /* If auto RTS enabled and RTS is inactive, then assert */
  3540. /* RTS and set a flag indicating that the driver should */
  3541. /* negate RTS when the transmission completes. */
  3542. info->drop_rts_on_tx_done = 0;
  3543. if (info->params.mode != MGSL_MODE_ASYNC) {
  3544. if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
  3545. get_signals( info );
  3546. if ( !(info->serial_signals & SerialSignal_RTS) ) {
  3547. info->serial_signals |= SerialSignal_RTS;
  3548. set_signals( info );
  3549. info->drop_rts_on_tx_done = 1;
  3550. }
  3551. }
  3552. write_reg16(info, TRC0,
  3553. (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
  3554. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  3555. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  3556. /* set TX CDA (current descriptor address) */
  3557. write_reg16(info, TXDMA + CDA,
  3558. info->tx_buf_list_ex[0].phys_entry);
  3559. /* set TX EDA (last descriptor address) */
  3560. write_reg16(info, TXDMA + EDA,
  3561. info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
  3562. /* enable underrun IRQ */
  3563. info->ie1_value &= ~IDLE;
  3564. info->ie1_value |= UDRN;
  3565. write_reg(info, IE1, info->ie1_value);
  3566. write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
  3567. write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
  3568. write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
  3569. mod_timer(&info->tx_timer, jiffies +
  3570. msecs_to_jiffies(5000));
  3571. }
  3572. else {
  3573. tx_load_fifo(info);
  3574. /* async, enable IRQ on txdata */
  3575. info->ie0_value |= TXRDYE;
  3576. write_reg(info, IE0, info->ie0_value);
  3577. }
  3578. info->tx_active = 1;
  3579. }
  3580. }
  3581. /* stop the transmitter and DMA
  3582. */
  3583. void tx_stop( SLMP_INFO *info )
  3584. {
  3585. if (debug_level >= DEBUG_LEVEL_ISR)
  3586. printk("%s(%d):%s tx_stop()\n",
  3587. __FILE__,__LINE__, info->device_name );
  3588. del_timer(&info->tx_timer);
  3589. write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
  3590. write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
  3591. write_reg(info, CMD, TXRESET);
  3592. info->ie1_value &= ~(UDRN + IDLE);
  3593. write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
  3594. write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
  3595. info->ie0_value &= ~TXRDYE;
  3596. write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
  3597. info->tx_enabled = 0;
  3598. info->tx_active = 0;
  3599. }
  3600. /* Fill the transmit FIFO until the FIFO is full or
  3601. * there is no more data to load.
  3602. */
  3603. void tx_load_fifo(SLMP_INFO *info)
  3604. {
  3605. u8 TwoBytes[2];
  3606. /* do nothing is now tx data available and no XON/XOFF pending */
  3607. if ( !info->tx_count && !info->x_char )
  3608. return;
  3609. /* load the Transmit FIFO until FIFOs full or all data sent */
  3610. while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
  3611. /* there is more space in the transmit FIFO and */
  3612. /* there is more data in transmit buffer */
  3613. if ( (info->tx_count > 1) && !info->x_char ) {
  3614. /* write 16-bits */
  3615. TwoBytes[0] = info->tx_buf[info->tx_get++];
  3616. if (info->tx_get >= info->max_frame_size)
  3617. info->tx_get -= info->max_frame_size;
  3618. TwoBytes[1] = info->tx_buf[info->tx_get++];
  3619. if (info->tx_get >= info->max_frame_size)
  3620. info->tx_get -= info->max_frame_size;
  3621. write_reg16(info, TRB, *((u16 *)TwoBytes));
  3622. info->tx_count -= 2;
  3623. info->icount.tx += 2;
  3624. } else {
  3625. /* only 1 byte left to transmit or 1 FIFO slot left */
  3626. if (info->x_char) {
  3627. /* transmit pending high priority char */
  3628. write_reg(info, TRB, info->x_char);
  3629. info->x_char = 0;
  3630. } else {
  3631. write_reg(info, TRB, info->tx_buf[info->tx_get++]);
  3632. if (info->tx_get >= info->max_frame_size)
  3633. info->tx_get -= info->max_frame_size;
  3634. info->tx_count--;
  3635. }
  3636. info->icount.tx++;
  3637. }
  3638. }
  3639. }
  3640. /* Reset a port to a known state
  3641. */
  3642. void reset_port(SLMP_INFO *info)
  3643. {
  3644. if (info->sca_base) {
  3645. tx_stop(info);
  3646. rx_stop(info);
  3647. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  3648. set_signals(info);
  3649. /* disable all port interrupts */
  3650. info->ie0_value = 0;
  3651. info->ie1_value = 0;
  3652. info->ie2_value = 0;
  3653. write_reg(info, IE0, info->ie0_value);
  3654. write_reg(info, IE1, info->ie1_value);
  3655. write_reg(info, IE2, info->ie2_value);
  3656. write_reg(info, CMD, CHRESET);
  3657. }
  3658. }
  3659. /* Reset all the ports to a known state.
  3660. */
  3661. void reset_adapter(SLMP_INFO *info)
  3662. {
  3663. int i;
  3664. for ( i=0; i < SCA_MAX_PORTS; ++i) {
  3665. if (info->port_array[i])
  3666. reset_port(info->port_array[i]);
  3667. }
  3668. }
  3669. /* Program port for asynchronous communications.
  3670. */
  3671. void async_mode(SLMP_INFO *info)
  3672. {
  3673. unsigned char RegValue;
  3674. tx_stop(info);
  3675. rx_stop(info);
  3676. /* MD0, Mode Register 0
  3677. *
  3678. * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
  3679. * 04 AUTO, Auto-enable (RTS/CTS/DCD)
  3680. * 03 Reserved, must be 0
  3681. * 02 CRCCC, CRC Calculation, 0=disabled
  3682. * 01..00 STOP<1..0> Stop bits (00=1,10=2)
  3683. *
  3684. * 0000 0000
  3685. */
  3686. RegValue = 0x00;
  3687. if (info->params.stop_bits != 1)
  3688. RegValue |= BIT1;
  3689. write_reg(info, MD0, RegValue);
  3690. /* MD1, Mode Register 1
  3691. *
  3692. * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
  3693. * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
  3694. * 03..02 RXCHR<1..0>, rx char size
  3695. * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
  3696. *
  3697. * 0100 0000
  3698. */
  3699. RegValue = 0x40;
  3700. switch (info->params.data_bits) {
  3701. case 7: RegValue |= BIT4 + BIT2; break;
  3702. case 6: RegValue |= BIT5 + BIT3; break;
  3703. case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
  3704. }
  3705. if (info->params.parity != ASYNC_PARITY_NONE) {
  3706. RegValue |= BIT1;
  3707. if (info->params.parity == ASYNC_PARITY_ODD)
  3708. RegValue |= BIT0;
  3709. }
  3710. write_reg(info, MD1, RegValue);
  3711. /* MD2, Mode Register 2
  3712. *
  3713. * 07..02 Reserved, must be 0
  3714. * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
  3715. *
  3716. * 0000 0000
  3717. */
  3718. RegValue = 0x00;
  3719. if (info->params.loopback)
  3720. RegValue |= (BIT1 + BIT0);
  3721. write_reg(info, MD2, RegValue);
  3722. /* RXS, Receive clock source
  3723. *
  3724. * 07 Reserved, must be 0
  3725. * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
  3726. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3727. */
  3728. RegValue=BIT6;
  3729. write_reg(info, RXS, RegValue);
  3730. /* TXS, Transmit clock source
  3731. *
  3732. * 07 Reserved, must be 0
  3733. * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
  3734. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3735. */
  3736. RegValue=BIT6;
  3737. write_reg(info, TXS, RegValue);
  3738. /* Control Register
  3739. *
  3740. * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
  3741. */
  3742. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3743. write_control_reg(info);
  3744. tx_set_idle(info);
  3745. /* RRC Receive Ready Control 0
  3746. *
  3747. * 07..05 Reserved, must be 0
  3748. * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
  3749. */
  3750. write_reg(info, RRC, 0x00);
  3751. /* TRC0 Transmit Ready Control 0
  3752. *
  3753. * 07..05 Reserved, must be 0
  3754. * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
  3755. */
  3756. write_reg(info, TRC0, 0x10);
  3757. /* TRC1 Transmit Ready Control 1
  3758. *
  3759. * 07..05 Reserved, must be 0
  3760. * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
  3761. */
  3762. write_reg(info, TRC1, 0x1e);
  3763. /* CTL, MSCI control register
  3764. *
  3765. * 07..06 Reserved, set to 0
  3766. * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
  3767. * 04 IDLC, idle control, 0=mark 1=idle register
  3768. * 03 BRK, break, 0=off 1 =on (async)
  3769. * 02 SYNCLD, sync char load enable (BSC) 1=enabled
  3770. * 01 GOP, go active on poll (LOOP mode) 1=enabled
  3771. * 00 RTS, RTS output control, 0=active 1=inactive
  3772. *
  3773. * 0001 0001
  3774. */
  3775. RegValue = 0x10;
  3776. if (!(info->serial_signals & SerialSignal_RTS))
  3777. RegValue |= 0x01;
  3778. write_reg(info, CTL, RegValue);
  3779. /* enable status interrupts */
  3780. info->ie0_value |= TXINTE + RXINTE;
  3781. write_reg(info, IE0, info->ie0_value);
  3782. /* enable break detect interrupt */
  3783. info->ie1_value = BRKD;
  3784. write_reg(info, IE1, info->ie1_value);
  3785. /* enable rx overrun interrupt */
  3786. info->ie2_value = OVRN;
  3787. write_reg(info, IE2, info->ie2_value);
  3788. set_rate( info, info->params.data_rate * 16 );
  3789. }
  3790. /* Program the SCA for HDLC communications.
  3791. */
  3792. void hdlc_mode(SLMP_INFO *info)
  3793. {
  3794. unsigned char RegValue;
  3795. u32 DpllDivisor;
  3796. // Can't use DPLL because SCA outputs recovered clock on RxC when
  3797. // DPLL mode selected. This causes output contention with RxC receiver.
  3798. // Use of DPLL would require external hardware to disable RxC receiver
  3799. // when DPLL mode selected.
  3800. info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
  3801. /* disable DMA interrupts */
  3802. write_reg(info, TXDMA + DIR, 0);
  3803. write_reg(info, RXDMA + DIR, 0);
  3804. /* MD0, Mode Register 0
  3805. *
  3806. * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
  3807. * 04 AUTO, Auto-enable (RTS/CTS/DCD)
  3808. * 03 Reserved, must be 0
  3809. * 02 CRCCC, CRC Calculation, 1=enabled
  3810. * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
  3811. * 00 CRC0, CRC initial value, 1 = all 1s
  3812. *
  3813. * 1000 0001
  3814. */
  3815. RegValue = 0x81;
  3816. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3817. RegValue |= BIT4;
  3818. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3819. RegValue |= BIT4;
  3820. if (info->params.crc_type == HDLC_CRC_16_CCITT)
  3821. RegValue |= BIT2 + BIT1;
  3822. write_reg(info, MD0, RegValue);
  3823. /* MD1, Mode Register 1
  3824. *
  3825. * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
  3826. * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
  3827. * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
  3828. * 01..00 PMPM<1..0>, Parity mode, 00=no parity
  3829. *
  3830. * 0000 0000
  3831. */
  3832. RegValue = 0x00;
  3833. write_reg(info, MD1, RegValue);
  3834. /* MD2, Mode Register 2
  3835. *
  3836. * 07 NRZFM, 0=NRZ, 1=FM
  3837. * 06..05 CODE<1..0> Encoding, 00=NRZ
  3838. * 04..03 DRATE<1..0> DPLL Divisor, 00=8
  3839. * 02 Reserved, must be 0
  3840. * 01..00 CNCT<1..0> Channel connection, 0=normal
  3841. *
  3842. * 0000 0000
  3843. */
  3844. RegValue = 0x00;
  3845. switch(info->params.encoding) {
  3846. case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
  3847. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
  3848. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
  3849. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
  3850. #if 0
  3851. case HDLC_ENCODING_NRZB: /* not supported */
  3852. case HDLC_ENCODING_NRZI_MARK: /* not supported */
  3853. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
  3854. #endif
  3855. }
  3856. if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
  3857. DpllDivisor = 16;
  3858. RegValue |= BIT3;
  3859. } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
  3860. DpllDivisor = 8;
  3861. } else {
  3862. DpllDivisor = 32;
  3863. RegValue |= BIT4;
  3864. }
  3865. write_reg(info, MD2, RegValue);
  3866. /* RXS, Receive clock source
  3867. *
  3868. * 07 Reserved, must be 0
  3869. * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
  3870. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3871. */
  3872. RegValue=0;
  3873. if (info->params.flags & HDLC_FLAG_RXC_BRG)
  3874. RegValue |= BIT6;
  3875. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3876. RegValue |= BIT6 + BIT5;
  3877. write_reg(info, RXS, RegValue);
  3878. /* TXS, Transmit clock source
  3879. *
  3880. * 07 Reserved, must be 0
  3881. * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
  3882. * 03..00 RXBR<3..0>, rate divisor, 0000=1
  3883. */
  3884. RegValue=0;
  3885. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3886. RegValue |= BIT6;
  3887. if (info->params.flags & HDLC_FLAG_TXC_DPLL)
  3888. RegValue |= BIT6 + BIT5;
  3889. write_reg(info, TXS, RegValue);
  3890. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3891. set_rate(info, info->params.clock_speed * DpllDivisor);
  3892. else
  3893. set_rate(info, info->params.clock_speed);
  3894. /* GPDATA (General Purpose I/O Data Register)
  3895. *
  3896. * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
  3897. */
  3898. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3899. info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
  3900. else
  3901. info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
  3902. write_control_reg(info);
  3903. /* RRC Receive Ready Control 0
  3904. *
  3905. * 07..05 Reserved, must be 0
  3906. * 04..00 RRC<4..0> Rx FIFO trigger active
  3907. */
  3908. write_reg(info, RRC, rx_active_fifo_level);
  3909. /* TRC0 Transmit Ready Control 0
  3910. *
  3911. * 07..05 Reserved, must be 0
  3912. * 04..00 TRC<4..0> Tx FIFO trigger active
  3913. */
  3914. write_reg(info, TRC0, tx_active_fifo_level);
  3915. /* TRC1 Transmit Ready Control 1
  3916. *
  3917. * 07..05 Reserved, must be 0
  3918. * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
  3919. */
  3920. write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
  3921. /* DMR, DMA Mode Register
  3922. *
  3923. * 07..05 Reserved, must be 0
  3924. * 04 TMOD, Transfer Mode: 1=chained-block
  3925. * 03 Reserved, must be 0
  3926. * 02 NF, Number of Frames: 1=multi-frame
  3927. * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
  3928. * 00 Reserved, must be 0
  3929. *
  3930. * 0001 0100
  3931. */
  3932. write_reg(info, TXDMA + DMR, 0x14);
  3933. write_reg(info, RXDMA + DMR, 0x14);
  3934. /* Set chain pointer base (upper 8 bits of 24 bit addr) */
  3935. write_reg(info, RXDMA + CPB,
  3936. (unsigned char)(info->buffer_list_phys >> 16));
  3937. /* Set chain pointer base (upper 8 bits of 24 bit addr) */
  3938. write_reg(info, TXDMA + CPB,
  3939. (unsigned char)(info->buffer_list_phys >> 16));
  3940. /* enable status interrupts. other code enables/disables
  3941. * the individual sources for these two interrupt classes.
  3942. */
  3943. info->ie0_value |= TXINTE + RXINTE;
  3944. write_reg(info, IE0, info->ie0_value);
  3945. /* CTL, MSCI control register
  3946. *
  3947. * 07..06 Reserved, set to 0
  3948. * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
  3949. * 04 IDLC, idle control, 0=mark 1=idle register
  3950. * 03 BRK, break, 0=off 1 =on (async)
  3951. * 02 SYNCLD, sync char load enable (BSC) 1=enabled
  3952. * 01 GOP, go active on poll (LOOP mode) 1=enabled
  3953. * 00 RTS, RTS output control, 0=active 1=inactive
  3954. *
  3955. * 0001 0001
  3956. */
  3957. RegValue = 0x10;
  3958. if (!(info->serial_signals & SerialSignal_RTS))
  3959. RegValue |= 0x01;
  3960. write_reg(info, CTL, RegValue);
  3961. /* preamble not supported ! */
  3962. tx_set_idle(info);
  3963. tx_stop(info);
  3964. rx_stop(info);
  3965. set_rate(info, info->params.clock_speed);
  3966. if (info->params.loopback)
  3967. enable_loopback(info,1);
  3968. }
  3969. /* Set the transmit HDLC idle mode
  3970. */
  3971. void tx_set_idle(SLMP_INFO *info)
  3972. {
  3973. unsigned char RegValue = 0xff;
  3974. /* Map API idle mode to SCA register bits */
  3975. switch(info->idle_mode) {
  3976. case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
  3977. case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
  3978. case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
  3979. case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
  3980. case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
  3981. case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
  3982. case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
  3983. }
  3984. write_reg(info, IDL, RegValue);
  3985. }
  3986. /* Query the adapter for the state of the V24 status (input) signals.
  3987. */
  3988. void get_signals(SLMP_INFO *info)
  3989. {
  3990. u16 status = read_reg(info, SR3);
  3991. u16 gpstatus = read_status_reg(info);
  3992. u16 testbit;
  3993. /* clear all serial signals except DTR and RTS */
  3994. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3995. /* set serial signal bits to reflect MISR */
  3996. if (!(status & BIT3))
  3997. info->serial_signals |= SerialSignal_CTS;
  3998. if ( !(status & BIT2))
  3999. info->serial_signals |= SerialSignal_DCD;
  4000. testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
  4001. if (!(gpstatus & testbit))
  4002. info->serial_signals |= SerialSignal_RI;
  4003. testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
  4004. if (!(gpstatus & testbit))
  4005. info->serial_signals |= SerialSignal_DSR;
  4006. }
  4007. /* Set the state of DTR and RTS based on contents of
  4008. * serial_signals member of device context.
  4009. */
  4010. void set_signals(SLMP_INFO *info)
  4011. {
  4012. unsigned char RegValue;
  4013. u16 EnableBit;
  4014. RegValue = read_reg(info, CTL);
  4015. if (info->serial_signals & SerialSignal_RTS)
  4016. RegValue &= ~BIT0;
  4017. else
  4018. RegValue |= BIT0;
  4019. write_reg(info, CTL, RegValue);
  4020. // Port 0..3 DTR is ctrl reg <1,3,5,7>
  4021. EnableBit = BIT1 << (info->port_num*2);
  4022. if (info->serial_signals & SerialSignal_DTR)
  4023. info->port_array[0]->ctrlreg_value &= ~EnableBit;
  4024. else
  4025. info->port_array[0]->ctrlreg_value |= EnableBit;
  4026. write_control_reg(info);
  4027. }
  4028. /*******************/
  4029. /* DMA Buffer Code */
  4030. /*******************/
  4031. /* Set the count for all receive buffers to SCABUFSIZE
  4032. * and set the current buffer to the first buffer. This effectively
  4033. * makes all buffers free and discards any data in buffers.
  4034. */
  4035. void rx_reset_buffers(SLMP_INFO *info)
  4036. {
  4037. rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
  4038. }
  4039. /* Free the buffers used by a received frame
  4040. *
  4041. * info pointer to device instance data
  4042. * first index of 1st receive buffer of frame
  4043. * last index of last receive buffer of frame
  4044. */
  4045. void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
  4046. {
  4047. int done = 0;
  4048. while(!done) {
  4049. /* reset current buffer for reuse */
  4050. info->rx_buf_list[first].status = 0xff;
  4051. if (first == last) {
  4052. done = 1;
  4053. /* set new last rx descriptor address */
  4054. write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
  4055. }
  4056. first++;
  4057. if (first == info->rx_buf_count)
  4058. first = 0;
  4059. }
  4060. /* set current buffer to next buffer after last buffer of frame */
  4061. info->current_rx_buf = first;
  4062. }
  4063. /* Return a received frame from the receive DMA buffers.
  4064. * Only frames received without errors are returned.
  4065. *
  4066. * Return Value: 1 if frame returned, otherwise 0
  4067. */
  4068. int rx_get_frame(SLMP_INFO *info)
  4069. {
  4070. unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
  4071. unsigned short status;
  4072. unsigned int framesize = 0;
  4073. int ReturnCode = 0;
  4074. unsigned long flags;
  4075. struct tty_struct *tty = info->tty;
  4076. unsigned char addr_field = 0xff;
  4077. SCADESC *desc;
  4078. SCADESC_EX *desc_ex;
  4079. CheckAgain:
  4080. /* assume no frame returned, set zero length */
  4081. framesize = 0;
  4082. addr_field = 0xff;
  4083. /*
  4084. * current_rx_buf points to the 1st buffer of the next available
  4085. * receive frame. To find the last buffer of the frame look for
  4086. * a non-zero status field in the buffer entries. (The status
  4087. * field is set by the 16C32 after completing a receive frame.
  4088. */
  4089. StartIndex = EndIndex = info->current_rx_buf;
  4090. for ( ;; ) {
  4091. desc = &info->rx_buf_list[EndIndex];
  4092. desc_ex = &info->rx_buf_list_ex[EndIndex];
  4093. if (desc->status == 0xff)
  4094. goto Cleanup; /* current desc still in use, no frames available */
  4095. if (framesize == 0 && info->params.addr_filter != 0xff)
  4096. addr_field = desc_ex->virt_addr[0];
  4097. framesize += desc->length;
  4098. /* Status != 0 means last buffer of frame */
  4099. if (desc->status)
  4100. break;
  4101. EndIndex++;
  4102. if (EndIndex == info->rx_buf_count)
  4103. EndIndex = 0;
  4104. if (EndIndex == info->current_rx_buf) {
  4105. /* all buffers have been 'used' but none mark */
  4106. /* the end of a frame. Reset buffers and receiver. */
  4107. if ( info->rx_enabled ){
  4108. spin_lock_irqsave(&info->lock,flags);
  4109. rx_start(info);
  4110. spin_unlock_irqrestore(&info->lock,flags);
  4111. }
  4112. goto Cleanup;
  4113. }
  4114. }
  4115. /* check status of receive frame */
  4116. /* frame status is byte stored after frame data
  4117. *
  4118. * 7 EOM (end of msg), 1 = last buffer of frame
  4119. * 6 Short Frame, 1 = short frame
  4120. * 5 Abort, 1 = frame aborted
  4121. * 4 Residue, 1 = last byte is partial
  4122. * 3 Overrun, 1 = overrun occurred during frame reception
  4123. * 2 CRC, 1 = CRC error detected
  4124. *
  4125. */
  4126. status = desc->status;
  4127. /* ignore CRC bit if not using CRC (bit is undefined) */
  4128. /* Note:CRC is not save to data buffer */
  4129. if (info->params.crc_type == HDLC_CRC_NONE)
  4130. status &= ~BIT2;
  4131. if (framesize == 0 ||
  4132. (addr_field != 0xff && addr_field != info->params.addr_filter)) {
  4133. /* discard 0 byte frames, this seems to occur sometime
  4134. * when remote is idling flags.
  4135. */
  4136. rx_free_frame_buffers(info, StartIndex, EndIndex);
  4137. goto CheckAgain;
  4138. }
  4139. if (framesize < 2)
  4140. status |= BIT6;
  4141. if (status & (BIT6+BIT5+BIT3+BIT2)) {
  4142. /* received frame has errors,
  4143. * update counts and mark frame size as 0
  4144. */
  4145. if (status & BIT6)
  4146. info->icount.rxshort++;
  4147. else if (status & BIT5)
  4148. info->icount.rxabort++;
  4149. else if (status & BIT3)
  4150. info->icount.rxover++;
  4151. else
  4152. info->icount.rxcrc++;
  4153. framesize = 0;
  4154. #if SYNCLINK_GENERIC_HDLC
  4155. {
  4156. struct net_device_stats *stats = hdlc_stats(info->netdev);
  4157. stats->rx_errors++;
  4158. stats->rx_frame_errors++;
  4159. }
  4160. #endif
  4161. }
  4162. if ( debug_level >= DEBUG_LEVEL_BH )
  4163. printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
  4164. __FILE__,__LINE__,info->device_name,status,framesize);
  4165. if ( debug_level >= DEBUG_LEVEL_DATA )
  4166. trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
  4167. min_t(int, framesize,SCABUFSIZE),0);
  4168. if (framesize) {
  4169. if (framesize > info->max_frame_size)
  4170. info->icount.rxlong++;
  4171. else {
  4172. /* copy dma buffer(s) to contiguous intermediate buffer */
  4173. int copy_count = framesize;
  4174. int index = StartIndex;
  4175. unsigned char *ptmp = info->tmp_rx_buf;
  4176. info->tmp_rx_buf_count = framesize;
  4177. info->icount.rxok++;
  4178. while(copy_count) {
  4179. int partial_count = min(copy_count,SCABUFSIZE);
  4180. memcpy( ptmp,
  4181. info->rx_buf_list_ex[index].virt_addr,
  4182. partial_count );
  4183. ptmp += partial_count;
  4184. copy_count -= partial_count;
  4185. if ( ++index == info->rx_buf_count )
  4186. index = 0;
  4187. }
  4188. #if SYNCLINK_GENERIC_HDLC
  4189. if (info->netcount)
  4190. hdlcdev_rx(info,info->tmp_rx_buf,framesize);
  4191. else
  4192. #endif
  4193. ldisc_receive_buf(tty,info->tmp_rx_buf,
  4194. info->flag_buf, framesize);
  4195. }
  4196. }
  4197. /* Free the buffers used by this frame. */
  4198. rx_free_frame_buffers( info, StartIndex, EndIndex );
  4199. ReturnCode = 1;
  4200. Cleanup:
  4201. if ( info->rx_enabled && info->rx_overflow ) {
  4202. /* Receiver is enabled, but needs to restarted due to
  4203. * rx buffer overflow. If buffers are empty, restart receiver.
  4204. */
  4205. if (info->rx_buf_list[EndIndex].status == 0xff) {
  4206. spin_lock_irqsave(&info->lock,flags);
  4207. rx_start(info);
  4208. spin_unlock_irqrestore(&info->lock,flags);
  4209. }
  4210. }
  4211. return ReturnCode;
  4212. }
  4213. /* load the transmit DMA buffer with data
  4214. */
  4215. void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
  4216. {
  4217. unsigned short copy_count;
  4218. unsigned int i = 0;
  4219. SCADESC *desc;
  4220. SCADESC_EX *desc_ex;
  4221. if ( debug_level >= DEBUG_LEVEL_DATA )
  4222. trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
  4223. /* Copy source buffer to one or more DMA buffers, starting with
  4224. * the first transmit dma buffer.
  4225. */
  4226. for(i=0;;)
  4227. {
  4228. copy_count = min_t(unsigned short,count,SCABUFSIZE);
  4229. desc = &info->tx_buf_list[i];
  4230. desc_ex = &info->tx_buf_list_ex[i];
  4231. load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
  4232. desc->length = copy_count;
  4233. desc->status = 0;
  4234. buf += copy_count;
  4235. count -= copy_count;
  4236. if (!count)
  4237. break;
  4238. i++;
  4239. if (i >= info->tx_buf_count)
  4240. i = 0;
  4241. }
  4242. info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
  4243. info->last_tx_buf = ++i;
  4244. }
  4245. int register_test(SLMP_INFO *info)
  4246. {
  4247. static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
  4248. static unsigned int count = ARRAY_SIZE(testval);
  4249. unsigned int i;
  4250. int rc = TRUE;
  4251. unsigned long flags;
  4252. spin_lock_irqsave(&info->lock,flags);
  4253. reset_port(info);
  4254. /* assume failure */
  4255. info->init_error = DiagStatus_AddressFailure;
  4256. /* Write bit patterns to various registers but do it out of */
  4257. /* sync, then read back and verify values. */
  4258. for (i = 0 ; i < count ; i++) {
  4259. write_reg(info, TMC, testval[i]);
  4260. write_reg(info, IDL, testval[(i+1)%count]);
  4261. write_reg(info, SA0, testval[(i+2)%count]);
  4262. write_reg(info, SA1, testval[(i+3)%count]);
  4263. if ( (read_reg(info, TMC) != testval[i]) ||
  4264. (read_reg(info, IDL) != testval[(i+1)%count]) ||
  4265. (read_reg(info, SA0) != testval[(i+2)%count]) ||
  4266. (read_reg(info, SA1) != testval[(i+3)%count]) )
  4267. {
  4268. rc = FALSE;
  4269. break;
  4270. }
  4271. }
  4272. reset_port(info);
  4273. spin_unlock_irqrestore(&info->lock,flags);
  4274. return rc;
  4275. }
  4276. int irq_test(SLMP_INFO *info)
  4277. {
  4278. unsigned long timeout;
  4279. unsigned long flags;
  4280. unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
  4281. spin_lock_irqsave(&info->lock,flags);
  4282. reset_port(info);
  4283. /* assume failure */
  4284. info->init_error = DiagStatus_IrqFailure;
  4285. info->irq_occurred = FALSE;
  4286. /* setup timer0 on SCA0 to interrupt */
  4287. /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
  4288. write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
  4289. write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
  4290. write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
  4291. /* TMCS, Timer Control/Status Register
  4292. *
  4293. * 07 CMF, Compare match flag (read only) 1=match
  4294. * 06 ECMI, CMF Interrupt Enable: 1=enabled
  4295. * 05 Reserved, must be 0
  4296. * 04 TME, Timer Enable
  4297. * 03..00 Reserved, must be 0
  4298. *
  4299. * 0101 0000
  4300. */
  4301. write_reg(info, (unsigned char)(timer + TMCS), 0x50);
  4302. spin_unlock_irqrestore(&info->lock,flags);
  4303. timeout=100;
  4304. while( timeout-- && !info->irq_occurred ) {
  4305. msleep_interruptible(10);
  4306. }
  4307. spin_lock_irqsave(&info->lock,flags);
  4308. reset_port(info);
  4309. spin_unlock_irqrestore(&info->lock,flags);
  4310. return info->irq_occurred;
  4311. }
  4312. /* initialize individual SCA device (2 ports)
  4313. */
  4314. static int sca_init(SLMP_INFO *info)
  4315. {
  4316. /* set wait controller to single mem partition (low), no wait states */
  4317. write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
  4318. write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
  4319. write_reg(info, WCRL, 0); /* wait controller low range */
  4320. write_reg(info, WCRM, 0); /* wait controller mid range */
  4321. write_reg(info, WCRH, 0); /* wait controller high range */
  4322. /* DPCR, DMA Priority Control
  4323. *
  4324. * 07..05 Not used, must be 0
  4325. * 04 BRC, bus release condition: 0=all transfers complete
  4326. * 03 CCC, channel change condition: 0=every cycle
  4327. * 02..00 PR<2..0>, priority 100=round robin
  4328. *
  4329. * 00000100 = 0x04
  4330. */
  4331. write_reg(info, DPCR, dma_priority);
  4332. /* DMA Master Enable, BIT7: 1=enable all channels */
  4333. write_reg(info, DMER, 0x80);
  4334. /* enable all interrupt classes */
  4335. write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
  4336. write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
  4337. write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
  4338. /* ITCR, interrupt control register
  4339. * 07 IPC, interrupt priority, 0=MSCI->DMA
  4340. * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
  4341. * 04 VOS, Vector Output, 0=unmodified vector
  4342. * 03..00 Reserved, must be 0
  4343. */
  4344. write_reg(info, ITCR, 0);
  4345. return TRUE;
  4346. }
  4347. /* initialize adapter hardware
  4348. */
  4349. int init_adapter(SLMP_INFO *info)
  4350. {
  4351. int i;
  4352. /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
  4353. volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
  4354. u32 readval;
  4355. info->misc_ctrl_value |= BIT30;
  4356. *MiscCtrl = info->misc_ctrl_value;
  4357. /*
  4358. * Force at least 170ns delay before clearing
  4359. * reset bit. Each read from LCR takes at least
  4360. * 30ns so 10 times for 300ns to be safe.
  4361. */
  4362. for(i=0;i<10;i++)
  4363. readval = *MiscCtrl;
  4364. info->misc_ctrl_value &= ~BIT30;
  4365. *MiscCtrl = info->misc_ctrl_value;
  4366. /* init control reg (all DTRs off, all clksel=input) */
  4367. info->ctrlreg_value = 0xaa;
  4368. write_control_reg(info);
  4369. {
  4370. volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
  4371. lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
  4372. switch(read_ahead_count)
  4373. {
  4374. case 16:
  4375. lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
  4376. break;
  4377. case 8:
  4378. lcr1_brdr_value |= BIT5 + BIT4;
  4379. break;
  4380. case 4:
  4381. lcr1_brdr_value |= BIT5 + BIT3;
  4382. break;
  4383. case 0:
  4384. lcr1_brdr_value |= BIT5;
  4385. break;
  4386. }
  4387. *LCR1BRDR = lcr1_brdr_value;
  4388. *MiscCtrl = misc_ctrl_value;
  4389. }
  4390. sca_init(info->port_array[0]);
  4391. sca_init(info->port_array[2]);
  4392. return TRUE;
  4393. }
  4394. /* Loopback an HDLC frame to test the hardware
  4395. * interrupt and DMA functions.
  4396. */
  4397. int loopback_test(SLMP_INFO *info)
  4398. {
  4399. #define TESTFRAMESIZE 20
  4400. unsigned long timeout;
  4401. u16 count = TESTFRAMESIZE;
  4402. unsigned char buf[TESTFRAMESIZE];
  4403. int rc = FALSE;
  4404. unsigned long flags;
  4405. struct tty_struct *oldtty = info->tty;
  4406. u32 speed = info->params.clock_speed;
  4407. info->params.clock_speed = 3686400;
  4408. info->tty = NULL;
  4409. /* assume failure */
  4410. info->init_error = DiagStatus_DmaFailure;
  4411. /* build and send transmit frame */
  4412. for (count = 0; count < TESTFRAMESIZE;++count)
  4413. buf[count] = (unsigned char)count;
  4414. memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
  4415. /* program hardware for HDLC and enabled receiver */
  4416. spin_lock_irqsave(&info->lock,flags);
  4417. hdlc_mode(info);
  4418. enable_loopback(info,1);
  4419. rx_start(info);
  4420. info->tx_count = count;
  4421. tx_load_dma_buffer(info,buf,count);
  4422. tx_start(info);
  4423. spin_unlock_irqrestore(&info->lock,flags);
  4424. /* wait for receive complete */
  4425. /* Set a timeout for waiting for interrupt. */
  4426. for ( timeout = 100; timeout; --timeout ) {
  4427. msleep_interruptible(10);
  4428. if (rx_get_frame(info)) {
  4429. rc = TRUE;
  4430. break;
  4431. }
  4432. }
  4433. /* verify received frame length and contents */
  4434. if (rc == TRUE &&
  4435. ( info->tmp_rx_buf_count != count ||
  4436. memcmp(buf, info->tmp_rx_buf,count))) {
  4437. rc = FALSE;
  4438. }
  4439. spin_lock_irqsave(&info->lock,flags);
  4440. reset_adapter(info);
  4441. spin_unlock_irqrestore(&info->lock,flags);
  4442. info->params.clock_speed = speed;
  4443. info->tty = oldtty;
  4444. return rc;
  4445. }
  4446. /* Perform diagnostics on hardware
  4447. */
  4448. int adapter_test( SLMP_INFO *info )
  4449. {
  4450. unsigned long flags;
  4451. if ( debug_level >= DEBUG_LEVEL_INFO )
  4452. printk( "%s(%d):Testing device %s\n",
  4453. __FILE__,__LINE__,info->device_name );
  4454. spin_lock_irqsave(&info->lock,flags);
  4455. init_adapter(info);
  4456. spin_unlock_irqrestore(&info->lock,flags);
  4457. info->port_array[0]->port_count = 0;
  4458. if ( register_test(info->port_array[0]) &&
  4459. register_test(info->port_array[1])) {
  4460. info->port_array[0]->port_count = 2;
  4461. if ( register_test(info->port_array[2]) &&
  4462. register_test(info->port_array[3]) )
  4463. info->port_array[0]->port_count += 2;
  4464. }
  4465. else {
  4466. printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
  4467. __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
  4468. return -ENODEV;
  4469. }
  4470. if ( !irq_test(info->port_array[0]) ||
  4471. !irq_test(info->port_array[1]) ||
  4472. (info->port_count == 4 && !irq_test(info->port_array[2])) ||
  4473. (info->port_count == 4 && !irq_test(info->port_array[3]))) {
  4474. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  4475. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  4476. return -ENODEV;
  4477. }
  4478. if (!loopback_test(info->port_array[0]) ||
  4479. !loopback_test(info->port_array[1]) ||
  4480. (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
  4481. (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
  4482. printk( "%s(%d):DMA test failure for device %s\n",
  4483. __FILE__,__LINE__,info->device_name);
  4484. return -ENODEV;
  4485. }
  4486. if ( debug_level >= DEBUG_LEVEL_INFO )
  4487. printk( "%s(%d):device %s passed diagnostics\n",
  4488. __FILE__,__LINE__,info->device_name );
  4489. info->port_array[0]->init_error = 0;
  4490. info->port_array[1]->init_error = 0;
  4491. if ( info->port_count > 2 ) {
  4492. info->port_array[2]->init_error = 0;
  4493. info->port_array[3]->init_error = 0;
  4494. }
  4495. return 0;
  4496. }
  4497. /* Test the shared memory on a PCI adapter.
  4498. */
  4499. int memory_test(SLMP_INFO *info)
  4500. {
  4501. static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
  4502. 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
  4503. unsigned long count = ARRAY_SIZE(testval);
  4504. unsigned long i;
  4505. unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
  4506. unsigned long * addr = (unsigned long *)info->memory_base;
  4507. /* Test data lines with test pattern at one location. */
  4508. for ( i = 0 ; i < count ; i++ ) {
  4509. *addr = testval[i];
  4510. if ( *addr != testval[i] )
  4511. return FALSE;
  4512. }
  4513. /* Test address lines with incrementing pattern over */
  4514. /* entire address range. */
  4515. for ( i = 0 ; i < limit ; i++ ) {
  4516. *addr = i * 4;
  4517. addr++;
  4518. }
  4519. addr = (unsigned long *)info->memory_base;
  4520. for ( i = 0 ; i < limit ; i++ ) {
  4521. if ( *addr != i * 4 )
  4522. return FALSE;
  4523. addr++;
  4524. }
  4525. memset( info->memory_base, 0, SCA_MEM_SIZE );
  4526. return TRUE;
  4527. }
  4528. /* Load data into PCI adapter shared memory.
  4529. *
  4530. * The PCI9050 releases control of the local bus
  4531. * after completing the current read or write operation.
  4532. *
  4533. * While the PCI9050 write FIFO not empty, the
  4534. * PCI9050 treats all of the writes as a single transaction
  4535. * and does not release the bus. This causes DMA latency problems
  4536. * at high speeds when copying large data blocks to the shared memory.
  4537. *
  4538. * This function breaks a write into multiple transations by
  4539. * interleaving a read which flushes the write FIFO and 'completes'
  4540. * the write transation. This allows any pending DMA request to gain control
  4541. * of the local bus in a timely fasion.
  4542. */
  4543. void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
  4544. {
  4545. /* A load interval of 16 allows for 4 32-bit writes at */
  4546. /* 136ns each for a maximum latency of 542ns on the local bus.*/
  4547. unsigned short interval = count / sca_pci_load_interval;
  4548. unsigned short i;
  4549. for ( i = 0 ; i < interval ; i++ )
  4550. {
  4551. memcpy(dest, src, sca_pci_load_interval);
  4552. read_status_reg(info);
  4553. dest += sca_pci_load_interval;
  4554. src += sca_pci_load_interval;
  4555. }
  4556. memcpy(dest, src, count % sca_pci_load_interval);
  4557. }
  4558. void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
  4559. {
  4560. int i;
  4561. int linecount;
  4562. if (xmit)
  4563. printk("%s tx data:\n",info->device_name);
  4564. else
  4565. printk("%s rx data:\n",info->device_name);
  4566. while(count) {
  4567. if (count > 16)
  4568. linecount = 16;
  4569. else
  4570. linecount = count;
  4571. for(i=0;i<linecount;i++)
  4572. printk("%02X ",(unsigned char)data[i]);
  4573. for(;i<17;i++)
  4574. printk(" ");
  4575. for(i=0;i<linecount;i++) {
  4576. if (data[i]>=040 && data[i]<=0176)
  4577. printk("%c",data[i]);
  4578. else
  4579. printk(".");
  4580. }
  4581. printk("\n");
  4582. data += linecount;
  4583. count -= linecount;
  4584. }
  4585. } /* end of trace_block() */
  4586. /* called when HDLC frame times out
  4587. * update stats and do tx completion processing
  4588. */
  4589. void tx_timeout(unsigned long context)
  4590. {
  4591. SLMP_INFO *info = (SLMP_INFO*)context;
  4592. unsigned long flags;
  4593. if ( debug_level >= DEBUG_LEVEL_INFO )
  4594. printk( "%s(%d):%s tx_timeout()\n",
  4595. __FILE__,__LINE__,info->device_name);
  4596. if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
  4597. info->icount.txtimeout++;
  4598. }
  4599. spin_lock_irqsave(&info->lock,flags);
  4600. info->tx_active = 0;
  4601. info->tx_count = info->tx_put = info->tx_get = 0;
  4602. spin_unlock_irqrestore(&info->lock,flags);
  4603. #if SYNCLINK_GENERIC_HDLC
  4604. if (info->netcount)
  4605. hdlcdev_tx_done(info);
  4606. else
  4607. #endif
  4608. bh_transmit(info);
  4609. }
  4610. /* called to periodically check the DSR/RI modem signal input status
  4611. */
  4612. void status_timeout(unsigned long context)
  4613. {
  4614. u16 status = 0;
  4615. SLMP_INFO *info = (SLMP_INFO*)context;
  4616. unsigned long flags;
  4617. unsigned char delta;
  4618. spin_lock_irqsave(&info->lock,flags);
  4619. get_signals(info);
  4620. spin_unlock_irqrestore(&info->lock,flags);
  4621. /* check for DSR/RI state change */
  4622. delta = info->old_signals ^ info->serial_signals;
  4623. info->old_signals = info->serial_signals;
  4624. if (delta & SerialSignal_DSR)
  4625. status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
  4626. if (delta & SerialSignal_RI)
  4627. status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
  4628. if (delta & SerialSignal_DCD)
  4629. status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
  4630. if (delta & SerialSignal_CTS)
  4631. status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
  4632. if (status)
  4633. isr_io_pin(info,status);
  4634. mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
  4635. }
  4636. /* Register Access Routines -
  4637. * All registers are memory mapped
  4638. */
  4639. #define CALC_REGADDR() \
  4640. unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
  4641. if (info->port_num > 1) \
  4642. RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
  4643. if ( info->port_num & 1) { \
  4644. if (Addr > 0x7f) \
  4645. RegAddr += 0x40; /* DMA access */ \
  4646. else if (Addr > 0x1f && Addr < 0x60) \
  4647. RegAddr += 0x20; /* MSCI access */ \
  4648. }
  4649. unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
  4650. {
  4651. CALC_REGADDR();
  4652. return *RegAddr;
  4653. }
  4654. void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
  4655. {
  4656. CALC_REGADDR();
  4657. *RegAddr = Value;
  4658. }
  4659. u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
  4660. {
  4661. CALC_REGADDR();
  4662. return *((u16 *)RegAddr);
  4663. }
  4664. void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
  4665. {
  4666. CALC_REGADDR();
  4667. *((u16 *)RegAddr) = Value;
  4668. }
  4669. unsigned char read_status_reg(SLMP_INFO * info)
  4670. {
  4671. unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
  4672. return *RegAddr;
  4673. }
  4674. void write_control_reg(SLMP_INFO * info)
  4675. {
  4676. unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
  4677. *RegAddr = info->port_array[0]->ctrlreg_value;
  4678. }
  4679. static int __devinit synclinkmp_init_one (struct pci_dev *dev,
  4680. const struct pci_device_id *ent)
  4681. {
  4682. if (pci_enable_device(dev)) {
  4683. printk("error enabling pci device %p\n", dev);
  4684. return -EIO;
  4685. }
  4686. device_init( ++synclinkmp_adapter_count, dev );
  4687. return 0;
  4688. }
  4689. static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
  4690. {
  4691. }