synclink_gt.c 121 KB

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  1. /*
  2. * $Id: synclink_gt.c,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  3. *
  4. * Device driver for Microgate SyncLink GT serial adapters.
  5. *
  6. * written by Paul Fulghum for Microgate Corporation
  7. * paulkf@microgate.com
  8. *
  9. * Microgate and SyncLink are trademarks of Microgate Corporation
  10. *
  11. * This code is released under the GNU General Public License (GPL)
  12. *
  13. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23. * OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. /*
  26. * DEBUG OUTPUT DEFINITIONS
  27. *
  28. * uncomment lines below to enable specific types of debug output
  29. *
  30. * DBGINFO information - most verbose output
  31. * DBGERR serious errors
  32. * DBGBH bottom half service routine debugging
  33. * DBGISR interrupt service routine debugging
  34. * DBGDATA output receive and transmit data
  35. * DBGTBUF output transmit DMA buffers and registers
  36. * DBGRBUF output receive DMA buffers and registers
  37. */
  38. #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39. #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40. #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41. #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42. #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43. //#define DBGTBUF(info) dump_tbufs(info)
  44. //#define DBGRBUF(info) dump_rbufs(info)
  45. #include <linux/module.h>
  46. #include <linux/version.h>
  47. #include <linux/errno.h>
  48. #include <linux/signal.h>
  49. #include <linux/sched.h>
  50. #include <linux/timer.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/pci.h>
  53. #include <linux/tty.h>
  54. #include <linux/tty_flip.h>
  55. #include <linux/serial.h>
  56. #include <linux/major.h>
  57. #include <linux/string.h>
  58. #include <linux/fcntl.h>
  59. #include <linux/ptrace.h>
  60. #include <linux/ioport.h>
  61. #include <linux/mm.h>
  62. #include <linux/slab.h>
  63. #include <linux/netdevice.h>
  64. #include <linux/vmalloc.h>
  65. #include <linux/init.h>
  66. #include <linux/delay.h>
  67. #include <linux/ioctl.h>
  68. #include <linux/termios.h>
  69. #include <linux/bitops.h>
  70. #include <linux/workqueue.h>
  71. #include <linux/hdlc.h>
  72. #include <asm/system.h>
  73. #include <asm/io.h>
  74. #include <asm/irq.h>
  75. #include <asm/dma.h>
  76. #include <asm/types.h>
  77. #include <asm/uaccess.h>
  78. #include "linux/synclink.h"
  79. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  80. #define SYNCLINK_GENERIC_HDLC 1
  81. #else
  82. #define SYNCLINK_GENERIC_HDLC 0
  83. #endif
  84. /*
  85. * module identification
  86. */
  87. static char *driver_name = "SyncLink GT";
  88. static char *driver_version = "$Revision: 1.1.1.1 $";
  89. static char *tty_driver_name = "synclink_gt";
  90. static char *tty_dev_prefix = "ttySLG";
  91. MODULE_LICENSE("GPL");
  92. #define MGSL_MAGIC 0x5401
  93. #define MAX_DEVICES 32
  94. static struct pci_device_id pci_table[] = {
  95. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  96. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  97. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  98. {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99. {0,}, /* terminate list */
  100. };
  101. MODULE_DEVICE_TABLE(pci, pci_table);
  102. static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
  103. static void remove_one(struct pci_dev *dev);
  104. static struct pci_driver pci_driver = {
  105. .name = "synclink_gt",
  106. .id_table = pci_table,
  107. .probe = init_one,
  108. .remove = __devexit_p(remove_one),
  109. };
  110. static int pci_registered;
  111. /*
  112. * module configuration and status
  113. */
  114. static struct slgt_info *slgt_device_list;
  115. static int slgt_device_count;
  116. static int ttymajor;
  117. static int debug_level;
  118. static int maxframe[MAX_DEVICES];
  119. static int dosyncppp[MAX_DEVICES];
  120. module_param(ttymajor, int, 0);
  121. module_param(debug_level, int, 0);
  122. module_param_array(maxframe, int, NULL, 0);
  123. module_param_array(dosyncppp, int, NULL, 0);
  124. MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
  125. MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
  126. MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
  127. MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
  128. /*
  129. * tty support and callbacks
  130. */
  131. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  132. static struct tty_driver *serial_driver;
  133. static int open(struct tty_struct *tty, struct file * filp);
  134. static void close(struct tty_struct *tty, struct file * filp);
  135. static void hangup(struct tty_struct *tty);
  136. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
  137. static int write(struct tty_struct *tty, const unsigned char *buf, int count);
  138. static void put_char(struct tty_struct *tty, unsigned char ch);
  139. static void send_xchar(struct tty_struct *tty, char ch);
  140. static void wait_until_sent(struct tty_struct *tty, int timeout);
  141. static int write_room(struct tty_struct *tty);
  142. static void flush_chars(struct tty_struct *tty);
  143. static void flush_buffer(struct tty_struct *tty);
  144. static void tx_hold(struct tty_struct *tty);
  145. static void tx_release(struct tty_struct *tty);
  146. static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
  147. static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
  148. static int chars_in_buffer(struct tty_struct *tty);
  149. static void throttle(struct tty_struct * tty);
  150. static void unthrottle(struct tty_struct * tty);
  151. static void set_break(struct tty_struct *tty, int break_state);
  152. /*
  153. * generic HDLC support and callbacks
  154. */
  155. #if SYNCLINK_GENERIC_HDLC
  156. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  157. static void hdlcdev_tx_done(struct slgt_info *info);
  158. static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
  159. static int hdlcdev_init(struct slgt_info *info);
  160. static void hdlcdev_exit(struct slgt_info *info);
  161. #endif
  162. /*
  163. * device specific structures, macros and functions
  164. */
  165. #define SLGT_MAX_PORTS 4
  166. #define SLGT_REG_SIZE 256
  167. /*
  168. * conditional wait facility
  169. */
  170. struct cond_wait {
  171. struct cond_wait *next;
  172. wait_queue_head_t q;
  173. wait_queue_t wait;
  174. unsigned int data;
  175. };
  176. static void init_cond_wait(struct cond_wait *w, unsigned int data);
  177. static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
  178. static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
  179. static void flush_cond_wait(struct cond_wait **head);
  180. /*
  181. * DMA buffer descriptor and access macros
  182. */
  183. struct slgt_desc
  184. {
  185. unsigned short count;
  186. unsigned short status;
  187. unsigned int pbuf; /* physical address of data buffer */
  188. unsigned int next; /* physical address of next descriptor */
  189. /* driver book keeping */
  190. char *buf; /* virtual address of data buffer */
  191. unsigned int pdesc; /* physical address of this descriptor */
  192. dma_addr_t buf_dma_addr;
  193. };
  194. #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
  195. #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
  196. #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
  197. #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
  198. #define desc_count(a) (le16_to_cpu((a).count))
  199. #define desc_status(a) (le16_to_cpu((a).status))
  200. #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
  201. #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
  202. #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
  203. #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
  204. #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
  205. struct _input_signal_events {
  206. int ri_up;
  207. int ri_down;
  208. int dsr_up;
  209. int dsr_down;
  210. int dcd_up;
  211. int dcd_down;
  212. int cts_up;
  213. int cts_down;
  214. };
  215. /*
  216. * device instance data structure
  217. */
  218. struct slgt_info {
  219. void *if_ptr; /* General purpose pointer (used by SPPP) */
  220. struct slgt_info *next_device; /* device list link */
  221. int magic;
  222. int flags;
  223. char device_name[25];
  224. struct pci_dev *pdev;
  225. int port_count; /* count of ports on adapter */
  226. int adapter_num; /* adapter instance number */
  227. int port_num; /* port instance number */
  228. /* array of pointers to port contexts on this adapter */
  229. struct slgt_info *port_array[SLGT_MAX_PORTS];
  230. int count; /* count of opens */
  231. int line; /* tty line instance number */
  232. unsigned short close_delay;
  233. unsigned short closing_wait; /* time to wait before closing */
  234. struct mgsl_icount icount;
  235. struct tty_struct *tty;
  236. int timeout;
  237. int x_char; /* xon/xoff character */
  238. int blocked_open; /* # of blocked opens */
  239. unsigned int read_status_mask;
  240. unsigned int ignore_status_mask;
  241. wait_queue_head_t open_wait;
  242. wait_queue_head_t close_wait;
  243. wait_queue_head_t status_event_wait_q;
  244. wait_queue_head_t event_wait_q;
  245. struct timer_list tx_timer;
  246. struct timer_list rx_timer;
  247. unsigned int gpio_present;
  248. struct cond_wait *gpio_wait_q;
  249. spinlock_t lock; /* spinlock for synchronizing with ISR */
  250. struct work_struct task;
  251. u32 pending_bh;
  252. int bh_requested;
  253. int bh_running;
  254. int isr_overflow;
  255. int irq_requested; /* nonzero if IRQ requested */
  256. int irq_occurred; /* for diagnostics use */
  257. /* device configuration */
  258. unsigned int bus_type;
  259. unsigned int irq_level;
  260. unsigned long irq_flags;
  261. unsigned char __iomem * reg_addr; /* memory mapped registers address */
  262. u32 phys_reg_addr;
  263. int reg_addr_requested;
  264. MGSL_PARAMS params; /* communications parameters */
  265. u32 idle_mode;
  266. u32 max_frame_size; /* as set by device config */
  267. unsigned int raw_rx_size;
  268. unsigned int if_mode;
  269. /* device status */
  270. int rx_enabled;
  271. int rx_restart;
  272. int tx_enabled;
  273. int tx_active;
  274. unsigned char signals; /* serial signal states */
  275. int init_error; /* initialization error */
  276. unsigned char *tx_buf;
  277. int tx_count;
  278. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  279. char char_buf[MAX_ASYNC_BUFFER_SIZE];
  280. BOOLEAN drop_rts_on_tx_done;
  281. struct _input_signal_events input_signal_events;
  282. int dcd_chkcount; /* check counts to prevent */
  283. int cts_chkcount; /* too many IRQs if a signal */
  284. int dsr_chkcount; /* is floating */
  285. int ri_chkcount;
  286. char *bufs; /* virtual address of DMA buffer lists */
  287. dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
  288. unsigned int rbuf_count;
  289. struct slgt_desc *rbufs;
  290. unsigned int rbuf_current;
  291. unsigned int rbuf_index;
  292. unsigned int tbuf_count;
  293. struct slgt_desc *tbufs;
  294. unsigned int tbuf_current;
  295. unsigned int tbuf_start;
  296. unsigned char *tmp_rbuf;
  297. unsigned int tmp_rbuf_count;
  298. /* SPPP/Cisco HDLC device parts */
  299. int netcount;
  300. int dosyncppp;
  301. spinlock_t netlock;
  302. #if SYNCLINK_GENERIC_HDLC
  303. struct net_device *netdev;
  304. #endif
  305. };
  306. static MGSL_PARAMS default_params = {
  307. .mode = MGSL_MODE_HDLC,
  308. .loopback = 0,
  309. .flags = HDLC_FLAG_UNDERRUN_ABORT15,
  310. .encoding = HDLC_ENCODING_NRZI_SPACE,
  311. .clock_speed = 0,
  312. .addr_filter = 0xff,
  313. .crc_type = HDLC_CRC_16_CCITT,
  314. .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
  315. .preamble = HDLC_PREAMBLE_PATTERN_NONE,
  316. .data_rate = 9600,
  317. .data_bits = 8,
  318. .stop_bits = 1,
  319. .parity = ASYNC_PARITY_NONE
  320. };
  321. #define BH_RECEIVE 1
  322. #define BH_TRANSMIT 2
  323. #define BH_STATUS 4
  324. #define IO_PIN_SHUTDOWN_LIMIT 100
  325. #define DMABUFSIZE 256
  326. #define DESC_LIST_SIZE 4096
  327. #define MASK_PARITY BIT1
  328. #define MASK_FRAMING BIT0
  329. #define MASK_BREAK BIT14
  330. #define MASK_OVERRUN BIT4
  331. #define GSR 0x00 /* global status */
  332. #define JCR 0x04 /* JTAG control */
  333. #define IODR 0x08 /* GPIO direction */
  334. #define IOER 0x0c /* GPIO interrupt enable */
  335. #define IOVR 0x10 /* GPIO value */
  336. #define IOSR 0x14 /* GPIO interrupt status */
  337. #define TDR 0x80 /* tx data */
  338. #define RDR 0x80 /* rx data */
  339. #define TCR 0x82 /* tx control */
  340. #define TIR 0x84 /* tx idle */
  341. #define TPR 0x85 /* tx preamble */
  342. #define RCR 0x86 /* rx control */
  343. #define VCR 0x88 /* V.24 control */
  344. #define CCR 0x89 /* clock control */
  345. #define BDR 0x8a /* baud divisor */
  346. #define SCR 0x8c /* serial control */
  347. #define SSR 0x8e /* serial status */
  348. #define RDCSR 0x90 /* rx DMA control/status */
  349. #define TDCSR 0x94 /* tx DMA control/status */
  350. #define RDDAR 0x98 /* rx DMA descriptor address */
  351. #define TDDAR 0x9c /* tx DMA descriptor address */
  352. #define RXIDLE BIT14
  353. #define RXBREAK BIT14
  354. #define IRQ_TXDATA BIT13
  355. #define IRQ_TXIDLE BIT12
  356. #define IRQ_TXUNDER BIT11 /* HDLC */
  357. #define IRQ_RXDATA BIT10
  358. #define IRQ_RXIDLE BIT9 /* HDLC */
  359. #define IRQ_RXBREAK BIT9 /* async */
  360. #define IRQ_RXOVER BIT8
  361. #define IRQ_DSR BIT7
  362. #define IRQ_CTS BIT6
  363. #define IRQ_DCD BIT5
  364. #define IRQ_RI BIT4
  365. #define IRQ_ALL 0x3ff0
  366. #define IRQ_MASTER BIT0
  367. #define slgt_irq_on(info, mask) \
  368. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
  369. #define slgt_irq_off(info, mask) \
  370. wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
  371. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
  372. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
  373. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
  374. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
  375. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
  376. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
  377. static void msc_set_vcr(struct slgt_info *info);
  378. static int startup(struct slgt_info *info);
  379. static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
  380. static void shutdown(struct slgt_info *info);
  381. static void program_hw(struct slgt_info *info);
  382. static void change_params(struct slgt_info *info);
  383. static int register_test(struct slgt_info *info);
  384. static int irq_test(struct slgt_info *info);
  385. static int loopback_test(struct slgt_info *info);
  386. static int adapter_test(struct slgt_info *info);
  387. static void reset_adapter(struct slgt_info *info);
  388. static void reset_port(struct slgt_info *info);
  389. static void async_mode(struct slgt_info *info);
  390. static void sync_mode(struct slgt_info *info);
  391. static void rx_stop(struct slgt_info *info);
  392. static void rx_start(struct slgt_info *info);
  393. static void reset_rbufs(struct slgt_info *info);
  394. static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
  395. static void rdma_reset(struct slgt_info *info);
  396. static int rx_get_frame(struct slgt_info *info);
  397. static int rx_get_buf(struct slgt_info *info);
  398. static void tx_start(struct slgt_info *info);
  399. static void tx_stop(struct slgt_info *info);
  400. static void tx_set_idle(struct slgt_info *info);
  401. static unsigned int free_tbuf_count(struct slgt_info *info);
  402. static void reset_tbufs(struct slgt_info *info);
  403. static void tdma_reset(struct slgt_info *info);
  404. static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
  405. static void get_signals(struct slgt_info *info);
  406. static void set_signals(struct slgt_info *info);
  407. static void enable_loopback(struct slgt_info *info);
  408. static void set_rate(struct slgt_info *info, u32 data_rate);
  409. static int bh_action(struct slgt_info *info);
  410. static void bh_handler(struct work_struct *work);
  411. static void bh_transmit(struct slgt_info *info);
  412. static void isr_serial(struct slgt_info *info);
  413. static void isr_rdma(struct slgt_info *info);
  414. static void isr_txeom(struct slgt_info *info, unsigned short status);
  415. static void isr_tdma(struct slgt_info *info);
  416. static irqreturn_t slgt_interrupt(int irq, void *dev_id);
  417. static int alloc_dma_bufs(struct slgt_info *info);
  418. static void free_dma_bufs(struct slgt_info *info);
  419. static int alloc_desc(struct slgt_info *info);
  420. static void free_desc(struct slgt_info *info);
  421. static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
  422. static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
  423. static int alloc_tmp_rbuf(struct slgt_info *info);
  424. static void free_tmp_rbuf(struct slgt_info *info);
  425. static void tx_timeout(unsigned long context);
  426. static void rx_timeout(unsigned long context);
  427. /*
  428. * ioctl handlers
  429. */
  430. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
  431. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  432. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
  433. static int get_txidle(struct slgt_info *info, int __user *idle_mode);
  434. static int set_txidle(struct slgt_info *info, int idle_mode);
  435. static int tx_enable(struct slgt_info *info, int enable);
  436. static int tx_abort(struct slgt_info *info);
  437. static int rx_enable(struct slgt_info *info, int enable);
  438. static int modem_input_wait(struct slgt_info *info,int arg);
  439. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
  440. static int tiocmget(struct tty_struct *tty, struct file *file);
  441. static int tiocmset(struct tty_struct *tty, struct file *file,
  442. unsigned int set, unsigned int clear);
  443. static void set_break(struct tty_struct *tty, int break_state);
  444. static int get_interface(struct slgt_info *info, int __user *if_mode);
  445. static int set_interface(struct slgt_info *info, int if_mode);
  446. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  447. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  448. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
  449. /*
  450. * driver functions
  451. */
  452. static void add_device(struct slgt_info *info);
  453. static void device_init(int adapter_num, struct pci_dev *pdev);
  454. static int claim_resources(struct slgt_info *info);
  455. static void release_resources(struct slgt_info *info);
  456. /*
  457. * DEBUG OUTPUT CODE
  458. */
  459. #ifndef DBGINFO
  460. #define DBGINFO(fmt)
  461. #endif
  462. #ifndef DBGERR
  463. #define DBGERR(fmt)
  464. #endif
  465. #ifndef DBGBH
  466. #define DBGBH(fmt)
  467. #endif
  468. #ifndef DBGISR
  469. #define DBGISR(fmt)
  470. #endif
  471. #ifdef DBGDATA
  472. static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
  473. {
  474. int i;
  475. int linecount;
  476. printk("%s %s data:\n",info->device_name, label);
  477. while(count) {
  478. linecount = (count > 16) ? 16 : count;
  479. for(i=0; i < linecount; i++)
  480. printk("%02X ",(unsigned char)data[i]);
  481. for(;i<17;i++)
  482. printk(" ");
  483. for(i=0;i<linecount;i++) {
  484. if (data[i]>=040 && data[i]<=0176)
  485. printk("%c",data[i]);
  486. else
  487. printk(".");
  488. }
  489. printk("\n");
  490. data += linecount;
  491. count -= linecount;
  492. }
  493. }
  494. #else
  495. #define DBGDATA(info, buf, size, label)
  496. #endif
  497. #ifdef DBGTBUF
  498. static void dump_tbufs(struct slgt_info *info)
  499. {
  500. int i;
  501. printk("tbuf_current=%d\n", info->tbuf_current);
  502. for (i=0 ; i < info->tbuf_count ; i++) {
  503. printk("%d: count=%04X status=%04X\n",
  504. i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
  505. }
  506. }
  507. #else
  508. #define DBGTBUF(info)
  509. #endif
  510. #ifdef DBGRBUF
  511. static void dump_rbufs(struct slgt_info *info)
  512. {
  513. int i;
  514. printk("rbuf_current=%d\n", info->rbuf_current);
  515. for (i=0 ; i < info->rbuf_count ; i++) {
  516. printk("%d: count=%04X status=%04X\n",
  517. i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
  518. }
  519. }
  520. #else
  521. #define DBGRBUF(info)
  522. #endif
  523. static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
  524. {
  525. #ifdef SANITY_CHECK
  526. if (!info) {
  527. printk("null struct slgt_info for (%s) in %s\n", devname, name);
  528. return 1;
  529. }
  530. if (info->magic != MGSL_MAGIC) {
  531. printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
  532. return 1;
  533. }
  534. #else
  535. if (!info)
  536. return 1;
  537. #endif
  538. return 0;
  539. }
  540. /**
  541. * line discipline callback wrappers
  542. *
  543. * The wrappers maintain line discipline references
  544. * while calling into the line discipline.
  545. *
  546. * ldisc_receive_buf - pass receive data to line discipline
  547. */
  548. static void ldisc_receive_buf(struct tty_struct *tty,
  549. const __u8 *data, char *flags, int count)
  550. {
  551. struct tty_ldisc *ld;
  552. if (!tty)
  553. return;
  554. ld = tty_ldisc_ref(tty);
  555. if (ld) {
  556. if (ld->receive_buf)
  557. ld->receive_buf(tty, data, flags, count);
  558. tty_ldisc_deref(ld);
  559. }
  560. }
  561. /* tty callbacks */
  562. static int open(struct tty_struct *tty, struct file *filp)
  563. {
  564. struct slgt_info *info;
  565. int retval, line;
  566. unsigned long flags;
  567. line = tty->index;
  568. if ((line < 0) || (line >= slgt_device_count)) {
  569. DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
  570. return -ENODEV;
  571. }
  572. info = slgt_device_list;
  573. while(info && info->line != line)
  574. info = info->next_device;
  575. if (sanity_check(info, tty->name, "open"))
  576. return -ENODEV;
  577. if (info->init_error) {
  578. DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
  579. return -ENODEV;
  580. }
  581. tty->driver_data = info;
  582. info->tty = tty;
  583. DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
  584. /* If port is closing, signal caller to try again */
  585. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  586. if (info->flags & ASYNC_CLOSING)
  587. interruptible_sleep_on(&info->close_wait);
  588. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  589. -EAGAIN : -ERESTARTSYS);
  590. goto cleanup;
  591. }
  592. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  593. spin_lock_irqsave(&info->netlock, flags);
  594. if (info->netcount) {
  595. retval = -EBUSY;
  596. spin_unlock_irqrestore(&info->netlock, flags);
  597. goto cleanup;
  598. }
  599. info->count++;
  600. spin_unlock_irqrestore(&info->netlock, flags);
  601. if (info->count == 1) {
  602. /* 1st open on this device, init hardware */
  603. retval = startup(info);
  604. if (retval < 0)
  605. goto cleanup;
  606. }
  607. retval = block_til_ready(tty, filp, info);
  608. if (retval) {
  609. DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
  610. goto cleanup;
  611. }
  612. retval = 0;
  613. cleanup:
  614. if (retval) {
  615. if (tty->count == 1)
  616. info->tty = NULL; /* tty layer will release tty struct */
  617. if(info->count)
  618. info->count--;
  619. }
  620. DBGINFO(("%s open rc=%d\n", info->device_name, retval));
  621. return retval;
  622. }
  623. static void close(struct tty_struct *tty, struct file *filp)
  624. {
  625. struct slgt_info *info = tty->driver_data;
  626. if (sanity_check(info, tty->name, "close"))
  627. return;
  628. DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
  629. if (!info->count)
  630. return;
  631. if (tty_hung_up_p(filp))
  632. goto cleanup;
  633. if ((tty->count == 1) && (info->count != 1)) {
  634. /*
  635. * tty->count is 1 and the tty structure will be freed.
  636. * info->count should be one in this case.
  637. * if it's not, correct it so that the port is shutdown.
  638. */
  639. DBGERR(("%s close: bad refcount; tty->count=1, "
  640. "info->count=%d\n", info->device_name, info->count));
  641. info->count = 1;
  642. }
  643. info->count--;
  644. /* if at least one open remaining, leave hardware active */
  645. if (info->count)
  646. goto cleanup;
  647. info->flags |= ASYNC_CLOSING;
  648. /* set tty->closing to notify line discipline to
  649. * only process XON/XOFF characters. Only the N_TTY
  650. * discipline appears to use this (ppp does not).
  651. */
  652. tty->closing = 1;
  653. /* wait for transmit data to clear all layers */
  654. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  655. DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
  656. tty_wait_until_sent(tty, info->closing_wait);
  657. }
  658. if (info->flags & ASYNC_INITIALIZED)
  659. wait_until_sent(tty, info->timeout);
  660. if (tty->driver->flush_buffer)
  661. tty->driver->flush_buffer(tty);
  662. tty_ldisc_flush(tty);
  663. shutdown(info);
  664. tty->closing = 0;
  665. info->tty = NULL;
  666. if (info->blocked_open) {
  667. if (info->close_delay) {
  668. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  669. }
  670. wake_up_interruptible(&info->open_wait);
  671. }
  672. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  673. wake_up_interruptible(&info->close_wait);
  674. cleanup:
  675. DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
  676. }
  677. static void hangup(struct tty_struct *tty)
  678. {
  679. struct slgt_info *info = tty->driver_data;
  680. if (sanity_check(info, tty->name, "hangup"))
  681. return;
  682. DBGINFO(("%s hangup\n", info->device_name));
  683. flush_buffer(tty);
  684. shutdown(info);
  685. info->count = 0;
  686. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  687. info->tty = NULL;
  688. wake_up_interruptible(&info->open_wait);
  689. }
  690. static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  691. {
  692. struct slgt_info *info = tty->driver_data;
  693. unsigned long flags;
  694. DBGINFO(("%s set_termios\n", tty->driver->name));
  695. /* just return if nothing has changed */
  696. if ((tty->termios->c_cflag == old_termios->c_cflag)
  697. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  698. == RELEVANT_IFLAG(old_termios->c_iflag)))
  699. return;
  700. change_params(info);
  701. /* Handle transition to B0 status */
  702. if (old_termios->c_cflag & CBAUD &&
  703. !(tty->termios->c_cflag & CBAUD)) {
  704. info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  705. spin_lock_irqsave(&info->lock,flags);
  706. set_signals(info);
  707. spin_unlock_irqrestore(&info->lock,flags);
  708. }
  709. /* Handle transition away from B0 status */
  710. if (!(old_termios->c_cflag & CBAUD) &&
  711. tty->termios->c_cflag & CBAUD) {
  712. info->signals |= SerialSignal_DTR;
  713. if (!(tty->termios->c_cflag & CRTSCTS) ||
  714. !test_bit(TTY_THROTTLED, &tty->flags)) {
  715. info->signals |= SerialSignal_RTS;
  716. }
  717. spin_lock_irqsave(&info->lock,flags);
  718. set_signals(info);
  719. spin_unlock_irqrestore(&info->lock,flags);
  720. }
  721. /* Handle turning off CRTSCTS */
  722. if (old_termios->c_cflag & CRTSCTS &&
  723. !(tty->termios->c_cflag & CRTSCTS)) {
  724. tty->hw_stopped = 0;
  725. tx_release(tty);
  726. }
  727. }
  728. static int write(struct tty_struct *tty,
  729. const unsigned char *buf, int count)
  730. {
  731. int ret = 0;
  732. struct slgt_info *info = tty->driver_data;
  733. unsigned long flags;
  734. if (sanity_check(info, tty->name, "write"))
  735. goto cleanup;
  736. DBGINFO(("%s write count=%d\n", info->device_name, count));
  737. if (!info->tx_buf)
  738. goto cleanup;
  739. if (count > info->max_frame_size) {
  740. ret = -EIO;
  741. goto cleanup;
  742. }
  743. if (!count)
  744. goto cleanup;
  745. if (info->params.mode == MGSL_MODE_RAW ||
  746. info->params.mode == MGSL_MODE_MONOSYNC ||
  747. info->params.mode == MGSL_MODE_BISYNC) {
  748. unsigned int bufs_needed = (count/DMABUFSIZE);
  749. unsigned int bufs_free = free_tbuf_count(info);
  750. if (count % DMABUFSIZE)
  751. ++bufs_needed;
  752. if (bufs_needed > bufs_free)
  753. goto cleanup;
  754. } else {
  755. if (info->tx_active)
  756. goto cleanup;
  757. if (info->tx_count) {
  758. /* send accumulated data from send_char() calls */
  759. /* as frame and wait before accepting more data. */
  760. tx_load(info, info->tx_buf, info->tx_count);
  761. goto start;
  762. }
  763. }
  764. ret = info->tx_count = count;
  765. tx_load(info, buf, count);
  766. goto start;
  767. start:
  768. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  769. spin_lock_irqsave(&info->lock,flags);
  770. if (!info->tx_active)
  771. tx_start(info);
  772. spin_unlock_irqrestore(&info->lock,flags);
  773. }
  774. cleanup:
  775. DBGINFO(("%s write rc=%d\n", info->device_name, ret));
  776. return ret;
  777. }
  778. static void put_char(struct tty_struct *tty, unsigned char ch)
  779. {
  780. struct slgt_info *info = tty->driver_data;
  781. unsigned long flags;
  782. if (sanity_check(info, tty->name, "put_char"))
  783. return;
  784. DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
  785. if (!info->tx_buf)
  786. return;
  787. spin_lock_irqsave(&info->lock,flags);
  788. if (!info->tx_active && (info->tx_count < info->max_frame_size))
  789. info->tx_buf[info->tx_count++] = ch;
  790. spin_unlock_irqrestore(&info->lock,flags);
  791. }
  792. static void send_xchar(struct tty_struct *tty, char ch)
  793. {
  794. struct slgt_info *info = tty->driver_data;
  795. unsigned long flags;
  796. if (sanity_check(info, tty->name, "send_xchar"))
  797. return;
  798. DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
  799. info->x_char = ch;
  800. if (ch) {
  801. spin_lock_irqsave(&info->lock,flags);
  802. if (!info->tx_enabled)
  803. tx_start(info);
  804. spin_unlock_irqrestore(&info->lock,flags);
  805. }
  806. }
  807. static void wait_until_sent(struct tty_struct *tty, int timeout)
  808. {
  809. struct slgt_info *info = tty->driver_data;
  810. unsigned long orig_jiffies, char_time;
  811. if (!info )
  812. return;
  813. if (sanity_check(info, tty->name, "wait_until_sent"))
  814. return;
  815. DBGINFO(("%s wait_until_sent entry\n", info->device_name));
  816. if (!(info->flags & ASYNC_INITIALIZED))
  817. goto exit;
  818. orig_jiffies = jiffies;
  819. /* Set check interval to 1/5 of estimated time to
  820. * send a character, and make it at least 1. The check
  821. * interval should also be less than the timeout.
  822. * Note: use tight timings here to satisfy the NIST-PCTS.
  823. */
  824. if (info->params.data_rate) {
  825. char_time = info->timeout/(32 * 5);
  826. if (!char_time)
  827. char_time++;
  828. } else
  829. char_time = 1;
  830. if (timeout)
  831. char_time = min_t(unsigned long, char_time, timeout);
  832. while (info->tx_active) {
  833. msleep_interruptible(jiffies_to_msecs(char_time));
  834. if (signal_pending(current))
  835. break;
  836. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  837. break;
  838. }
  839. exit:
  840. DBGINFO(("%s wait_until_sent exit\n", info->device_name));
  841. }
  842. static int write_room(struct tty_struct *tty)
  843. {
  844. struct slgt_info *info = tty->driver_data;
  845. int ret;
  846. if (sanity_check(info, tty->name, "write_room"))
  847. return 0;
  848. ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
  849. DBGINFO(("%s write_room=%d\n", info->device_name, ret));
  850. return ret;
  851. }
  852. static void flush_chars(struct tty_struct *tty)
  853. {
  854. struct slgt_info *info = tty->driver_data;
  855. unsigned long flags;
  856. if (sanity_check(info, tty->name, "flush_chars"))
  857. return;
  858. DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
  859. if (info->tx_count <= 0 || tty->stopped ||
  860. tty->hw_stopped || !info->tx_buf)
  861. return;
  862. DBGINFO(("%s flush_chars start transmit\n", info->device_name));
  863. spin_lock_irqsave(&info->lock,flags);
  864. if (!info->tx_active && info->tx_count) {
  865. tx_load(info, info->tx_buf,info->tx_count);
  866. tx_start(info);
  867. }
  868. spin_unlock_irqrestore(&info->lock,flags);
  869. }
  870. static void flush_buffer(struct tty_struct *tty)
  871. {
  872. struct slgt_info *info = tty->driver_data;
  873. unsigned long flags;
  874. if (sanity_check(info, tty->name, "flush_buffer"))
  875. return;
  876. DBGINFO(("%s flush_buffer\n", info->device_name));
  877. spin_lock_irqsave(&info->lock,flags);
  878. if (!info->tx_active)
  879. info->tx_count = 0;
  880. spin_unlock_irqrestore(&info->lock,flags);
  881. tty_wakeup(tty);
  882. }
  883. /*
  884. * throttle (stop) transmitter
  885. */
  886. static void tx_hold(struct tty_struct *tty)
  887. {
  888. struct slgt_info *info = tty->driver_data;
  889. unsigned long flags;
  890. if (sanity_check(info, tty->name, "tx_hold"))
  891. return;
  892. DBGINFO(("%s tx_hold\n", info->device_name));
  893. spin_lock_irqsave(&info->lock,flags);
  894. if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
  895. tx_stop(info);
  896. spin_unlock_irqrestore(&info->lock,flags);
  897. }
  898. /*
  899. * release (start) transmitter
  900. */
  901. static void tx_release(struct tty_struct *tty)
  902. {
  903. struct slgt_info *info = tty->driver_data;
  904. unsigned long flags;
  905. if (sanity_check(info, tty->name, "tx_release"))
  906. return;
  907. DBGINFO(("%s tx_release\n", info->device_name));
  908. spin_lock_irqsave(&info->lock,flags);
  909. if (!info->tx_active && info->tx_count) {
  910. tx_load(info, info->tx_buf, info->tx_count);
  911. tx_start(info);
  912. }
  913. spin_unlock_irqrestore(&info->lock,flags);
  914. }
  915. /*
  916. * Service an IOCTL request
  917. *
  918. * Arguments
  919. *
  920. * tty pointer to tty instance data
  921. * file pointer to associated file object for device
  922. * cmd IOCTL command code
  923. * arg command argument/context
  924. *
  925. * Return 0 if success, otherwise error code
  926. */
  927. static int ioctl(struct tty_struct *tty, struct file *file,
  928. unsigned int cmd, unsigned long arg)
  929. {
  930. struct slgt_info *info = tty->driver_data;
  931. struct mgsl_icount cnow; /* kernel counter temps */
  932. struct serial_icounter_struct __user *p_cuser; /* user space */
  933. unsigned long flags;
  934. void __user *argp = (void __user *)arg;
  935. if (sanity_check(info, tty->name, "ioctl"))
  936. return -ENODEV;
  937. DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
  938. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  939. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  940. if (tty->flags & (1 << TTY_IO_ERROR))
  941. return -EIO;
  942. }
  943. switch (cmd) {
  944. case MGSL_IOCGPARAMS:
  945. return get_params(info, argp);
  946. case MGSL_IOCSPARAMS:
  947. return set_params(info, argp);
  948. case MGSL_IOCGTXIDLE:
  949. return get_txidle(info, argp);
  950. case MGSL_IOCSTXIDLE:
  951. return set_txidle(info, (int)arg);
  952. case MGSL_IOCTXENABLE:
  953. return tx_enable(info, (int)arg);
  954. case MGSL_IOCRXENABLE:
  955. return rx_enable(info, (int)arg);
  956. case MGSL_IOCTXABORT:
  957. return tx_abort(info);
  958. case MGSL_IOCGSTATS:
  959. return get_stats(info, argp);
  960. case MGSL_IOCWAITEVENT:
  961. return wait_mgsl_event(info, argp);
  962. case TIOCMIWAIT:
  963. return modem_input_wait(info,(int)arg);
  964. case MGSL_IOCGIF:
  965. return get_interface(info, argp);
  966. case MGSL_IOCSIF:
  967. return set_interface(info,(int)arg);
  968. case MGSL_IOCSGPIO:
  969. return set_gpio(info, argp);
  970. case MGSL_IOCGGPIO:
  971. return get_gpio(info, argp);
  972. case MGSL_IOCWAITGPIO:
  973. return wait_gpio(info, argp);
  974. case TIOCGICOUNT:
  975. spin_lock_irqsave(&info->lock,flags);
  976. cnow = info->icount;
  977. spin_unlock_irqrestore(&info->lock,flags);
  978. p_cuser = argp;
  979. if (put_user(cnow.cts, &p_cuser->cts) ||
  980. put_user(cnow.dsr, &p_cuser->dsr) ||
  981. put_user(cnow.rng, &p_cuser->rng) ||
  982. put_user(cnow.dcd, &p_cuser->dcd) ||
  983. put_user(cnow.rx, &p_cuser->rx) ||
  984. put_user(cnow.tx, &p_cuser->tx) ||
  985. put_user(cnow.frame, &p_cuser->frame) ||
  986. put_user(cnow.overrun, &p_cuser->overrun) ||
  987. put_user(cnow.parity, &p_cuser->parity) ||
  988. put_user(cnow.brk, &p_cuser->brk) ||
  989. put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
  990. return -EFAULT;
  991. return 0;
  992. default:
  993. return -ENOIOCTLCMD;
  994. }
  995. return 0;
  996. }
  997. /*
  998. * proc fs support
  999. */
  1000. static inline int line_info(char *buf, struct slgt_info *info)
  1001. {
  1002. char stat_buf[30];
  1003. int ret;
  1004. unsigned long flags;
  1005. ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
  1006. info->device_name, info->phys_reg_addr,
  1007. info->irq_level, info->max_frame_size);
  1008. /* output current serial signal states */
  1009. spin_lock_irqsave(&info->lock,flags);
  1010. get_signals(info);
  1011. spin_unlock_irqrestore(&info->lock,flags);
  1012. stat_buf[0] = 0;
  1013. stat_buf[1] = 0;
  1014. if (info->signals & SerialSignal_RTS)
  1015. strcat(stat_buf, "|RTS");
  1016. if (info->signals & SerialSignal_CTS)
  1017. strcat(stat_buf, "|CTS");
  1018. if (info->signals & SerialSignal_DTR)
  1019. strcat(stat_buf, "|DTR");
  1020. if (info->signals & SerialSignal_DSR)
  1021. strcat(stat_buf, "|DSR");
  1022. if (info->signals & SerialSignal_DCD)
  1023. strcat(stat_buf, "|CD");
  1024. if (info->signals & SerialSignal_RI)
  1025. strcat(stat_buf, "|RI");
  1026. if (info->params.mode != MGSL_MODE_ASYNC) {
  1027. ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
  1028. info->icount.txok, info->icount.rxok);
  1029. if (info->icount.txunder)
  1030. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  1031. if (info->icount.txabort)
  1032. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  1033. if (info->icount.rxshort)
  1034. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  1035. if (info->icount.rxlong)
  1036. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  1037. if (info->icount.rxover)
  1038. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  1039. if (info->icount.rxcrc)
  1040. ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
  1041. } else {
  1042. ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
  1043. info->icount.tx, info->icount.rx);
  1044. if (info->icount.frame)
  1045. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  1046. if (info->icount.parity)
  1047. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  1048. if (info->icount.brk)
  1049. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  1050. if (info->icount.overrun)
  1051. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  1052. }
  1053. /* Append serial signal status to end */
  1054. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  1055. ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  1056. info->tx_active,info->bh_requested,info->bh_running,
  1057. info->pending_bh);
  1058. return ret;
  1059. }
  1060. /* Called to print information about devices
  1061. */
  1062. static int read_proc(char *page, char **start, off_t off, int count,
  1063. int *eof, void *data)
  1064. {
  1065. int len = 0, l;
  1066. off_t begin = 0;
  1067. struct slgt_info *info;
  1068. len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
  1069. info = slgt_device_list;
  1070. while( info ) {
  1071. l = line_info(page + len, info);
  1072. len += l;
  1073. if (len+begin > off+count)
  1074. goto done;
  1075. if (len+begin < off) {
  1076. begin += len;
  1077. len = 0;
  1078. }
  1079. info = info->next_device;
  1080. }
  1081. *eof = 1;
  1082. done:
  1083. if (off >= len+begin)
  1084. return 0;
  1085. *start = page + (off-begin);
  1086. return ((count < begin+len-off) ? count : begin+len-off);
  1087. }
  1088. /*
  1089. * return count of bytes in transmit buffer
  1090. */
  1091. static int chars_in_buffer(struct tty_struct *tty)
  1092. {
  1093. struct slgt_info *info = tty->driver_data;
  1094. if (sanity_check(info, tty->name, "chars_in_buffer"))
  1095. return 0;
  1096. DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
  1097. return info->tx_count;
  1098. }
  1099. /*
  1100. * signal remote device to throttle send data (our receive data)
  1101. */
  1102. static void throttle(struct tty_struct * tty)
  1103. {
  1104. struct slgt_info *info = tty->driver_data;
  1105. unsigned long flags;
  1106. if (sanity_check(info, tty->name, "throttle"))
  1107. return;
  1108. DBGINFO(("%s throttle\n", info->device_name));
  1109. if (I_IXOFF(tty))
  1110. send_xchar(tty, STOP_CHAR(tty));
  1111. if (tty->termios->c_cflag & CRTSCTS) {
  1112. spin_lock_irqsave(&info->lock,flags);
  1113. info->signals &= ~SerialSignal_RTS;
  1114. set_signals(info);
  1115. spin_unlock_irqrestore(&info->lock,flags);
  1116. }
  1117. }
  1118. /*
  1119. * signal remote device to stop throttling send data (our receive data)
  1120. */
  1121. static void unthrottle(struct tty_struct * tty)
  1122. {
  1123. struct slgt_info *info = tty->driver_data;
  1124. unsigned long flags;
  1125. if (sanity_check(info, tty->name, "unthrottle"))
  1126. return;
  1127. DBGINFO(("%s unthrottle\n", info->device_name));
  1128. if (I_IXOFF(tty)) {
  1129. if (info->x_char)
  1130. info->x_char = 0;
  1131. else
  1132. send_xchar(tty, START_CHAR(tty));
  1133. }
  1134. if (tty->termios->c_cflag & CRTSCTS) {
  1135. spin_lock_irqsave(&info->lock,flags);
  1136. info->signals |= SerialSignal_RTS;
  1137. set_signals(info);
  1138. spin_unlock_irqrestore(&info->lock,flags);
  1139. }
  1140. }
  1141. /*
  1142. * set or clear transmit break condition
  1143. * break_state -1=set break condition, 0=clear
  1144. */
  1145. static void set_break(struct tty_struct *tty, int break_state)
  1146. {
  1147. struct slgt_info *info = tty->driver_data;
  1148. unsigned short value;
  1149. unsigned long flags;
  1150. if (sanity_check(info, tty->name, "set_break"))
  1151. return;
  1152. DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
  1153. spin_lock_irqsave(&info->lock,flags);
  1154. value = rd_reg16(info, TCR);
  1155. if (break_state == -1)
  1156. value |= BIT6;
  1157. else
  1158. value &= ~BIT6;
  1159. wr_reg16(info, TCR, value);
  1160. spin_unlock_irqrestore(&info->lock,flags);
  1161. }
  1162. #if SYNCLINK_GENERIC_HDLC
  1163. /**
  1164. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  1165. * set encoding and frame check sequence (FCS) options
  1166. *
  1167. * dev pointer to network device structure
  1168. * encoding serial encoding setting
  1169. * parity FCS setting
  1170. *
  1171. * returns 0 if success, otherwise error code
  1172. */
  1173. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  1174. unsigned short parity)
  1175. {
  1176. struct slgt_info *info = dev_to_port(dev);
  1177. unsigned char new_encoding;
  1178. unsigned short new_crctype;
  1179. /* return error if TTY interface open */
  1180. if (info->count)
  1181. return -EBUSY;
  1182. DBGINFO(("%s hdlcdev_attach\n", info->device_name));
  1183. switch (encoding)
  1184. {
  1185. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  1186. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  1187. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  1188. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  1189. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  1190. default: return -EINVAL;
  1191. }
  1192. switch (parity)
  1193. {
  1194. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  1195. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  1196. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  1197. default: return -EINVAL;
  1198. }
  1199. info->params.encoding = new_encoding;
  1200. info->params.crc_type = new_crctype;
  1201. /* if network interface up, reprogram hardware */
  1202. if (info->netcount)
  1203. program_hw(info);
  1204. return 0;
  1205. }
  1206. /**
  1207. * called by generic HDLC layer to send frame
  1208. *
  1209. * skb socket buffer containing HDLC frame
  1210. * dev pointer to network device structure
  1211. *
  1212. * returns 0 if success, otherwise error code
  1213. */
  1214. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  1215. {
  1216. struct slgt_info *info = dev_to_port(dev);
  1217. struct net_device_stats *stats = hdlc_stats(dev);
  1218. unsigned long flags;
  1219. DBGINFO(("%s hdlc_xmit\n", dev->name));
  1220. /* stop sending until this frame completes */
  1221. netif_stop_queue(dev);
  1222. /* copy data to device buffers */
  1223. info->tx_count = skb->len;
  1224. tx_load(info, skb->data, skb->len);
  1225. /* update network statistics */
  1226. stats->tx_packets++;
  1227. stats->tx_bytes += skb->len;
  1228. /* done with socket buffer, so free it */
  1229. dev_kfree_skb(skb);
  1230. /* save start time for transmit timeout detection */
  1231. dev->trans_start = jiffies;
  1232. /* start hardware transmitter if necessary */
  1233. spin_lock_irqsave(&info->lock,flags);
  1234. if (!info->tx_active)
  1235. tx_start(info);
  1236. spin_unlock_irqrestore(&info->lock,flags);
  1237. return 0;
  1238. }
  1239. /**
  1240. * called by network layer when interface enabled
  1241. * claim resources and initialize hardware
  1242. *
  1243. * dev pointer to network device structure
  1244. *
  1245. * returns 0 if success, otherwise error code
  1246. */
  1247. static int hdlcdev_open(struct net_device *dev)
  1248. {
  1249. struct slgt_info *info = dev_to_port(dev);
  1250. int rc;
  1251. unsigned long flags;
  1252. DBGINFO(("%s hdlcdev_open\n", dev->name));
  1253. /* generic HDLC layer open processing */
  1254. if ((rc = hdlc_open(dev)))
  1255. return rc;
  1256. /* arbitrate between network and tty opens */
  1257. spin_lock_irqsave(&info->netlock, flags);
  1258. if (info->count != 0 || info->netcount != 0) {
  1259. DBGINFO(("%s hdlc_open busy\n", dev->name));
  1260. spin_unlock_irqrestore(&info->netlock, flags);
  1261. return -EBUSY;
  1262. }
  1263. info->netcount=1;
  1264. spin_unlock_irqrestore(&info->netlock, flags);
  1265. /* claim resources and init adapter */
  1266. if ((rc = startup(info)) != 0) {
  1267. spin_lock_irqsave(&info->netlock, flags);
  1268. info->netcount=0;
  1269. spin_unlock_irqrestore(&info->netlock, flags);
  1270. return rc;
  1271. }
  1272. /* assert DTR and RTS, apply hardware settings */
  1273. info->signals |= SerialSignal_RTS + SerialSignal_DTR;
  1274. program_hw(info);
  1275. /* enable network layer transmit */
  1276. dev->trans_start = jiffies;
  1277. netif_start_queue(dev);
  1278. /* inform generic HDLC layer of current DCD status */
  1279. spin_lock_irqsave(&info->lock, flags);
  1280. get_signals(info);
  1281. spin_unlock_irqrestore(&info->lock, flags);
  1282. if (info->signals & SerialSignal_DCD)
  1283. netif_carrier_on(dev);
  1284. else
  1285. netif_carrier_off(dev);
  1286. return 0;
  1287. }
  1288. /**
  1289. * called by network layer when interface is disabled
  1290. * shutdown hardware and release resources
  1291. *
  1292. * dev pointer to network device structure
  1293. *
  1294. * returns 0 if success, otherwise error code
  1295. */
  1296. static int hdlcdev_close(struct net_device *dev)
  1297. {
  1298. struct slgt_info *info = dev_to_port(dev);
  1299. unsigned long flags;
  1300. DBGINFO(("%s hdlcdev_close\n", dev->name));
  1301. netif_stop_queue(dev);
  1302. /* shutdown adapter and release resources */
  1303. shutdown(info);
  1304. hdlc_close(dev);
  1305. spin_lock_irqsave(&info->netlock, flags);
  1306. info->netcount=0;
  1307. spin_unlock_irqrestore(&info->netlock, flags);
  1308. return 0;
  1309. }
  1310. /**
  1311. * called by network layer to process IOCTL call to network device
  1312. *
  1313. * dev pointer to network device structure
  1314. * ifr pointer to network interface request structure
  1315. * cmd IOCTL command code
  1316. *
  1317. * returns 0 if success, otherwise error code
  1318. */
  1319. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1320. {
  1321. const size_t size = sizeof(sync_serial_settings);
  1322. sync_serial_settings new_line;
  1323. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  1324. struct slgt_info *info = dev_to_port(dev);
  1325. unsigned int flags;
  1326. DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
  1327. /* return error if TTY interface open */
  1328. if (info->count)
  1329. return -EBUSY;
  1330. if (cmd != SIOCWANDEV)
  1331. return hdlc_ioctl(dev, ifr, cmd);
  1332. switch(ifr->ifr_settings.type) {
  1333. case IF_GET_IFACE: /* return current sync_serial_settings */
  1334. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  1335. if (ifr->ifr_settings.size < size) {
  1336. ifr->ifr_settings.size = size; /* data size wanted */
  1337. return -ENOBUFS;
  1338. }
  1339. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1340. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1341. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1342. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1343. switch (flags){
  1344. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  1345. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  1346. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  1347. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  1348. default: new_line.clock_type = CLOCK_DEFAULT;
  1349. }
  1350. new_line.clock_rate = info->params.clock_speed;
  1351. new_line.loopback = info->params.loopback ? 1:0;
  1352. if (copy_to_user(line, &new_line, size))
  1353. return -EFAULT;
  1354. return 0;
  1355. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  1356. if(!capable(CAP_NET_ADMIN))
  1357. return -EPERM;
  1358. if (copy_from_user(&new_line, line, size))
  1359. return -EFAULT;
  1360. switch (new_line.clock_type)
  1361. {
  1362. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  1363. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  1364. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  1365. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  1366. case CLOCK_DEFAULT: flags = info->params.flags &
  1367. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1368. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1369. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1370. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  1371. default: return -EINVAL;
  1372. }
  1373. if (new_line.loopback != 0 && new_line.loopback != 1)
  1374. return -EINVAL;
  1375. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  1376. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  1377. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  1378. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  1379. info->params.flags |= flags;
  1380. info->params.loopback = new_line.loopback;
  1381. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  1382. info->params.clock_speed = new_line.clock_rate;
  1383. else
  1384. info->params.clock_speed = 0;
  1385. /* if network interface up, reprogram hardware */
  1386. if (info->netcount)
  1387. program_hw(info);
  1388. return 0;
  1389. default:
  1390. return hdlc_ioctl(dev, ifr, cmd);
  1391. }
  1392. }
  1393. /**
  1394. * called by network layer when transmit timeout is detected
  1395. *
  1396. * dev pointer to network device structure
  1397. */
  1398. static void hdlcdev_tx_timeout(struct net_device *dev)
  1399. {
  1400. struct slgt_info *info = dev_to_port(dev);
  1401. struct net_device_stats *stats = hdlc_stats(dev);
  1402. unsigned long flags;
  1403. DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
  1404. stats->tx_errors++;
  1405. stats->tx_aborted_errors++;
  1406. spin_lock_irqsave(&info->lock,flags);
  1407. tx_stop(info);
  1408. spin_unlock_irqrestore(&info->lock,flags);
  1409. netif_wake_queue(dev);
  1410. }
  1411. /**
  1412. * called by device driver when transmit completes
  1413. * reenable network layer transmit if stopped
  1414. *
  1415. * info pointer to device instance information
  1416. */
  1417. static void hdlcdev_tx_done(struct slgt_info *info)
  1418. {
  1419. if (netif_queue_stopped(info->netdev))
  1420. netif_wake_queue(info->netdev);
  1421. }
  1422. /**
  1423. * called by device driver when frame received
  1424. * pass frame to network layer
  1425. *
  1426. * info pointer to device instance information
  1427. * buf pointer to buffer contianing frame data
  1428. * size count of data bytes in buf
  1429. */
  1430. static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
  1431. {
  1432. struct sk_buff *skb = dev_alloc_skb(size);
  1433. struct net_device *dev = info->netdev;
  1434. struct net_device_stats *stats = hdlc_stats(dev);
  1435. DBGINFO(("%s hdlcdev_rx\n", dev->name));
  1436. if (skb == NULL) {
  1437. DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
  1438. stats->rx_dropped++;
  1439. return;
  1440. }
  1441. memcpy(skb_put(skb, size),buf,size);
  1442. skb->protocol = hdlc_type_trans(skb, info->netdev);
  1443. stats->rx_packets++;
  1444. stats->rx_bytes += size;
  1445. netif_rx(skb);
  1446. info->netdev->last_rx = jiffies;
  1447. }
  1448. /**
  1449. * called by device driver when adding device instance
  1450. * do generic HDLC initialization
  1451. *
  1452. * info pointer to device instance information
  1453. *
  1454. * returns 0 if success, otherwise error code
  1455. */
  1456. static int hdlcdev_init(struct slgt_info *info)
  1457. {
  1458. int rc;
  1459. struct net_device *dev;
  1460. hdlc_device *hdlc;
  1461. /* allocate and initialize network and HDLC layer objects */
  1462. if (!(dev = alloc_hdlcdev(info))) {
  1463. printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
  1464. return -ENOMEM;
  1465. }
  1466. /* for network layer reporting purposes only */
  1467. dev->mem_start = info->phys_reg_addr;
  1468. dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
  1469. dev->irq = info->irq_level;
  1470. /* network layer callbacks and settings */
  1471. dev->do_ioctl = hdlcdev_ioctl;
  1472. dev->open = hdlcdev_open;
  1473. dev->stop = hdlcdev_close;
  1474. dev->tx_timeout = hdlcdev_tx_timeout;
  1475. dev->watchdog_timeo = 10*HZ;
  1476. dev->tx_queue_len = 50;
  1477. /* generic HDLC layer callbacks and settings */
  1478. hdlc = dev_to_hdlc(dev);
  1479. hdlc->attach = hdlcdev_attach;
  1480. hdlc->xmit = hdlcdev_xmit;
  1481. /* register objects with HDLC layer */
  1482. if ((rc = register_hdlc_device(dev))) {
  1483. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  1484. free_netdev(dev);
  1485. return rc;
  1486. }
  1487. info->netdev = dev;
  1488. return 0;
  1489. }
  1490. /**
  1491. * called by device driver when removing device instance
  1492. * do generic HDLC cleanup
  1493. *
  1494. * info pointer to device instance information
  1495. */
  1496. static void hdlcdev_exit(struct slgt_info *info)
  1497. {
  1498. unregister_hdlc_device(info->netdev);
  1499. free_netdev(info->netdev);
  1500. info->netdev = NULL;
  1501. }
  1502. #endif /* ifdef CONFIG_HDLC */
  1503. /*
  1504. * get async data from rx DMA buffers
  1505. */
  1506. static void rx_async(struct slgt_info *info)
  1507. {
  1508. struct tty_struct *tty = info->tty;
  1509. struct mgsl_icount *icount = &info->icount;
  1510. unsigned int start, end;
  1511. unsigned char *p;
  1512. unsigned char status;
  1513. struct slgt_desc *bufs = info->rbufs;
  1514. int i, count;
  1515. int chars = 0;
  1516. int stat;
  1517. unsigned char ch;
  1518. start = end = info->rbuf_current;
  1519. while(desc_complete(bufs[end])) {
  1520. count = desc_count(bufs[end]) - info->rbuf_index;
  1521. p = bufs[end].buf + info->rbuf_index;
  1522. DBGISR(("%s rx_async count=%d\n", info->device_name, count));
  1523. DBGDATA(info, p, count, "rx");
  1524. for(i=0 ; i < count; i+=2, p+=2) {
  1525. ch = *p;
  1526. icount->rx++;
  1527. stat = 0;
  1528. if ((status = *(p+1) & (BIT1 + BIT0))) {
  1529. if (status & BIT1)
  1530. icount->parity++;
  1531. else if (status & BIT0)
  1532. icount->frame++;
  1533. /* discard char if tty control flags say so */
  1534. if (status & info->ignore_status_mask)
  1535. continue;
  1536. if (status & BIT1)
  1537. stat = TTY_PARITY;
  1538. else if (status & BIT0)
  1539. stat = TTY_FRAME;
  1540. }
  1541. if (tty) {
  1542. tty_insert_flip_char(tty, ch, stat);
  1543. chars++;
  1544. }
  1545. }
  1546. if (i < count) {
  1547. /* receive buffer not completed */
  1548. info->rbuf_index += i;
  1549. mod_timer(&info->rx_timer, jiffies + 1);
  1550. break;
  1551. }
  1552. info->rbuf_index = 0;
  1553. free_rbufs(info, end, end);
  1554. if (++end == info->rbuf_count)
  1555. end = 0;
  1556. /* if entire list searched then no frame available */
  1557. if (end == start)
  1558. break;
  1559. }
  1560. if (tty && chars)
  1561. tty_flip_buffer_push(tty);
  1562. }
  1563. /*
  1564. * return next bottom half action to perform
  1565. */
  1566. static int bh_action(struct slgt_info *info)
  1567. {
  1568. unsigned long flags;
  1569. int rc;
  1570. spin_lock_irqsave(&info->lock,flags);
  1571. if (info->pending_bh & BH_RECEIVE) {
  1572. info->pending_bh &= ~BH_RECEIVE;
  1573. rc = BH_RECEIVE;
  1574. } else if (info->pending_bh & BH_TRANSMIT) {
  1575. info->pending_bh &= ~BH_TRANSMIT;
  1576. rc = BH_TRANSMIT;
  1577. } else if (info->pending_bh & BH_STATUS) {
  1578. info->pending_bh &= ~BH_STATUS;
  1579. rc = BH_STATUS;
  1580. } else {
  1581. /* Mark BH routine as complete */
  1582. info->bh_running = 0;
  1583. info->bh_requested = 0;
  1584. rc = 0;
  1585. }
  1586. spin_unlock_irqrestore(&info->lock,flags);
  1587. return rc;
  1588. }
  1589. /*
  1590. * perform bottom half processing
  1591. */
  1592. static void bh_handler(struct work_struct *work)
  1593. {
  1594. struct slgt_info *info = container_of(work, struct slgt_info, task);
  1595. int action;
  1596. if (!info)
  1597. return;
  1598. info->bh_running = 1;
  1599. while((action = bh_action(info))) {
  1600. switch (action) {
  1601. case BH_RECEIVE:
  1602. DBGBH(("%s bh receive\n", info->device_name));
  1603. switch(info->params.mode) {
  1604. case MGSL_MODE_ASYNC:
  1605. rx_async(info);
  1606. break;
  1607. case MGSL_MODE_HDLC:
  1608. while(rx_get_frame(info));
  1609. break;
  1610. case MGSL_MODE_RAW:
  1611. case MGSL_MODE_MONOSYNC:
  1612. case MGSL_MODE_BISYNC:
  1613. while(rx_get_buf(info));
  1614. break;
  1615. }
  1616. /* restart receiver if rx DMA buffers exhausted */
  1617. if (info->rx_restart)
  1618. rx_start(info);
  1619. break;
  1620. case BH_TRANSMIT:
  1621. bh_transmit(info);
  1622. break;
  1623. case BH_STATUS:
  1624. DBGBH(("%s bh status\n", info->device_name));
  1625. info->ri_chkcount = 0;
  1626. info->dsr_chkcount = 0;
  1627. info->dcd_chkcount = 0;
  1628. info->cts_chkcount = 0;
  1629. break;
  1630. default:
  1631. DBGBH(("%s unknown action\n", info->device_name));
  1632. break;
  1633. }
  1634. }
  1635. DBGBH(("%s bh_handler exit\n", info->device_name));
  1636. }
  1637. static void bh_transmit(struct slgt_info *info)
  1638. {
  1639. struct tty_struct *tty = info->tty;
  1640. DBGBH(("%s bh_transmit\n", info->device_name));
  1641. if (tty)
  1642. tty_wakeup(tty);
  1643. }
  1644. static void dsr_change(struct slgt_info *info)
  1645. {
  1646. get_signals(info);
  1647. DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
  1648. if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1649. slgt_irq_off(info, IRQ_DSR);
  1650. return;
  1651. }
  1652. info->icount.dsr++;
  1653. if (info->signals & SerialSignal_DSR)
  1654. info->input_signal_events.dsr_up++;
  1655. else
  1656. info->input_signal_events.dsr_down++;
  1657. wake_up_interruptible(&info->status_event_wait_q);
  1658. wake_up_interruptible(&info->event_wait_q);
  1659. info->pending_bh |= BH_STATUS;
  1660. }
  1661. static void cts_change(struct slgt_info *info)
  1662. {
  1663. get_signals(info);
  1664. DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
  1665. if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1666. slgt_irq_off(info, IRQ_CTS);
  1667. return;
  1668. }
  1669. info->icount.cts++;
  1670. if (info->signals & SerialSignal_CTS)
  1671. info->input_signal_events.cts_up++;
  1672. else
  1673. info->input_signal_events.cts_down++;
  1674. wake_up_interruptible(&info->status_event_wait_q);
  1675. wake_up_interruptible(&info->event_wait_q);
  1676. info->pending_bh |= BH_STATUS;
  1677. if (info->flags & ASYNC_CTS_FLOW) {
  1678. if (info->tty) {
  1679. if (info->tty->hw_stopped) {
  1680. if (info->signals & SerialSignal_CTS) {
  1681. info->tty->hw_stopped = 0;
  1682. info->pending_bh |= BH_TRANSMIT;
  1683. return;
  1684. }
  1685. } else {
  1686. if (!(info->signals & SerialSignal_CTS))
  1687. info->tty->hw_stopped = 1;
  1688. }
  1689. }
  1690. }
  1691. }
  1692. static void dcd_change(struct slgt_info *info)
  1693. {
  1694. get_signals(info);
  1695. DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
  1696. if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1697. slgt_irq_off(info, IRQ_DCD);
  1698. return;
  1699. }
  1700. info->icount.dcd++;
  1701. if (info->signals & SerialSignal_DCD) {
  1702. info->input_signal_events.dcd_up++;
  1703. } else {
  1704. info->input_signal_events.dcd_down++;
  1705. }
  1706. #if SYNCLINK_GENERIC_HDLC
  1707. if (info->netcount) {
  1708. if (info->signals & SerialSignal_DCD)
  1709. netif_carrier_on(info->netdev);
  1710. else
  1711. netif_carrier_off(info->netdev);
  1712. }
  1713. #endif
  1714. wake_up_interruptible(&info->status_event_wait_q);
  1715. wake_up_interruptible(&info->event_wait_q);
  1716. info->pending_bh |= BH_STATUS;
  1717. if (info->flags & ASYNC_CHECK_CD) {
  1718. if (info->signals & SerialSignal_DCD)
  1719. wake_up_interruptible(&info->open_wait);
  1720. else {
  1721. if (info->tty)
  1722. tty_hangup(info->tty);
  1723. }
  1724. }
  1725. }
  1726. static void ri_change(struct slgt_info *info)
  1727. {
  1728. get_signals(info);
  1729. DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
  1730. if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
  1731. slgt_irq_off(info, IRQ_RI);
  1732. return;
  1733. }
  1734. info->icount.dcd++;
  1735. if (info->signals & SerialSignal_RI) {
  1736. info->input_signal_events.ri_up++;
  1737. } else {
  1738. info->input_signal_events.ri_down++;
  1739. }
  1740. wake_up_interruptible(&info->status_event_wait_q);
  1741. wake_up_interruptible(&info->event_wait_q);
  1742. info->pending_bh |= BH_STATUS;
  1743. }
  1744. static void isr_serial(struct slgt_info *info)
  1745. {
  1746. unsigned short status = rd_reg16(info, SSR);
  1747. DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
  1748. wr_reg16(info, SSR, status); /* clear pending */
  1749. info->irq_occurred = 1;
  1750. if (info->params.mode == MGSL_MODE_ASYNC) {
  1751. if (status & IRQ_TXIDLE) {
  1752. if (info->tx_count)
  1753. isr_txeom(info, status);
  1754. }
  1755. if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
  1756. info->icount.brk++;
  1757. /* process break detection if tty control allows */
  1758. if (info->tty) {
  1759. if (!(status & info->ignore_status_mask)) {
  1760. if (info->read_status_mask & MASK_BREAK) {
  1761. tty_insert_flip_char(info->tty, 0, TTY_BREAK);
  1762. if (info->flags & ASYNC_SAK)
  1763. do_SAK(info->tty);
  1764. }
  1765. }
  1766. }
  1767. }
  1768. } else {
  1769. if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
  1770. isr_txeom(info, status);
  1771. if (status & IRQ_RXIDLE) {
  1772. if (status & RXIDLE)
  1773. info->icount.rxidle++;
  1774. else
  1775. info->icount.exithunt++;
  1776. wake_up_interruptible(&info->event_wait_q);
  1777. }
  1778. if (status & IRQ_RXOVER)
  1779. rx_start(info);
  1780. }
  1781. if (status & IRQ_DSR)
  1782. dsr_change(info);
  1783. if (status & IRQ_CTS)
  1784. cts_change(info);
  1785. if (status & IRQ_DCD)
  1786. dcd_change(info);
  1787. if (status & IRQ_RI)
  1788. ri_change(info);
  1789. }
  1790. static void isr_rdma(struct slgt_info *info)
  1791. {
  1792. unsigned int status = rd_reg32(info, RDCSR);
  1793. DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
  1794. /* RDCSR (rx DMA control/status)
  1795. *
  1796. * 31..07 reserved
  1797. * 06 save status byte to DMA buffer
  1798. * 05 error
  1799. * 04 eol (end of list)
  1800. * 03 eob (end of buffer)
  1801. * 02 IRQ enable
  1802. * 01 reset
  1803. * 00 enable
  1804. */
  1805. wr_reg32(info, RDCSR, status); /* clear pending */
  1806. if (status & (BIT5 + BIT4)) {
  1807. DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
  1808. info->rx_restart = 1;
  1809. }
  1810. info->pending_bh |= BH_RECEIVE;
  1811. }
  1812. static void isr_tdma(struct slgt_info *info)
  1813. {
  1814. unsigned int status = rd_reg32(info, TDCSR);
  1815. DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
  1816. /* TDCSR (tx DMA control/status)
  1817. *
  1818. * 31..06 reserved
  1819. * 05 error
  1820. * 04 eol (end of list)
  1821. * 03 eob (end of buffer)
  1822. * 02 IRQ enable
  1823. * 01 reset
  1824. * 00 enable
  1825. */
  1826. wr_reg32(info, TDCSR, status); /* clear pending */
  1827. if (status & (BIT5 + BIT4 + BIT3)) {
  1828. // another transmit buffer has completed
  1829. // run bottom half to get more send data from user
  1830. info->pending_bh |= BH_TRANSMIT;
  1831. }
  1832. }
  1833. static void isr_txeom(struct slgt_info *info, unsigned short status)
  1834. {
  1835. DBGISR(("%s txeom status=%04x\n", info->device_name, status));
  1836. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  1837. tdma_reset(info);
  1838. reset_tbufs(info);
  1839. if (status & IRQ_TXUNDER) {
  1840. unsigned short val = rd_reg16(info, TCR);
  1841. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  1842. wr_reg16(info, TCR, val); /* clear reset bit */
  1843. }
  1844. if (info->tx_active) {
  1845. if (info->params.mode != MGSL_MODE_ASYNC) {
  1846. if (status & IRQ_TXUNDER)
  1847. info->icount.txunder++;
  1848. else if (status & IRQ_TXIDLE)
  1849. info->icount.txok++;
  1850. }
  1851. info->tx_active = 0;
  1852. info->tx_count = 0;
  1853. del_timer(&info->tx_timer);
  1854. if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
  1855. info->signals &= ~SerialSignal_RTS;
  1856. info->drop_rts_on_tx_done = 0;
  1857. set_signals(info);
  1858. }
  1859. #if SYNCLINK_GENERIC_HDLC
  1860. if (info->netcount)
  1861. hdlcdev_tx_done(info);
  1862. else
  1863. #endif
  1864. {
  1865. if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
  1866. tx_stop(info);
  1867. return;
  1868. }
  1869. info->pending_bh |= BH_TRANSMIT;
  1870. }
  1871. }
  1872. }
  1873. static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
  1874. {
  1875. struct cond_wait *w, *prev;
  1876. /* wake processes waiting for specific transitions */
  1877. for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
  1878. if (w->data & changed) {
  1879. w->data = state;
  1880. wake_up_interruptible(&w->q);
  1881. if (prev != NULL)
  1882. prev->next = w->next;
  1883. else
  1884. info->gpio_wait_q = w->next;
  1885. } else
  1886. prev = w;
  1887. }
  1888. }
  1889. /* interrupt service routine
  1890. *
  1891. * irq interrupt number
  1892. * dev_id device ID supplied during interrupt registration
  1893. */
  1894. static irqreturn_t slgt_interrupt(int irq, void *dev_id)
  1895. {
  1896. struct slgt_info *info;
  1897. unsigned int gsr;
  1898. unsigned int i;
  1899. DBGISR(("slgt_interrupt irq=%d entry\n", irq));
  1900. info = dev_id;
  1901. if (!info)
  1902. return IRQ_NONE;
  1903. spin_lock(&info->lock);
  1904. while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
  1905. DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
  1906. info->irq_occurred = 1;
  1907. for(i=0; i < info->port_count ; i++) {
  1908. if (info->port_array[i] == NULL)
  1909. continue;
  1910. if (gsr & (BIT8 << i))
  1911. isr_serial(info->port_array[i]);
  1912. if (gsr & (BIT16 << (i*2)))
  1913. isr_rdma(info->port_array[i]);
  1914. if (gsr & (BIT17 << (i*2)))
  1915. isr_tdma(info->port_array[i]);
  1916. }
  1917. }
  1918. if (info->gpio_present) {
  1919. unsigned int state;
  1920. unsigned int changed;
  1921. while ((changed = rd_reg32(info, IOSR)) != 0) {
  1922. DBGISR(("%s iosr=%08x\n", info->device_name, changed));
  1923. /* read latched state of GPIO signals */
  1924. state = rd_reg32(info, IOVR);
  1925. /* clear pending GPIO interrupt bits */
  1926. wr_reg32(info, IOSR, changed);
  1927. for (i=0 ; i < info->port_count ; i++) {
  1928. if (info->port_array[i] != NULL)
  1929. isr_gpio(info->port_array[i], changed, state);
  1930. }
  1931. }
  1932. }
  1933. for(i=0; i < info->port_count ; i++) {
  1934. struct slgt_info *port = info->port_array[i];
  1935. if (port && (port->count || port->netcount) &&
  1936. port->pending_bh && !port->bh_running &&
  1937. !port->bh_requested) {
  1938. DBGISR(("%s bh queued\n", port->device_name));
  1939. schedule_work(&port->task);
  1940. port->bh_requested = 1;
  1941. }
  1942. }
  1943. spin_unlock(&info->lock);
  1944. DBGISR(("slgt_interrupt irq=%d exit\n", irq));
  1945. return IRQ_HANDLED;
  1946. }
  1947. static int startup(struct slgt_info *info)
  1948. {
  1949. DBGINFO(("%s startup\n", info->device_name));
  1950. if (info->flags & ASYNC_INITIALIZED)
  1951. return 0;
  1952. if (!info->tx_buf) {
  1953. info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
  1954. if (!info->tx_buf) {
  1955. DBGERR(("%s can't allocate tx buffer\n", info->device_name));
  1956. return -ENOMEM;
  1957. }
  1958. }
  1959. info->pending_bh = 0;
  1960. memset(&info->icount, 0, sizeof(info->icount));
  1961. /* program hardware for current parameters */
  1962. change_params(info);
  1963. if (info->tty)
  1964. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  1965. info->flags |= ASYNC_INITIALIZED;
  1966. return 0;
  1967. }
  1968. /*
  1969. * called by close() and hangup() to shutdown hardware
  1970. */
  1971. static void shutdown(struct slgt_info *info)
  1972. {
  1973. unsigned long flags;
  1974. if (!(info->flags & ASYNC_INITIALIZED))
  1975. return;
  1976. DBGINFO(("%s shutdown\n", info->device_name));
  1977. /* clear status wait queue because status changes */
  1978. /* can't happen after shutting down the hardware */
  1979. wake_up_interruptible(&info->status_event_wait_q);
  1980. wake_up_interruptible(&info->event_wait_q);
  1981. del_timer_sync(&info->tx_timer);
  1982. del_timer_sync(&info->rx_timer);
  1983. kfree(info->tx_buf);
  1984. info->tx_buf = NULL;
  1985. spin_lock_irqsave(&info->lock,flags);
  1986. tx_stop(info);
  1987. rx_stop(info);
  1988. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  1989. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  1990. info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1991. set_signals(info);
  1992. }
  1993. flush_cond_wait(&info->gpio_wait_q);
  1994. spin_unlock_irqrestore(&info->lock,flags);
  1995. if (info->tty)
  1996. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1997. info->flags &= ~ASYNC_INITIALIZED;
  1998. }
  1999. static void program_hw(struct slgt_info *info)
  2000. {
  2001. unsigned long flags;
  2002. spin_lock_irqsave(&info->lock,flags);
  2003. rx_stop(info);
  2004. tx_stop(info);
  2005. if (info->params.mode != MGSL_MODE_ASYNC ||
  2006. info->netcount)
  2007. sync_mode(info);
  2008. else
  2009. async_mode(info);
  2010. set_signals(info);
  2011. info->dcd_chkcount = 0;
  2012. info->cts_chkcount = 0;
  2013. info->ri_chkcount = 0;
  2014. info->dsr_chkcount = 0;
  2015. slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
  2016. get_signals(info);
  2017. if (info->netcount ||
  2018. (info->tty && info->tty->termios->c_cflag & CREAD))
  2019. rx_start(info);
  2020. spin_unlock_irqrestore(&info->lock,flags);
  2021. }
  2022. /*
  2023. * reconfigure adapter based on new parameters
  2024. */
  2025. static void change_params(struct slgt_info *info)
  2026. {
  2027. unsigned cflag;
  2028. int bits_per_char;
  2029. if (!info->tty || !info->tty->termios)
  2030. return;
  2031. DBGINFO(("%s change_params\n", info->device_name));
  2032. cflag = info->tty->termios->c_cflag;
  2033. /* if B0 rate (hangup) specified then negate DTR and RTS */
  2034. /* otherwise assert DTR and RTS */
  2035. if (cflag & CBAUD)
  2036. info->signals |= SerialSignal_RTS + SerialSignal_DTR;
  2037. else
  2038. info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2039. /* byte size and parity */
  2040. switch (cflag & CSIZE) {
  2041. case CS5: info->params.data_bits = 5; break;
  2042. case CS6: info->params.data_bits = 6; break;
  2043. case CS7: info->params.data_bits = 7; break;
  2044. case CS8: info->params.data_bits = 8; break;
  2045. default: info->params.data_bits = 7; break;
  2046. }
  2047. info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
  2048. if (cflag & PARENB)
  2049. info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
  2050. else
  2051. info->params.parity = ASYNC_PARITY_NONE;
  2052. /* calculate number of jiffies to transmit a full
  2053. * FIFO (32 bytes) at specified data rate
  2054. */
  2055. bits_per_char = info->params.data_bits +
  2056. info->params.stop_bits + 1;
  2057. info->params.data_rate = tty_get_baud_rate(info->tty);
  2058. if (info->params.data_rate) {
  2059. info->timeout = (32*HZ*bits_per_char) /
  2060. info->params.data_rate;
  2061. }
  2062. info->timeout += HZ/50; /* Add .02 seconds of slop */
  2063. if (cflag & CRTSCTS)
  2064. info->flags |= ASYNC_CTS_FLOW;
  2065. else
  2066. info->flags &= ~ASYNC_CTS_FLOW;
  2067. if (cflag & CLOCAL)
  2068. info->flags &= ~ASYNC_CHECK_CD;
  2069. else
  2070. info->flags |= ASYNC_CHECK_CD;
  2071. /* process tty input control flags */
  2072. info->read_status_mask = IRQ_RXOVER;
  2073. if (I_INPCK(info->tty))
  2074. info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
  2075. if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
  2076. info->read_status_mask |= MASK_BREAK;
  2077. if (I_IGNPAR(info->tty))
  2078. info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
  2079. if (I_IGNBRK(info->tty)) {
  2080. info->ignore_status_mask |= MASK_BREAK;
  2081. /* If ignoring parity and break indicators, ignore
  2082. * overruns too. (For real raw support).
  2083. */
  2084. if (I_IGNPAR(info->tty))
  2085. info->ignore_status_mask |= MASK_OVERRUN;
  2086. }
  2087. program_hw(info);
  2088. }
  2089. static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
  2090. {
  2091. DBGINFO(("%s get_stats\n", info->device_name));
  2092. if (!user_icount) {
  2093. memset(&info->icount, 0, sizeof(info->icount));
  2094. } else {
  2095. if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
  2096. return -EFAULT;
  2097. }
  2098. return 0;
  2099. }
  2100. static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
  2101. {
  2102. DBGINFO(("%s get_params\n", info->device_name));
  2103. if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
  2104. return -EFAULT;
  2105. return 0;
  2106. }
  2107. static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
  2108. {
  2109. unsigned long flags;
  2110. MGSL_PARAMS tmp_params;
  2111. DBGINFO(("%s set_params\n", info->device_name));
  2112. if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
  2113. return -EFAULT;
  2114. spin_lock_irqsave(&info->lock, flags);
  2115. memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
  2116. spin_unlock_irqrestore(&info->lock, flags);
  2117. change_params(info);
  2118. return 0;
  2119. }
  2120. static int get_txidle(struct slgt_info *info, int __user *idle_mode)
  2121. {
  2122. DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
  2123. if (put_user(info->idle_mode, idle_mode))
  2124. return -EFAULT;
  2125. return 0;
  2126. }
  2127. static int set_txidle(struct slgt_info *info, int idle_mode)
  2128. {
  2129. unsigned long flags;
  2130. DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
  2131. spin_lock_irqsave(&info->lock,flags);
  2132. info->idle_mode = idle_mode;
  2133. if (info->params.mode != MGSL_MODE_ASYNC)
  2134. tx_set_idle(info);
  2135. spin_unlock_irqrestore(&info->lock,flags);
  2136. return 0;
  2137. }
  2138. static int tx_enable(struct slgt_info *info, int enable)
  2139. {
  2140. unsigned long flags;
  2141. DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
  2142. spin_lock_irqsave(&info->lock,flags);
  2143. if (enable) {
  2144. if (!info->tx_enabled)
  2145. tx_start(info);
  2146. } else {
  2147. if (info->tx_enabled)
  2148. tx_stop(info);
  2149. }
  2150. spin_unlock_irqrestore(&info->lock,flags);
  2151. return 0;
  2152. }
  2153. /*
  2154. * abort transmit HDLC frame
  2155. */
  2156. static int tx_abort(struct slgt_info *info)
  2157. {
  2158. unsigned long flags;
  2159. DBGINFO(("%s tx_abort\n", info->device_name));
  2160. spin_lock_irqsave(&info->lock,flags);
  2161. tdma_reset(info);
  2162. spin_unlock_irqrestore(&info->lock,flags);
  2163. return 0;
  2164. }
  2165. static int rx_enable(struct slgt_info *info, int enable)
  2166. {
  2167. unsigned long flags;
  2168. DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
  2169. spin_lock_irqsave(&info->lock,flags);
  2170. if (enable) {
  2171. if (!info->rx_enabled)
  2172. rx_start(info);
  2173. else if (enable == 2) {
  2174. /* force hunt mode (write 1 to RCR[3]) */
  2175. wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
  2176. }
  2177. } else {
  2178. if (info->rx_enabled)
  2179. rx_stop(info);
  2180. }
  2181. spin_unlock_irqrestore(&info->lock,flags);
  2182. return 0;
  2183. }
  2184. /*
  2185. * wait for specified event to occur
  2186. */
  2187. static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
  2188. {
  2189. unsigned long flags;
  2190. int s;
  2191. int rc=0;
  2192. struct mgsl_icount cprev, cnow;
  2193. int events;
  2194. int mask;
  2195. struct _input_signal_events oldsigs, newsigs;
  2196. DECLARE_WAITQUEUE(wait, current);
  2197. if (get_user(mask, mask_ptr))
  2198. return -EFAULT;
  2199. DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
  2200. spin_lock_irqsave(&info->lock,flags);
  2201. /* return immediately if state matches requested events */
  2202. get_signals(info);
  2203. s = info->signals;
  2204. events = mask &
  2205. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2206. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2207. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2208. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2209. if (events) {
  2210. spin_unlock_irqrestore(&info->lock,flags);
  2211. goto exit;
  2212. }
  2213. /* save current irq counts */
  2214. cprev = info->icount;
  2215. oldsigs = info->input_signal_events;
  2216. /* enable hunt and idle irqs if needed */
  2217. if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
  2218. unsigned short val = rd_reg16(info, SCR);
  2219. if (!(val & IRQ_RXIDLE))
  2220. wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
  2221. }
  2222. set_current_state(TASK_INTERRUPTIBLE);
  2223. add_wait_queue(&info->event_wait_q, &wait);
  2224. spin_unlock_irqrestore(&info->lock,flags);
  2225. for(;;) {
  2226. schedule();
  2227. if (signal_pending(current)) {
  2228. rc = -ERESTARTSYS;
  2229. break;
  2230. }
  2231. /* get current irq counts */
  2232. spin_lock_irqsave(&info->lock,flags);
  2233. cnow = info->icount;
  2234. newsigs = info->input_signal_events;
  2235. set_current_state(TASK_INTERRUPTIBLE);
  2236. spin_unlock_irqrestore(&info->lock,flags);
  2237. /* if no change, wait aborted for some reason */
  2238. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2239. newsigs.dsr_down == oldsigs.dsr_down &&
  2240. newsigs.dcd_up == oldsigs.dcd_up &&
  2241. newsigs.dcd_down == oldsigs.dcd_down &&
  2242. newsigs.cts_up == oldsigs.cts_up &&
  2243. newsigs.cts_down == oldsigs.cts_down &&
  2244. newsigs.ri_up == oldsigs.ri_up &&
  2245. newsigs.ri_down == oldsigs.ri_down &&
  2246. cnow.exithunt == cprev.exithunt &&
  2247. cnow.rxidle == cprev.rxidle) {
  2248. rc = -EIO;
  2249. break;
  2250. }
  2251. events = mask &
  2252. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2253. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2254. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2255. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2256. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2257. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2258. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2259. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2260. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2261. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2262. if (events)
  2263. break;
  2264. cprev = cnow;
  2265. oldsigs = newsigs;
  2266. }
  2267. remove_wait_queue(&info->event_wait_q, &wait);
  2268. set_current_state(TASK_RUNNING);
  2269. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2270. spin_lock_irqsave(&info->lock,flags);
  2271. if (!waitqueue_active(&info->event_wait_q)) {
  2272. /* disable enable exit hunt mode/idle rcvd IRQs */
  2273. wr_reg16(info, SCR,
  2274. (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
  2275. }
  2276. spin_unlock_irqrestore(&info->lock,flags);
  2277. }
  2278. exit:
  2279. if (rc == 0)
  2280. rc = put_user(events, mask_ptr);
  2281. return rc;
  2282. }
  2283. static int get_interface(struct slgt_info *info, int __user *if_mode)
  2284. {
  2285. DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
  2286. if (put_user(info->if_mode, if_mode))
  2287. return -EFAULT;
  2288. return 0;
  2289. }
  2290. static int set_interface(struct slgt_info *info, int if_mode)
  2291. {
  2292. unsigned long flags;
  2293. unsigned short val;
  2294. DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
  2295. spin_lock_irqsave(&info->lock,flags);
  2296. info->if_mode = if_mode;
  2297. msc_set_vcr(info);
  2298. /* TCR (tx control) 07 1=RTS driver control */
  2299. val = rd_reg16(info, TCR);
  2300. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  2301. val |= BIT7;
  2302. else
  2303. val &= ~BIT7;
  2304. wr_reg16(info, TCR, val);
  2305. spin_unlock_irqrestore(&info->lock,flags);
  2306. return 0;
  2307. }
  2308. /*
  2309. * set general purpose IO pin state and direction
  2310. *
  2311. * user_gpio fields:
  2312. * state each bit indicates a pin state
  2313. * smask set bit indicates pin state to set
  2314. * dir each bit indicates a pin direction (0=input, 1=output)
  2315. * dmask set bit indicates pin direction to set
  2316. */
  2317. static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2318. {
  2319. unsigned long flags;
  2320. struct gpio_desc gpio;
  2321. __u32 data;
  2322. if (!info->gpio_present)
  2323. return -EINVAL;
  2324. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2325. return -EFAULT;
  2326. DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
  2327. info->device_name, gpio.state, gpio.smask,
  2328. gpio.dir, gpio.dmask));
  2329. spin_lock_irqsave(&info->lock,flags);
  2330. if (gpio.dmask) {
  2331. data = rd_reg32(info, IODR);
  2332. data |= gpio.dmask & gpio.dir;
  2333. data &= ~(gpio.dmask & ~gpio.dir);
  2334. wr_reg32(info, IODR, data);
  2335. }
  2336. if (gpio.smask) {
  2337. data = rd_reg32(info, IOVR);
  2338. data |= gpio.smask & gpio.state;
  2339. data &= ~(gpio.smask & ~gpio.state);
  2340. wr_reg32(info, IOVR, data);
  2341. }
  2342. spin_unlock_irqrestore(&info->lock,flags);
  2343. return 0;
  2344. }
  2345. /*
  2346. * get general purpose IO pin state and direction
  2347. */
  2348. static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2349. {
  2350. struct gpio_desc gpio;
  2351. if (!info->gpio_present)
  2352. return -EINVAL;
  2353. gpio.state = rd_reg32(info, IOVR);
  2354. gpio.smask = 0xffffffff;
  2355. gpio.dir = rd_reg32(info, IODR);
  2356. gpio.dmask = 0xffffffff;
  2357. if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2358. return -EFAULT;
  2359. DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
  2360. info->device_name, gpio.state, gpio.dir));
  2361. return 0;
  2362. }
  2363. /*
  2364. * conditional wait facility
  2365. */
  2366. static void init_cond_wait(struct cond_wait *w, unsigned int data)
  2367. {
  2368. init_waitqueue_head(&w->q);
  2369. init_waitqueue_entry(&w->wait, current);
  2370. w->data = data;
  2371. }
  2372. static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
  2373. {
  2374. set_current_state(TASK_INTERRUPTIBLE);
  2375. add_wait_queue(&w->q, &w->wait);
  2376. w->next = *head;
  2377. *head = w;
  2378. }
  2379. static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
  2380. {
  2381. struct cond_wait *w, *prev;
  2382. remove_wait_queue(&cw->q, &cw->wait);
  2383. set_current_state(TASK_RUNNING);
  2384. for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
  2385. if (w == cw) {
  2386. if (prev != NULL)
  2387. prev->next = w->next;
  2388. else
  2389. *head = w->next;
  2390. break;
  2391. }
  2392. }
  2393. }
  2394. static void flush_cond_wait(struct cond_wait **head)
  2395. {
  2396. while (*head != NULL) {
  2397. wake_up_interruptible(&(*head)->q);
  2398. *head = (*head)->next;
  2399. }
  2400. }
  2401. /*
  2402. * wait for general purpose I/O pin(s) to enter specified state
  2403. *
  2404. * user_gpio fields:
  2405. * state - bit indicates target pin state
  2406. * smask - set bit indicates watched pin
  2407. *
  2408. * The wait ends when at least one watched pin enters the specified
  2409. * state. When 0 (no error) is returned, user_gpio->state is set to the
  2410. * state of all GPIO pins when the wait ends.
  2411. *
  2412. * Note: Each pin may be a dedicated input, dedicated output, or
  2413. * configurable input/output. The number and configuration of pins
  2414. * varies with the specific adapter model. Only input pins (dedicated
  2415. * or configured) can be monitored with this function.
  2416. */
  2417. static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
  2418. {
  2419. unsigned long flags;
  2420. int rc = 0;
  2421. struct gpio_desc gpio;
  2422. struct cond_wait wait;
  2423. u32 state;
  2424. if (!info->gpio_present)
  2425. return -EINVAL;
  2426. if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
  2427. return -EFAULT;
  2428. DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
  2429. info->device_name, gpio.state, gpio.smask));
  2430. /* ignore output pins identified by set IODR bit */
  2431. if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
  2432. return -EINVAL;
  2433. init_cond_wait(&wait, gpio.smask);
  2434. spin_lock_irqsave(&info->lock, flags);
  2435. /* enable interrupts for watched pins */
  2436. wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
  2437. /* get current pin states */
  2438. state = rd_reg32(info, IOVR);
  2439. if (gpio.smask & ~(state ^ gpio.state)) {
  2440. /* already in target state */
  2441. gpio.state = state;
  2442. } else {
  2443. /* wait for target state */
  2444. add_cond_wait(&info->gpio_wait_q, &wait);
  2445. spin_unlock_irqrestore(&info->lock, flags);
  2446. schedule();
  2447. if (signal_pending(current))
  2448. rc = -ERESTARTSYS;
  2449. else
  2450. gpio.state = wait.data;
  2451. spin_lock_irqsave(&info->lock, flags);
  2452. remove_cond_wait(&info->gpio_wait_q, &wait);
  2453. }
  2454. /* disable all GPIO interrupts if no waiting processes */
  2455. if (info->gpio_wait_q == NULL)
  2456. wr_reg32(info, IOER, 0);
  2457. spin_unlock_irqrestore(&info->lock,flags);
  2458. if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
  2459. rc = -EFAULT;
  2460. return rc;
  2461. }
  2462. static int modem_input_wait(struct slgt_info *info,int arg)
  2463. {
  2464. unsigned long flags;
  2465. int rc;
  2466. struct mgsl_icount cprev, cnow;
  2467. DECLARE_WAITQUEUE(wait, current);
  2468. /* save current irq counts */
  2469. spin_lock_irqsave(&info->lock,flags);
  2470. cprev = info->icount;
  2471. add_wait_queue(&info->status_event_wait_q, &wait);
  2472. set_current_state(TASK_INTERRUPTIBLE);
  2473. spin_unlock_irqrestore(&info->lock,flags);
  2474. for(;;) {
  2475. schedule();
  2476. if (signal_pending(current)) {
  2477. rc = -ERESTARTSYS;
  2478. break;
  2479. }
  2480. /* get new irq counts */
  2481. spin_lock_irqsave(&info->lock,flags);
  2482. cnow = info->icount;
  2483. set_current_state(TASK_INTERRUPTIBLE);
  2484. spin_unlock_irqrestore(&info->lock,flags);
  2485. /* if no change, wait aborted for some reason */
  2486. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2487. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2488. rc = -EIO;
  2489. break;
  2490. }
  2491. /* check for change in caller specified modem input */
  2492. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2493. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2494. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2495. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2496. rc = 0;
  2497. break;
  2498. }
  2499. cprev = cnow;
  2500. }
  2501. remove_wait_queue(&info->status_event_wait_q, &wait);
  2502. set_current_state(TASK_RUNNING);
  2503. return rc;
  2504. }
  2505. /*
  2506. * return state of serial control and status signals
  2507. */
  2508. static int tiocmget(struct tty_struct *tty, struct file *file)
  2509. {
  2510. struct slgt_info *info = tty->driver_data;
  2511. unsigned int result;
  2512. unsigned long flags;
  2513. spin_lock_irqsave(&info->lock,flags);
  2514. get_signals(info);
  2515. spin_unlock_irqrestore(&info->lock,flags);
  2516. result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2517. ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2518. ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2519. ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2520. ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2521. ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2522. DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
  2523. return result;
  2524. }
  2525. /*
  2526. * set modem control signals (DTR/RTS)
  2527. *
  2528. * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
  2529. * TIOCMSET = set/clear signal values
  2530. * value bit mask for command
  2531. */
  2532. static int tiocmset(struct tty_struct *tty, struct file *file,
  2533. unsigned int set, unsigned int clear)
  2534. {
  2535. struct slgt_info *info = tty->driver_data;
  2536. unsigned long flags;
  2537. DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
  2538. if (set & TIOCM_RTS)
  2539. info->signals |= SerialSignal_RTS;
  2540. if (set & TIOCM_DTR)
  2541. info->signals |= SerialSignal_DTR;
  2542. if (clear & TIOCM_RTS)
  2543. info->signals &= ~SerialSignal_RTS;
  2544. if (clear & TIOCM_DTR)
  2545. info->signals &= ~SerialSignal_DTR;
  2546. spin_lock_irqsave(&info->lock,flags);
  2547. set_signals(info);
  2548. spin_unlock_irqrestore(&info->lock,flags);
  2549. return 0;
  2550. }
  2551. /*
  2552. * block current process until the device is ready to open
  2553. */
  2554. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2555. struct slgt_info *info)
  2556. {
  2557. DECLARE_WAITQUEUE(wait, current);
  2558. int retval;
  2559. int do_clocal = 0, extra_count = 0;
  2560. unsigned long flags;
  2561. DBGINFO(("%s block_til_ready\n", tty->driver->name));
  2562. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2563. /* nonblock mode is set or port is not enabled */
  2564. info->flags |= ASYNC_NORMAL_ACTIVE;
  2565. return 0;
  2566. }
  2567. if (tty->termios->c_cflag & CLOCAL)
  2568. do_clocal = 1;
  2569. /* Wait for carrier detect and the line to become
  2570. * free (i.e., not in use by the callout). While we are in
  2571. * this loop, info->count is dropped by one, so that
  2572. * close() knows when to free things. We restore it upon
  2573. * exit, either normal or abnormal.
  2574. */
  2575. retval = 0;
  2576. add_wait_queue(&info->open_wait, &wait);
  2577. spin_lock_irqsave(&info->lock, flags);
  2578. if (!tty_hung_up_p(filp)) {
  2579. extra_count = 1;
  2580. info->count--;
  2581. }
  2582. spin_unlock_irqrestore(&info->lock, flags);
  2583. info->blocked_open++;
  2584. while (1) {
  2585. if ((tty->termios->c_cflag & CBAUD)) {
  2586. spin_lock_irqsave(&info->lock,flags);
  2587. info->signals |= SerialSignal_RTS + SerialSignal_DTR;
  2588. set_signals(info);
  2589. spin_unlock_irqrestore(&info->lock,flags);
  2590. }
  2591. set_current_state(TASK_INTERRUPTIBLE);
  2592. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2593. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2594. -EAGAIN : -ERESTARTSYS;
  2595. break;
  2596. }
  2597. spin_lock_irqsave(&info->lock,flags);
  2598. get_signals(info);
  2599. spin_unlock_irqrestore(&info->lock,flags);
  2600. if (!(info->flags & ASYNC_CLOSING) &&
  2601. (do_clocal || (info->signals & SerialSignal_DCD)) ) {
  2602. break;
  2603. }
  2604. if (signal_pending(current)) {
  2605. retval = -ERESTARTSYS;
  2606. break;
  2607. }
  2608. DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
  2609. schedule();
  2610. }
  2611. set_current_state(TASK_RUNNING);
  2612. remove_wait_queue(&info->open_wait, &wait);
  2613. if (extra_count)
  2614. info->count++;
  2615. info->blocked_open--;
  2616. if (!retval)
  2617. info->flags |= ASYNC_NORMAL_ACTIVE;
  2618. DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
  2619. return retval;
  2620. }
  2621. static int alloc_tmp_rbuf(struct slgt_info *info)
  2622. {
  2623. info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
  2624. if (info->tmp_rbuf == NULL)
  2625. return -ENOMEM;
  2626. return 0;
  2627. }
  2628. static void free_tmp_rbuf(struct slgt_info *info)
  2629. {
  2630. kfree(info->tmp_rbuf);
  2631. info->tmp_rbuf = NULL;
  2632. }
  2633. /*
  2634. * allocate DMA descriptor lists.
  2635. */
  2636. static int alloc_desc(struct slgt_info *info)
  2637. {
  2638. unsigned int i;
  2639. unsigned int pbufs;
  2640. /* allocate memory to hold descriptor lists */
  2641. info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
  2642. if (info->bufs == NULL)
  2643. return -ENOMEM;
  2644. memset(info->bufs, 0, DESC_LIST_SIZE);
  2645. info->rbufs = (struct slgt_desc*)info->bufs;
  2646. info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
  2647. pbufs = (unsigned int)info->bufs_dma_addr;
  2648. /*
  2649. * Build circular lists of descriptors
  2650. */
  2651. for (i=0; i < info->rbuf_count; i++) {
  2652. /* physical address of this descriptor */
  2653. info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
  2654. /* physical address of next descriptor */
  2655. if (i == info->rbuf_count - 1)
  2656. info->rbufs[i].next = cpu_to_le32(pbufs);
  2657. else
  2658. info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
  2659. set_desc_count(info->rbufs[i], DMABUFSIZE);
  2660. }
  2661. for (i=0; i < info->tbuf_count; i++) {
  2662. /* physical address of this descriptor */
  2663. info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
  2664. /* physical address of next descriptor */
  2665. if (i == info->tbuf_count - 1)
  2666. info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
  2667. else
  2668. info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
  2669. }
  2670. return 0;
  2671. }
  2672. static void free_desc(struct slgt_info *info)
  2673. {
  2674. if (info->bufs != NULL) {
  2675. pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
  2676. info->bufs = NULL;
  2677. info->rbufs = NULL;
  2678. info->tbufs = NULL;
  2679. }
  2680. }
  2681. static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2682. {
  2683. int i;
  2684. for (i=0; i < count; i++) {
  2685. if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
  2686. return -ENOMEM;
  2687. bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
  2688. }
  2689. return 0;
  2690. }
  2691. static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
  2692. {
  2693. int i;
  2694. for (i=0; i < count; i++) {
  2695. if (bufs[i].buf == NULL)
  2696. continue;
  2697. pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
  2698. bufs[i].buf = NULL;
  2699. }
  2700. }
  2701. static int alloc_dma_bufs(struct slgt_info *info)
  2702. {
  2703. info->rbuf_count = 32;
  2704. info->tbuf_count = 32;
  2705. if (alloc_desc(info) < 0 ||
  2706. alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
  2707. alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
  2708. alloc_tmp_rbuf(info) < 0) {
  2709. DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
  2710. return -ENOMEM;
  2711. }
  2712. reset_rbufs(info);
  2713. return 0;
  2714. }
  2715. static void free_dma_bufs(struct slgt_info *info)
  2716. {
  2717. if (info->bufs) {
  2718. free_bufs(info, info->rbufs, info->rbuf_count);
  2719. free_bufs(info, info->tbufs, info->tbuf_count);
  2720. free_desc(info);
  2721. }
  2722. free_tmp_rbuf(info);
  2723. }
  2724. static int claim_resources(struct slgt_info *info)
  2725. {
  2726. if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
  2727. DBGERR(("%s reg addr conflict, addr=%08X\n",
  2728. info->device_name, info->phys_reg_addr));
  2729. info->init_error = DiagStatus_AddressConflict;
  2730. goto errout;
  2731. }
  2732. else
  2733. info->reg_addr_requested = 1;
  2734. info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
  2735. if (!info->reg_addr) {
  2736. DBGERR(("%s cant map device registers, addr=%08X\n",
  2737. info->device_name, info->phys_reg_addr));
  2738. info->init_error = DiagStatus_CantAssignPciResources;
  2739. goto errout;
  2740. }
  2741. return 0;
  2742. errout:
  2743. release_resources(info);
  2744. return -ENODEV;
  2745. }
  2746. static void release_resources(struct slgt_info *info)
  2747. {
  2748. if (info->irq_requested) {
  2749. free_irq(info->irq_level, info);
  2750. info->irq_requested = 0;
  2751. }
  2752. if (info->reg_addr_requested) {
  2753. release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
  2754. info->reg_addr_requested = 0;
  2755. }
  2756. if (info->reg_addr) {
  2757. iounmap(info->reg_addr);
  2758. info->reg_addr = NULL;
  2759. }
  2760. }
  2761. /* Add the specified device instance data structure to the
  2762. * global linked list of devices and increment the device count.
  2763. */
  2764. static void add_device(struct slgt_info *info)
  2765. {
  2766. char *devstr;
  2767. info->next_device = NULL;
  2768. info->line = slgt_device_count;
  2769. sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
  2770. if (info->line < MAX_DEVICES) {
  2771. if (maxframe[info->line])
  2772. info->max_frame_size = maxframe[info->line];
  2773. info->dosyncppp = dosyncppp[info->line];
  2774. }
  2775. slgt_device_count++;
  2776. if (!slgt_device_list)
  2777. slgt_device_list = info;
  2778. else {
  2779. struct slgt_info *current_dev = slgt_device_list;
  2780. while(current_dev->next_device)
  2781. current_dev = current_dev->next_device;
  2782. current_dev->next_device = info;
  2783. }
  2784. if (info->max_frame_size < 4096)
  2785. info->max_frame_size = 4096;
  2786. else if (info->max_frame_size > 65535)
  2787. info->max_frame_size = 65535;
  2788. switch(info->pdev->device) {
  2789. case SYNCLINK_GT_DEVICE_ID:
  2790. devstr = "GT";
  2791. break;
  2792. case SYNCLINK_GT2_DEVICE_ID:
  2793. devstr = "GT2";
  2794. break;
  2795. case SYNCLINK_GT4_DEVICE_ID:
  2796. devstr = "GT4";
  2797. break;
  2798. case SYNCLINK_AC_DEVICE_ID:
  2799. devstr = "AC";
  2800. info->params.mode = MGSL_MODE_ASYNC;
  2801. break;
  2802. default:
  2803. devstr = "(unknown model)";
  2804. }
  2805. printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
  2806. devstr, info->device_name, info->phys_reg_addr,
  2807. info->irq_level, info->max_frame_size);
  2808. #if SYNCLINK_GENERIC_HDLC
  2809. hdlcdev_init(info);
  2810. #endif
  2811. }
  2812. /*
  2813. * allocate device instance structure, return NULL on failure
  2814. */
  2815. static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
  2816. {
  2817. struct slgt_info *info;
  2818. info = kmalloc(sizeof(struct slgt_info), GFP_KERNEL);
  2819. if (!info) {
  2820. DBGERR(("%s device alloc failed adapter=%d port=%d\n",
  2821. driver_name, adapter_num, port_num));
  2822. } else {
  2823. memset(info, 0, sizeof(struct slgt_info));
  2824. info->magic = MGSL_MAGIC;
  2825. INIT_WORK(&info->task, bh_handler);
  2826. info->max_frame_size = 4096;
  2827. info->raw_rx_size = DMABUFSIZE;
  2828. info->close_delay = 5*HZ/10;
  2829. info->closing_wait = 30*HZ;
  2830. init_waitqueue_head(&info->open_wait);
  2831. init_waitqueue_head(&info->close_wait);
  2832. init_waitqueue_head(&info->status_event_wait_q);
  2833. init_waitqueue_head(&info->event_wait_q);
  2834. spin_lock_init(&info->netlock);
  2835. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  2836. info->idle_mode = HDLC_TXIDLE_FLAGS;
  2837. info->adapter_num = adapter_num;
  2838. info->port_num = port_num;
  2839. setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
  2840. setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
  2841. /* Copy configuration info to device instance data */
  2842. info->pdev = pdev;
  2843. info->irq_level = pdev->irq;
  2844. info->phys_reg_addr = pci_resource_start(pdev,0);
  2845. info->bus_type = MGSL_BUS_TYPE_PCI;
  2846. info->irq_flags = IRQF_SHARED;
  2847. info->init_error = -1; /* assume error, set to 0 on successful init */
  2848. }
  2849. return info;
  2850. }
  2851. static void device_init(int adapter_num, struct pci_dev *pdev)
  2852. {
  2853. struct slgt_info *port_array[SLGT_MAX_PORTS];
  2854. int i;
  2855. int port_count = 1;
  2856. if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
  2857. port_count = 2;
  2858. else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
  2859. port_count = 4;
  2860. /* allocate device instances for all ports */
  2861. for (i=0; i < port_count; ++i) {
  2862. port_array[i] = alloc_dev(adapter_num, i, pdev);
  2863. if (port_array[i] == NULL) {
  2864. for (--i; i >= 0; --i)
  2865. kfree(port_array[i]);
  2866. return;
  2867. }
  2868. }
  2869. /* give copy of port_array to all ports and add to device list */
  2870. for (i=0; i < port_count; ++i) {
  2871. memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
  2872. add_device(port_array[i]);
  2873. port_array[i]->port_count = port_count;
  2874. spin_lock_init(&port_array[i]->lock);
  2875. }
  2876. /* Allocate and claim adapter resources */
  2877. if (!claim_resources(port_array[0])) {
  2878. alloc_dma_bufs(port_array[0]);
  2879. /* copy resource information from first port to others */
  2880. for (i = 1; i < port_count; ++i) {
  2881. port_array[i]->lock = port_array[0]->lock;
  2882. port_array[i]->irq_level = port_array[0]->irq_level;
  2883. port_array[i]->reg_addr = port_array[0]->reg_addr;
  2884. alloc_dma_bufs(port_array[i]);
  2885. }
  2886. if (request_irq(port_array[0]->irq_level,
  2887. slgt_interrupt,
  2888. port_array[0]->irq_flags,
  2889. port_array[0]->device_name,
  2890. port_array[0]) < 0) {
  2891. DBGERR(("%s request_irq failed IRQ=%d\n",
  2892. port_array[0]->device_name,
  2893. port_array[0]->irq_level));
  2894. } else {
  2895. port_array[0]->irq_requested = 1;
  2896. adapter_test(port_array[0]);
  2897. for (i=1 ; i < port_count ; i++) {
  2898. port_array[i]->init_error = port_array[0]->init_error;
  2899. port_array[i]->gpio_present = port_array[0]->gpio_present;
  2900. }
  2901. }
  2902. }
  2903. }
  2904. static int __devinit init_one(struct pci_dev *dev,
  2905. const struct pci_device_id *ent)
  2906. {
  2907. if (pci_enable_device(dev)) {
  2908. printk("error enabling pci device %p\n", dev);
  2909. return -EIO;
  2910. }
  2911. pci_set_master(dev);
  2912. device_init(slgt_device_count, dev);
  2913. return 0;
  2914. }
  2915. static void __devexit remove_one(struct pci_dev *dev)
  2916. {
  2917. }
  2918. static const struct tty_operations ops = {
  2919. .open = open,
  2920. .close = close,
  2921. .write = write,
  2922. .put_char = put_char,
  2923. .flush_chars = flush_chars,
  2924. .write_room = write_room,
  2925. .chars_in_buffer = chars_in_buffer,
  2926. .flush_buffer = flush_buffer,
  2927. .ioctl = ioctl,
  2928. .throttle = throttle,
  2929. .unthrottle = unthrottle,
  2930. .send_xchar = send_xchar,
  2931. .break_ctl = set_break,
  2932. .wait_until_sent = wait_until_sent,
  2933. .read_proc = read_proc,
  2934. .set_termios = set_termios,
  2935. .stop = tx_hold,
  2936. .start = tx_release,
  2937. .hangup = hangup,
  2938. .tiocmget = tiocmget,
  2939. .tiocmset = tiocmset,
  2940. };
  2941. static void slgt_cleanup(void)
  2942. {
  2943. int rc;
  2944. struct slgt_info *info;
  2945. struct slgt_info *tmp;
  2946. printk("unload %s %s\n", driver_name, driver_version);
  2947. if (serial_driver) {
  2948. if ((rc = tty_unregister_driver(serial_driver)))
  2949. DBGERR(("tty_unregister_driver error=%d\n", rc));
  2950. put_tty_driver(serial_driver);
  2951. }
  2952. /* reset devices */
  2953. info = slgt_device_list;
  2954. while(info) {
  2955. reset_port(info);
  2956. info = info->next_device;
  2957. }
  2958. /* release devices */
  2959. info = slgt_device_list;
  2960. while(info) {
  2961. #if SYNCLINK_GENERIC_HDLC
  2962. hdlcdev_exit(info);
  2963. #endif
  2964. free_dma_bufs(info);
  2965. free_tmp_rbuf(info);
  2966. if (info->port_num == 0)
  2967. release_resources(info);
  2968. tmp = info;
  2969. info = info->next_device;
  2970. kfree(tmp);
  2971. }
  2972. if (pci_registered)
  2973. pci_unregister_driver(&pci_driver);
  2974. }
  2975. /*
  2976. * Driver initialization entry point.
  2977. */
  2978. static int __init slgt_init(void)
  2979. {
  2980. int rc;
  2981. printk("%s %s\n", driver_name, driver_version);
  2982. slgt_device_count = 0;
  2983. if ((rc = pci_register_driver(&pci_driver)) < 0) {
  2984. printk("%s pci_register_driver error=%d\n", driver_name, rc);
  2985. return rc;
  2986. }
  2987. pci_registered = 1;
  2988. if (!slgt_device_list) {
  2989. printk("%s no devices found\n",driver_name);
  2990. pci_unregister_driver(&pci_driver);
  2991. return -ENODEV;
  2992. }
  2993. serial_driver = alloc_tty_driver(MAX_DEVICES);
  2994. if (!serial_driver) {
  2995. rc = -ENOMEM;
  2996. goto error;
  2997. }
  2998. /* Initialize the tty_driver structure */
  2999. serial_driver->owner = THIS_MODULE;
  3000. serial_driver->driver_name = tty_driver_name;
  3001. serial_driver->name = tty_dev_prefix;
  3002. serial_driver->major = ttymajor;
  3003. serial_driver->minor_start = 64;
  3004. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3005. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3006. serial_driver->init_termios = tty_std_termios;
  3007. serial_driver->init_termios.c_cflag =
  3008. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3009. serial_driver->init_termios.c_ispeed = 9600;
  3010. serial_driver->init_termios.c_ospeed = 9600;
  3011. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  3012. tty_set_operations(serial_driver, &ops);
  3013. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3014. DBGERR(("%s can't register serial driver\n", driver_name));
  3015. put_tty_driver(serial_driver);
  3016. serial_driver = NULL;
  3017. goto error;
  3018. }
  3019. printk("%s %s, tty major#%d\n",
  3020. driver_name, driver_version,
  3021. serial_driver->major);
  3022. return 0;
  3023. error:
  3024. slgt_cleanup();
  3025. return rc;
  3026. }
  3027. static void __exit slgt_exit(void)
  3028. {
  3029. slgt_cleanup();
  3030. }
  3031. module_init(slgt_init);
  3032. module_exit(slgt_exit);
  3033. /*
  3034. * register access routines
  3035. */
  3036. #define CALC_REGADDR() \
  3037. unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
  3038. if (addr >= 0x80) \
  3039. reg_addr += (info->port_num) * 32;
  3040. static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
  3041. {
  3042. CALC_REGADDR();
  3043. return readb((void __iomem *)reg_addr);
  3044. }
  3045. static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
  3046. {
  3047. CALC_REGADDR();
  3048. writeb(value, (void __iomem *)reg_addr);
  3049. }
  3050. static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
  3051. {
  3052. CALC_REGADDR();
  3053. return readw((void __iomem *)reg_addr);
  3054. }
  3055. static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
  3056. {
  3057. CALC_REGADDR();
  3058. writew(value, (void __iomem *)reg_addr);
  3059. }
  3060. static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
  3061. {
  3062. CALC_REGADDR();
  3063. return readl((void __iomem *)reg_addr);
  3064. }
  3065. static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
  3066. {
  3067. CALC_REGADDR();
  3068. writel(value, (void __iomem *)reg_addr);
  3069. }
  3070. static void rdma_reset(struct slgt_info *info)
  3071. {
  3072. unsigned int i;
  3073. /* set reset bit */
  3074. wr_reg32(info, RDCSR, BIT1);
  3075. /* wait for enable bit cleared */
  3076. for(i=0 ; i < 1000 ; i++)
  3077. if (!(rd_reg32(info, RDCSR) & BIT0))
  3078. break;
  3079. }
  3080. static void tdma_reset(struct slgt_info *info)
  3081. {
  3082. unsigned int i;
  3083. /* set reset bit */
  3084. wr_reg32(info, TDCSR, BIT1);
  3085. /* wait for enable bit cleared */
  3086. for(i=0 ; i < 1000 ; i++)
  3087. if (!(rd_reg32(info, TDCSR) & BIT0))
  3088. break;
  3089. }
  3090. /*
  3091. * enable internal loopback
  3092. * TxCLK and RxCLK are generated from BRG
  3093. * and TxD is looped back to RxD internally.
  3094. */
  3095. static void enable_loopback(struct slgt_info *info)
  3096. {
  3097. /* SCR (serial control) BIT2=looopback enable */
  3098. wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
  3099. if (info->params.mode != MGSL_MODE_ASYNC) {
  3100. /* CCR (clock control)
  3101. * 07..05 tx clock source (010 = BRG)
  3102. * 04..02 rx clock source (010 = BRG)
  3103. * 01 auxclk enable (0 = disable)
  3104. * 00 BRG enable (1 = enable)
  3105. *
  3106. * 0100 1001
  3107. */
  3108. wr_reg8(info, CCR, 0x49);
  3109. /* set speed if available, otherwise use default */
  3110. if (info->params.clock_speed)
  3111. set_rate(info, info->params.clock_speed);
  3112. else
  3113. set_rate(info, 3686400);
  3114. }
  3115. }
  3116. /*
  3117. * set baud rate generator to specified rate
  3118. */
  3119. static void set_rate(struct slgt_info *info, u32 rate)
  3120. {
  3121. unsigned int div;
  3122. static unsigned int osc = 14745600;
  3123. /* div = osc/rate - 1
  3124. *
  3125. * Round div up if osc/rate is not integer to
  3126. * force to next slowest rate.
  3127. */
  3128. if (rate) {
  3129. div = osc/rate;
  3130. if (!(osc % rate) && div)
  3131. div--;
  3132. wr_reg16(info, BDR, (unsigned short)div);
  3133. }
  3134. }
  3135. static void rx_stop(struct slgt_info *info)
  3136. {
  3137. unsigned short val;
  3138. /* disable and reset receiver */
  3139. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3140. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3141. wr_reg16(info, RCR, val); /* clear reset bit */
  3142. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
  3143. /* clear pending rx interrupts */
  3144. wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
  3145. rdma_reset(info);
  3146. info->rx_enabled = 0;
  3147. info->rx_restart = 0;
  3148. }
  3149. static void rx_start(struct slgt_info *info)
  3150. {
  3151. unsigned short val;
  3152. slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
  3153. /* clear pending rx overrun IRQ */
  3154. wr_reg16(info, SSR, IRQ_RXOVER);
  3155. /* reset and disable receiver */
  3156. val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
  3157. wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3158. wr_reg16(info, RCR, val); /* clear reset bit */
  3159. rdma_reset(info);
  3160. reset_rbufs(info);
  3161. /* set 1st descriptor address */
  3162. wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
  3163. if (info->params.mode != MGSL_MODE_ASYNC) {
  3164. /* enable rx DMA and DMA interrupt */
  3165. wr_reg32(info, RDCSR, (BIT2 + BIT0));
  3166. } else {
  3167. /* enable saving of rx status, rx DMA and DMA interrupt */
  3168. wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
  3169. }
  3170. slgt_irq_on(info, IRQ_RXOVER);
  3171. /* enable receiver */
  3172. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
  3173. info->rx_restart = 0;
  3174. info->rx_enabled = 1;
  3175. }
  3176. static void tx_start(struct slgt_info *info)
  3177. {
  3178. if (!info->tx_enabled) {
  3179. wr_reg16(info, TCR,
  3180. (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
  3181. info->tx_enabled = TRUE;
  3182. }
  3183. if (info->tx_count) {
  3184. info->drop_rts_on_tx_done = 0;
  3185. if (info->params.mode != MGSL_MODE_ASYNC) {
  3186. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  3187. get_signals(info);
  3188. if (!(info->signals & SerialSignal_RTS)) {
  3189. info->signals |= SerialSignal_RTS;
  3190. set_signals(info);
  3191. info->drop_rts_on_tx_done = 1;
  3192. }
  3193. }
  3194. slgt_irq_off(info, IRQ_TXDATA);
  3195. slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
  3196. /* clear tx idle and underrun status bits */
  3197. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3198. if (!(rd_reg32(info, TDCSR) & BIT0)) {
  3199. /* tx DMA stopped, restart tx DMA */
  3200. tdma_reset(info);
  3201. /* set 1st descriptor address */
  3202. wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
  3203. switch(info->params.mode) {
  3204. case MGSL_MODE_RAW:
  3205. case MGSL_MODE_MONOSYNC:
  3206. case MGSL_MODE_BISYNC:
  3207. wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
  3208. break;
  3209. default:
  3210. wr_reg32(info, TDCSR, BIT0); /* DMA enable */
  3211. }
  3212. }
  3213. if (info->params.mode == MGSL_MODE_HDLC)
  3214. mod_timer(&info->tx_timer, jiffies +
  3215. msecs_to_jiffies(5000));
  3216. } else {
  3217. tdma_reset(info);
  3218. /* set 1st descriptor address */
  3219. wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
  3220. slgt_irq_off(info, IRQ_TXDATA);
  3221. slgt_irq_on(info, IRQ_TXIDLE);
  3222. /* clear tx idle status bit */
  3223. wr_reg16(info, SSR, IRQ_TXIDLE);
  3224. /* enable tx DMA */
  3225. wr_reg32(info, TDCSR, BIT0);
  3226. }
  3227. info->tx_active = 1;
  3228. }
  3229. }
  3230. static void tx_stop(struct slgt_info *info)
  3231. {
  3232. unsigned short val;
  3233. del_timer(&info->tx_timer);
  3234. tdma_reset(info);
  3235. /* reset and disable transmitter */
  3236. val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
  3237. wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
  3238. slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
  3239. /* clear tx idle and underrun status bit */
  3240. wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
  3241. reset_tbufs(info);
  3242. info->tx_enabled = 0;
  3243. info->tx_active = 0;
  3244. }
  3245. static void reset_port(struct slgt_info *info)
  3246. {
  3247. if (!info->reg_addr)
  3248. return;
  3249. tx_stop(info);
  3250. rx_stop(info);
  3251. info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  3252. set_signals(info);
  3253. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3254. }
  3255. static void reset_adapter(struct slgt_info *info)
  3256. {
  3257. int i;
  3258. for (i=0; i < info->port_count; ++i) {
  3259. if (info->port_array[i])
  3260. reset_port(info->port_array[i]);
  3261. }
  3262. }
  3263. static void async_mode(struct slgt_info *info)
  3264. {
  3265. unsigned short val;
  3266. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3267. tx_stop(info);
  3268. rx_stop(info);
  3269. /* TCR (tx control)
  3270. *
  3271. * 15..13 mode, 010=async
  3272. * 12..10 encoding, 000=NRZ
  3273. * 09 parity enable
  3274. * 08 1=odd parity, 0=even parity
  3275. * 07 1=RTS driver control
  3276. * 06 1=break enable
  3277. * 05..04 character length
  3278. * 00=5 bits
  3279. * 01=6 bits
  3280. * 10=7 bits
  3281. * 11=8 bits
  3282. * 03 0=1 stop bit, 1=2 stop bits
  3283. * 02 reset
  3284. * 01 enable
  3285. * 00 auto-CTS enable
  3286. */
  3287. val = 0x4000;
  3288. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3289. val |= BIT7;
  3290. if (info->params.parity != ASYNC_PARITY_NONE) {
  3291. val |= BIT9;
  3292. if (info->params.parity == ASYNC_PARITY_ODD)
  3293. val |= BIT8;
  3294. }
  3295. switch (info->params.data_bits)
  3296. {
  3297. case 6: val |= BIT4; break;
  3298. case 7: val |= BIT5; break;
  3299. case 8: val |= BIT5 + BIT4; break;
  3300. }
  3301. if (info->params.stop_bits != 1)
  3302. val |= BIT3;
  3303. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3304. val |= BIT0;
  3305. wr_reg16(info, TCR, val);
  3306. /* RCR (rx control)
  3307. *
  3308. * 15..13 mode, 010=async
  3309. * 12..10 encoding, 000=NRZ
  3310. * 09 parity enable
  3311. * 08 1=odd parity, 0=even parity
  3312. * 07..06 reserved, must be 0
  3313. * 05..04 character length
  3314. * 00=5 bits
  3315. * 01=6 bits
  3316. * 10=7 bits
  3317. * 11=8 bits
  3318. * 03 reserved, must be zero
  3319. * 02 reset
  3320. * 01 enable
  3321. * 00 auto-DCD enable
  3322. */
  3323. val = 0x4000;
  3324. if (info->params.parity != ASYNC_PARITY_NONE) {
  3325. val |= BIT9;
  3326. if (info->params.parity == ASYNC_PARITY_ODD)
  3327. val |= BIT8;
  3328. }
  3329. switch (info->params.data_bits)
  3330. {
  3331. case 6: val |= BIT4; break;
  3332. case 7: val |= BIT5; break;
  3333. case 8: val |= BIT5 + BIT4; break;
  3334. }
  3335. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3336. val |= BIT0;
  3337. wr_reg16(info, RCR, val);
  3338. /* CCR (clock control)
  3339. *
  3340. * 07..05 011 = tx clock source is BRG/16
  3341. * 04..02 010 = rx clock source is BRG
  3342. * 01 0 = auxclk disabled
  3343. * 00 1 = BRG enabled
  3344. *
  3345. * 0110 1001
  3346. */
  3347. wr_reg8(info, CCR, 0x69);
  3348. msc_set_vcr(info);
  3349. /* SCR (serial control)
  3350. *
  3351. * 15 1=tx req on FIFO half empty
  3352. * 14 1=rx req on FIFO half full
  3353. * 13 tx data IRQ enable
  3354. * 12 tx idle IRQ enable
  3355. * 11 rx break on IRQ enable
  3356. * 10 rx data IRQ enable
  3357. * 09 rx break off IRQ enable
  3358. * 08 overrun IRQ enable
  3359. * 07 DSR IRQ enable
  3360. * 06 CTS IRQ enable
  3361. * 05 DCD IRQ enable
  3362. * 04 RI IRQ enable
  3363. * 03 reserved, must be zero
  3364. * 02 1=txd->rxd internal loopback enable
  3365. * 01 reserved, must be zero
  3366. * 00 1=master IRQ enable
  3367. */
  3368. val = BIT15 + BIT14 + BIT0;
  3369. wr_reg16(info, SCR, val);
  3370. slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
  3371. set_rate(info, info->params.data_rate * 16);
  3372. if (info->params.loopback)
  3373. enable_loopback(info);
  3374. }
  3375. static void sync_mode(struct slgt_info *info)
  3376. {
  3377. unsigned short val;
  3378. slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
  3379. tx_stop(info);
  3380. rx_stop(info);
  3381. /* TCR (tx control)
  3382. *
  3383. * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
  3384. * 12..10 encoding
  3385. * 09 CRC enable
  3386. * 08 CRC32
  3387. * 07 1=RTS driver control
  3388. * 06 preamble enable
  3389. * 05..04 preamble length
  3390. * 03 share open/close flag
  3391. * 02 reset
  3392. * 01 enable
  3393. * 00 auto-CTS enable
  3394. */
  3395. val = 0;
  3396. switch(info->params.mode) {
  3397. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3398. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3399. case MGSL_MODE_RAW: val |= BIT13; break;
  3400. }
  3401. if (info->if_mode & MGSL_INTERFACE_RTS_EN)
  3402. val |= BIT7;
  3403. switch(info->params.encoding)
  3404. {
  3405. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3406. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3407. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3408. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3409. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3410. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3411. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3412. }
  3413. switch (info->params.crc_type & HDLC_CRC_MASK)
  3414. {
  3415. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3416. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3417. }
  3418. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  3419. val |= BIT6;
  3420. switch (info->params.preamble_length)
  3421. {
  3422. case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
  3423. case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
  3424. case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
  3425. }
  3426. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3427. val |= BIT0;
  3428. wr_reg16(info, TCR, val);
  3429. /* TPR (transmit preamble) */
  3430. switch (info->params.preamble)
  3431. {
  3432. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  3433. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  3434. case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
  3435. case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
  3436. case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
  3437. default: val = 0x7e; break;
  3438. }
  3439. wr_reg8(info, TPR, (unsigned char)val);
  3440. /* RCR (rx control)
  3441. *
  3442. * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
  3443. * 12..10 encoding
  3444. * 09 CRC enable
  3445. * 08 CRC32
  3446. * 07..03 reserved, must be 0
  3447. * 02 reset
  3448. * 01 enable
  3449. * 00 auto-DCD enable
  3450. */
  3451. val = 0;
  3452. switch(info->params.mode) {
  3453. case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
  3454. case MGSL_MODE_BISYNC: val |= BIT15; break;
  3455. case MGSL_MODE_RAW: val |= BIT13; break;
  3456. }
  3457. switch(info->params.encoding)
  3458. {
  3459. case HDLC_ENCODING_NRZB: val |= BIT10; break;
  3460. case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
  3461. case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
  3462. case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
  3463. case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
  3464. case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
  3465. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
  3466. }
  3467. switch (info->params.crc_type & HDLC_CRC_MASK)
  3468. {
  3469. case HDLC_CRC_16_CCITT: val |= BIT9; break;
  3470. case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
  3471. }
  3472. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3473. val |= BIT0;
  3474. wr_reg16(info, RCR, val);
  3475. /* CCR (clock control)
  3476. *
  3477. * 07..05 tx clock source
  3478. * 04..02 rx clock source
  3479. * 01 auxclk enable
  3480. * 00 BRG enable
  3481. */
  3482. val = 0;
  3483. if (info->params.flags & HDLC_FLAG_TXC_BRG)
  3484. {
  3485. // when RxC source is DPLL, BRG generates 16X DPLL
  3486. // reference clock, so take TxC from BRG/16 to get
  3487. // transmit clock at actual data rate
  3488. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3489. val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
  3490. else
  3491. val |= BIT6; /* 010, txclk = BRG */
  3492. }
  3493. else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
  3494. val |= BIT7; /* 100, txclk = DPLL Input */
  3495. else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
  3496. val |= BIT5; /* 001, txclk = RXC Input */
  3497. if (info->params.flags & HDLC_FLAG_RXC_BRG)
  3498. val |= BIT3; /* 010, rxclk = BRG */
  3499. else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  3500. val |= BIT4; /* 100, rxclk = DPLL */
  3501. else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
  3502. val |= BIT2; /* 001, rxclk = TXC Input */
  3503. if (info->params.clock_speed)
  3504. val |= BIT1 + BIT0;
  3505. wr_reg8(info, CCR, (unsigned char)val);
  3506. if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
  3507. {
  3508. // program DPLL mode
  3509. switch(info->params.encoding)
  3510. {
  3511. case HDLC_ENCODING_BIPHASE_MARK:
  3512. case HDLC_ENCODING_BIPHASE_SPACE:
  3513. val = BIT7; break;
  3514. case HDLC_ENCODING_BIPHASE_LEVEL:
  3515. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
  3516. val = BIT7 + BIT6; break;
  3517. default: val = BIT6; // NRZ encodings
  3518. }
  3519. wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
  3520. // DPLL requires a 16X reference clock from BRG
  3521. set_rate(info, info->params.clock_speed * 16);
  3522. }
  3523. else
  3524. set_rate(info, info->params.clock_speed);
  3525. tx_set_idle(info);
  3526. msc_set_vcr(info);
  3527. /* SCR (serial control)
  3528. *
  3529. * 15 1=tx req on FIFO half empty
  3530. * 14 1=rx req on FIFO half full
  3531. * 13 tx data IRQ enable
  3532. * 12 tx idle IRQ enable
  3533. * 11 underrun IRQ enable
  3534. * 10 rx data IRQ enable
  3535. * 09 rx idle IRQ enable
  3536. * 08 overrun IRQ enable
  3537. * 07 DSR IRQ enable
  3538. * 06 CTS IRQ enable
  3539. * 05 DCD IRQ enable
  3540. * 04 RI IRQ enable
  3541. * 03 reserved, must be zero
  3542. * 02 1=txd->rxd internal loopback enable
  3543. * 01 reserved, must be zero
  3544. * 00 1=master IRQ enable
  3545. */
  3546. wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
  3547. if (info->params.loopback)
  3548. enable_loopback(info);
  3549. }
  3550. /*
  3551. * set transmit idle mode
  3552. */
  3553. static void tx_set_idle(struct slgt_info *info)
  3554. {
  3555. unsigned char val;
  3556. unsigned short tcr;
  3557. /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
  3558. * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
  3559. */
  3560. tcr = rd_reg16(info, TCR);
  3561. if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
  3562. /* disable preamble, set idle size to 16 bits */
  3563. tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
  3564. /* MSB of 16 bit idle specified in tx preamble register (TPR) */
  3565. wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
  3566. } else if (!(tcr & BIT6)) {
  3567. /* preamble is disabled, set idle size to 8 bits */
  3568. tcr &= ~(BIT5 + BIT4);
  3569. }
  3570. wr_reg16(info, TCR, tcr);
  3571. if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
  3572. /* LSB of custom tx idle specified in tx idle register */
  3573. val = (unsigned char)(info->idle_mode & 0xff);
  3574. } else {
  3575. /* standard 8 bit idle patterns */
  3576. switch(info->idle_mode)
  3577. {
  3578. case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
  3579. case HDLC_TXIDLE_ALT_ZEROS_ONES:
  3580. case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
  3581. case HDLC_TXIDLE_ZEROS:
  3582. case HDLC_TXIDLE_SPACE: val = 0x00; break;
  3583. default: val = 0xff;
  3584. }
  3585. }
  3586. wr_reg8(info, TIR, val);
  3587. }
  3588. /*
  3589. * get state of V24 status (input) signals
  3590. */
  3591. static void get_signals(struct slgt_info *info)
  3592. {
  3593. unsigned short status = rd_reg16(info, SSR);
  3594. /* clear all serial signals except DTR and RTS */
  3595. info->signals &= SerialSignal_DTR + SerialSignal_RTS;
  3596. if (status & BIT3)
  3597. info->signals |= SerialSignal_DSR;
  3598. if (status & BIT2)
  3599. info->signals |= SerialSignal_CTS;
  3600. if (status & BIT1)
  3601. info->signals |= SerialSignal_DCD;
  3602. if (status & BIT0)
  3603. info->signals |= SerialSignal_RI;
  3604. }
  3605. /*
  3606. * set V.24 Control Register based on current configuration
  3607. */
  3608. static void msc_set_vcr(struct slgt_info *info)
  3609. {
  3610. unsigned char val = 0;
  3611. /* VCR (V.24 control)
  3612. *
  3613. * 07..04 serial IF select
  3614. * 03 DTR
  3615. * 02 RTS
  3616. * 01 LL
  3617. * 00 RL
  3618. */
  3619. switch(info->if_mode & MGSL_INTERFACE_MASK)
  3620. {
  3621. case MGSL_INTERFACE_RS232:
  3622. val |= BIT5; /* 0010 */
  3623. break;
  3624. case MGSL_INTERFACE_V35:
  3625. val |= BIT7 + BIT6 + BIT5; /* 1110 */
  3626. break;
  3627. case MGSL_INTERFACE_RS422:
  3628. val |= BIT6; /* 0100 */
  3629. break;
  3630. }
  3631. if (info->signals & SerialSignal_DTR)
  3632. val |= BIT3;
  3633. if (info->signals & SerialSignal_RTS)
  3634. val |= BIT2;
  3635. if (info->if_mode & MGSL_INTERFACE_LL)
  3636. val |= BIT1;
  3637. if (info->if_mode & MGSL_INTERFACE_RL)
  3638. val |= BIT0;
  3639. wr_reg8(info, VCR, val);
  3640. }
  3641. /*
  3642. * set state of V24 control (output) signals
  3643. */
  3644. static void set_signals(struct slgt_info *info)
  3645. {
  3646. unsigned char val = rd_reg8(info, VCR);
  3647. if (info->signals & SerialSignal_DTR)
  3648. val |= BIT3;
  3649. else
  3650. val &= ~BIT3;
  3651. if (info->signals & SerialSignal_RTS)
  3652. val |= BIT2;
  3653. else
  3654. val &= ~BIT2;
  3655. wr_reg8(info, VCR, val);
  3656. }
  3657. /*
  3658. * free range of receive DMA buffers (i to last)
  3659. */
  3660. static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
  3661. {
  3662. int done = 0;
  3663. while(!done) {
  3664. /* reset current buffer for reuse */
  3665. info->rbufs[i].status = 0;
  3666. switch(info->params.mode) {
  3667. case MGSL_MODE_RAW:
  3668. case MGSL_MODE_MONOSYNC:
  3669. case MGSL_MODE_BISYNC:
  3670. set_desc_count(info->rbufs[i], info->raw_rx_size);
  3671. break;
  3672. default:
  3673. set_desc_count(info->rbufs[i], DMABUFSIZE);
  3674. }
  3675. if (i == last)
  3676. done = 1;
  3677. if (++i == info->rbuf_count)
  3678. i = 0;
  3679. }
  3680. info->rbuf_current = i;
  3681. }
  3682. /*
  3683. * mark all receive DMA buffers as free
  3684. */
  3685. static void reset_rbufs(struct slgt_info *info)
  3686. {
  3687. free_rbufs(info, 0, info->rbuf_count - 1);
  3688. }
  3689. /*
  3690. * pass receive HDLC frame to upper layer
  3691. *
  3692. * return 1 if frame available, otherwise 0
  3693. */
  3694. static int rx_get_frame(struct slgt_info *info)
  3695. {
  3696. unsigned int start, end;
  3697. unsigned short status;
  3698. unsigned int framesize = 0;
  3699. int rc = 0;
  3700. unsigned long flags;
  3701. struct tty_struct *tty = info->tty;
  3702. unsigned char addr_field = 0xff;
  3703. unsigned int crc_size = 0;
  3704. switch (info->params.crc_type & HDLC_CRC_MASK) {
  3705. case HDLC_CRC_16_CCITT: crc_size = 2; break;
  3706. case HDLC_CRC_32_CCITT: crc_size = 4; break;
  3707. }
  3708. check_again:
  3709. framesize = 0;
  3710. addr_field = 0xff;
  3711. start = end = info->rbuf_current;
  3712. for (;;) {
  3713. if (!desc_complete(info->rbufs[end]))
  3714. goto cleanup;
  3715. if (framesize == 0 && info->params.addr_filter != 0xff)
  3716. addr_field = info->rbufs[end].buf[0];
  3717. framesize += desc_count(info->rbufs[end]);
  3718. if (desc_eof(info->rbufs[end]))
  3719. break;
  3720. if (++end == info->rbuf_count)
  3721. end = 0;
  3722. if (end == info->rbuf_current) {
  3723. if (info->rx_enabled){
  3724. spin_lock_irqsave(&info->lock,flags);
  3725. rx_start(info);
  3726. spin_unlock_irqrestore(&info->lock,flags);
  3727. }
  3728. goto cleanup;
  3729. }
  3730. }
  3731. /* status
  3732. *
  3733. * 15 buffer complete
  3734. * 14..06 reserved
  3735. * 05..04 residue
  3736. * 02 eof (end of frame)
  3737. * 01 CRC error
  3738. * 00 abort
  3739. */
  3740. status = desc_status(info->rbufs[end]);
  3741. /* ignore CRC bit if not using CRC (bit is undefined) */
  3742. if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
  3743. status &= ~BIT1;
  3744. if (framesize == 0 ||
  3745. (addr_field != 0xff && addr_field != info->params.addr_filter)) {
  3746. free_rbufs(info, start, end);
  3747. goto check_again;
  3748. }
  3749. if (framesize < (2 + crc_size) || status & BIT0) {
  3750. info->icount.rxshort++;
  3751. framesize = 0;
  3752. } else if (status & BIT1) {
  3753. info->icount.rxcrc++;
  3754. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
  3755. framesize = 0;
  3756. }
  3757. #if SYNCLINK_GENERIC_HDLC
  3758. if (framesize == 0) {
  3759. struct net_device_stats *stats = hdlc_stats(info->netdev);
  3760. stats->rx_errors++;
  3761. stats->rx_frame_errors++;
  3762. }
  3763. #endif
  3764. DBGBH(("%s rx frame status=%04X size=%d\n",
  3765. info->device_name, status, framesize));
  3766. DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
  3767. if (framesize) {
  3768. if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
  3769. framesize -= crc_size;
  3770. crc_size = 0;
  3771. }
  3772. if (framesize > info->max_frame_size + crc_size)
  3773. info->icount.rxlong++;
  3774. else {
  3775. /* copy dma buffer(s) to contiguous temp buffer */
  3776. int copy_count = framesize;
  3777. int i = start;
  3778. unsigned char *p = info->tmp_rbuf;
  3779. info->tmp_rbuf_count = framesize;
  3780. info->icount.rxok++;
  3781. while(copy_count) {
  3782. int partial_count = min(copy_count, DMABUFSIZE);
  3783. memcpy(p, info->rbufs[i].buf, partial_count);
  3784. p += partial_count;
  3785. copy_count -= partial_count;
  3786. if (++i == info->rbuf_count)
  3787. i = 0;
  3788. }
  3789. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3790. *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
  3791. framesize++;
  3792. }
  3793. #if SYNCLINK_GENERIC_HDLC
  3794. if (info->netcount)
  3795. hdlcdev_rx(info,info->tmp_rbuf, framesize);
  3796. else
  3797. #endif
  3798. ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
  3799. }
  3800. }
  3801. free_rbufs(info, start, end);
  3802. rc = 1;
  3803. cleanup:
  3804. return rc;
  3805. }
  3806. /*
  3807. * pass receive buffer (RAW synchronous mode) to tty layer
  3808. * return 1 if buffer available, otherwise 0
  3809. */
  3810. static int rx_get_buf(struct slgt_info *info)
  3811. {
  3812. unsigned int i = info->rbuf_current;
  3813. unsigned int count;
  3814. if (!desc_complete(info->rbufs[i]))
  3815. return 0;
  3816. count = desc_count(info->rbufs[i]);
  3817. switch(info->params.mode) {
  3818. case MGSL_MODE_MONOSYNC:
  3819. case MGSL_MODE_BISYNC:
  3820. /* ignore residue in byte synchronous modes */
  3821. if (desc_residue(info->rbufs[i]))
  3822. count--;
  3823. break;
  3824. }
  3825. DBGDATA(info, info->rbufs[i].buf, count, "rx");
  3826. DBGINFO(("rx_get_buf size=%d\n", count));
  3827. if (count)
  3828. ldisc_receive_buf(info->tty, info->rbufs[i].buf,
  3829. info->flag_buf, count);
  3830. free_rbufs(info, i, i);
  3831. return 1;
  3832. }
  3833. static void reset_tbufs(struct slgt_info *info)
  3834. {
  3835. unsigned int i;
  3836. info->tbuf_current = 0;
  3837. for (i=0 ; i < info->tbuf_count ; i++) {
  3838. info->tbufs[i].status = 0;
  3839. info->tbufs[i].count = 0;
  3840. }
  3841. }
  3842. /*
  3843. * return number of free transmit DMA buffers
  3844. */
  3845. static unsigned int free_tbuf_count(struct slgt_info *info)
  3846. {
  3847. unsigned int count = 0;
  3848. unsigned int i = info->tbuf_current;
  3849. do
  3850. {
  3851. if (desc_count(info->tbufs[i]))
  3852. break; /* buffer in use */
  3853. ++count;
  3854. if (++i == info->tbuf_count)
  3855. i=0;
  3856. } while (i != info->tbuf_current);
  3857. /* last buffer with zero count may be in use, assume it is */
  3858. if (count)
  3859. --count;
  3860. return count;
  3861. }
  3862. /*
  3863. * load transmit DMA buffer(s) with data
  3864. */
  3865. static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
  3866. {
  3867. unsigned short count;
  3868. unsigned int i;
  3869. struct slgt_desc *d;
  3870. if (size == 0)
  3871. return;
  3872. DBGDATA(info, buf, size, "tx");
  3873. info->tbuf_start = i = info->tbuf_current;
  3874. while (size) {
  3875. d = &info->tbufs[i];
  3876. if (++i == info->tbuf_count)
  3877. i = 0;
  3878. count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
  3879. memcpy(d->buf, buf, count);
  3880. size -= count;
  3881. buf += count;
  3882. /*
  3883. * set EOF bit for last buffer of HDLC frame or
  3884. * for every buffer in raw mode
  3885. */
  3886. if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
  3887. info->params.mode == MGSL_MODE_RAW)
  3888. set_desc_eof(*d, 1);
  3889. else
  3890. set_desc_eof(*d, 0);
  3891. set_desc_count(*d, count);
  3892. }
  3893. info->tbuf_current = i;
  3894. }
  3895. static int register_test(struct slgt_info *info)
  3896. {
  3897. static unsigned short patterns[] =
  3898. {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
  3899. static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
  3900. unsigned int i;
  3901. int rc = 0;
  3902. for (i=0 ; i < count ; i++) {
  3903. wr_reg16(info, TIR, patterns[i]);
  3904. wr_reg16(info, BDR, patterns[(i+1)%count]);
  3905. if ((rd_reg16(info, TIR) != patterns[i]) ||
  3906. (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
  3907. rc = -ENODEV;
  3908. break;
  3909. }
  3910. }
  3911. info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
  3912. info->init_error = rc ? 0 : DiagStatus_AddressFailure;
  3913. return rc;
  3914. }
  3915. static int irq_test(struct slgt_info *info)
  3916. {
  3917. unsigned long timeout;
  3918. unsigned long flags;
  3919. struct tty_struct *oldtty = info->tty;
  3920. u32 speed = info->params.data_rate;
  3921. info->params.data_rate = 921600;
  3922. info->tty = NULL;
  3923. spin_lock_irqsave(&info->lock, flags);
  3924. async_mode(info);
  3925. slgt_irq_on(info, IRQ_TXIDLE);
  3926. /* enable transmitter */
  3927. wr_reg16(info, TCR,
  3928. (unsigned short)(rd_reg16(info, TCR) | BIT1));
  3929. /* write one byte and wait for tx idle */
  3930. wr_reg16(info, TDR, 0);
  3931. /* assume failure */
  3932. info->init_error = DiagStatus_IrqFailure;
  3933. info->irq_occurred = FALSE;
  3934. spin_unlock_irqrestore(&info->lock, flags);
  3935. timeout=100;
  3936. while(timeout-- && !info->irq_occurred)
  3937. msleep_interruptible(10);
  3938. spin_lock_irqsave(&info->lock,flags);
  3939. reset_port(info);
  3940. spin_unlock_irqrestore(&info->lock,flags);
  3941. info->params.data_rate = speed;
  3942. info->tty = oldtty;
  3943. info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
  3944. return info->irq_occurred ? 0 : -ENODEV;
  3945. }
  3946. static int loopback_test_rx(struct slgt_info *info)
  3947. {
  3948. unsigned char *src, *dest;
  3949. int count;
  3950. if (desc_complete(info->rbufs[0])) {
  3951. count = desc_count(info->rbufs[0]);
  3952. src = info->rbufs[0].buf;
  3953. dest = info->tmp_rbuf;
  3954. for( ; count ; count-=2, src+=2) {
  3955. /* src=data byte (src+1)=status byte */
  3956. if (!(*(src+1) & (BIT9 + BIT8))) {
  3957. *dest = *src;
  3958. dest++;
  3959. info->tmp_rbuf_count++;
  3960. }
  3961. }
  3962. DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
  3963. return 1;
  3964. }
  3965. return 0;
  3966. }
  3967. static int loopback_test(struct slgt_info *info)
  3968. {
  3969. #define TESTFRAMESIZE 20
  3970. unsigned long timeout;
  3971. u16 count = TESTFRAMESIZE;
  3972. unsigned char buf[TESTFRAMESIZE];
  3973. int rc = -ENODEV;
  3974. unsigned long flags;
  3975. struct tty_struct *oldtty = info->tty;
  3976. MGSL_PARAMS params;
  3977. memcpy(&params, &info->params, sizeof(params));
  3978. info->params.mode = MGSL_MODE_ASYNC;
  3979. info->params.data_rate = 921600;
  3980. info->params.loopback = 1;
  3981. info->tty = NULL;
  3982. /* build and send transmit frame */
  3983. for (count = 0; count < TESTFRAMESIZE; ++count)
  3984. buf[count] = (unsigned char)count;
  3985. info->tmp_rbuf_count = 0;
  3986. memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
  3987. /* program hardware for HDLC and enabled receiver */
  3988. spin_lock_irqsave(&info->lock,flags);
  3989. async_mode(info);
  3990. rx_start(info);
  3991. info->tx_count = count;
  3992. tx_load(info, buf, count);
  3993. tx_start(info);
  3994. spin_unlock_irqrestore(&info->lock, flags);
  3995. /* wait for receive complete */
  3996. for (timeout = 100; timeout; --timeout) {
  3997. msleep_interruptible(10);
  3998. if (loopback_test_rx(info)) {
  3999. rc = 0;
  4000. break;
  4001. }
  4002. }
  4003. /* verify received frame length and contents */
  4004. if (!rc && (info->tmp_rbuf_count != count ||
  4005. memcmp(buf, info->tmp_rbuf, count))) {
  4006. rc = -ENODEV;
  4007. }
  4008. spin_lock_irqsave(&info->lock,flags);
  4009. reset_adapter(info);
  4010. spin_unlock_irqrestore(&info->lock,flags);
  4011. memcpy(&info->params, &params, sizeof(info->params));
  4012. info->tty = oldtty;
  4013. info->init_error = rc ? DiagStatus_DmaFailure : 0;
  4014. return rc;
  4015. }
  4016. static int adapter_test(struct slgt_info *info)
  4017. {
  4018. DBGINFO(("testing %s\n", info->device_name));
  4019. if (register_test(info) < 0) {
  4020. printk("register test failure %s addr=%08X\n",
  4021. info->device_name, info->phys_reg_addr);
  4022. } else if (irq_test(info) < 0) {
  4023. printk("IRQ test failure %s IRQ=%d\n",
  4024. info->device_name, info->irq_level);
  4025. } else if (loopback_test(info) < 0) {
  4026. printk("loopback test failure %s\n", info->device_name);
  4027. }
  4028. return info->init_error;
  4029. }
  4030. /*
  4031. * transmit timeout handler
  4032. */
  4033. static void tx_timeout(unsigned long context)
  4034. {
  4035. struct slgt_info *info = (struct slgt_info*)context;
  4036. unsigned long flags;
  4037. DBGINFO(("%s tx_timeout\n", info->device_name));
  4038. if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
  4039. info->icount.txtimeout++;
  4040. }
  4041. spin_lock_irqsave(&info->lock,flags);
  4042. info->tx_active = 0;
  4043. info->tx_count = 0;
  4044. spin_unlock_irqrestore(&info->lock,flags);
  4045. #if SYNCLINK_GENERIC_HDLC
  4046. if (info->netcount)
  4047. hdlcdev_tx_done(info);
  4048. else
  4049. #endif
  4050. bh_transmit(info);
  4051. }
  4052. /*
  4053. * receive buffer polling timer
  4054. */
  4055. static void rx_timeout(unsigned long context)
  4056. {
  4057. struct slgt_info *info = (struct slgt_info*)context;
  4058. unsigned long flags;
  4059. DBGINFO(("%s rx_timeout\n", info->device_name));
  4060. spin_lock_irqsave(&info->lock, flags);
  4061. info->pending_bh |= BH_RECEIVE;
  4062. spin_unlock_irqrestore(&info->lock, flags);
  4063. bh_handler(&info->task);
  4064. }