synclink.c 232 KB

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  1. /*
  2. * linux/drivers/char/synclink.c
  3. *
  4. * $Id: synclink.c,v 1.1.1.1 2007/06/12 07:27:10 eyryu Exp $
  5. *
  6. * Device driver for Microgate SyncLink ISA and PCI
  7. * high speed multiprotocol serial adapters.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  15. *
  16. * Original release 01/11/99
  17. *
  18. * This code is released under the GNU General Public License (GPL)
  19. *
  20. * This driver is primarily intended for use in synchronous
  21. * HDLC mode. Asynchronous mode is also provided.
  22. *
  23. * When operating in synchronous mode, each call to mgsl_write()
  24. * contains exactly one complete HDLC frame. Calling mgsl_put_char
  25. * will start assembling an HDLC frame that will not be sent until
  26. * mgsl_flush_chars or mgsl_write is called.
  27. *
  28. * Synchronous receive data is reported as complete frames. To accomplish
  29. * this, the TTY flip buffer is bypassed (too small to hold largest
  30. * frame and may fragment frames) and the line discipline
  31. * receive entry point is called directly.
  32. *
  33. * This driver has been tested with a slightly modified ppp.c driver
  34. * for synchronous PPP.
  35. *
  36. * 2000/02/16
  37. * Added interface for syncppp.c driver (an alternate synchronous PPP
  38. * implementation that also supports Cisco HDLC). Each device instance
  39. * registers as a tty device AND a network device (if dosyncppp option
  40. * is set for the device). The functionality is determined by which
  41. * device interface is opened.
  42. *
  43. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  44. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  45. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  46. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  47. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  48. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  49. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  51. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  52. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  53. * OF THE POSSIBILITY OF SUCH DAMAGE.
  54. */
  55. #if defined(__i386__)
  56. # define BREAKPOINT() asm(" int $3");
  57. #else
  58. # define BREAKPOINT() { }
  59. #endif
  60. #define MAX_ISA_DEVICES 10
  61. #define MAX_PCI_DEVICES 10
  62. #define MAX_TOTAL_DEVICES 20
  63. #include <linux/module.h>
  64. #include <linux/errno.h>
  65. #include <linux/signal.h>
  66. #include <linux/sched.h>
  67. #include <linux/timer.h>
  68. #include <linux/interrupt.h>
  69. #include <linux/pci.h>
  70. #include <linux/tty.h>
  71. #include <linux/tty_flip.h>
  72. #include <linux/serial.h>
  73. #include <linux/major.h>
  74. #include <linux/string.h>
  75. #include <linux/fcntl.h>
  76. #include <linux/ptrace.h>
  77. #include <linux/ioport.h>
  78. #include <linux/mm.h>
  79. #include <linux/slab.h>
  80. #include <linux/delay.h>
  81. #include <linux/netdevice.h>
  82. #include <linux/vmalloc.h>
  83. #include <linux/init.h>
  84. #include <linux/delay.h>
  85. #include <linux/ioctl.h>
  86. #include <asm/system.h>
  87. #include <asm/io.h>
  88. #include <asm/irq.h>
  89. #include <asm/dma.h>
  90. #include <linux/bitops.h>
  91. #include <asm/types.h>
  92. #include <linux/termios.h>
  93. #include <linux/workqueue.h>
  94. #include <linux/hdlc.h>
  95. #include <linux/dma-mapping.h>
  96. #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
  97. #define SYNCLINK_GENERIC_HDLC 1
  98. #else
  99. #define SYNCLINK_GENERIC_HDLC 0
  100. #endif
  101. #define GET_USER(error,value,addr) error = get_user(value,addr)
  102. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  103. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  104. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  105. #include <asm/uaccess.h>
  106. #include "linux/synclink.h"
  107. #define RCLRVALUE 0xffff
  108. static MGSL_PARAMS default_params = {
  109. MGSL_MODE_HDLC, /* unsigned long mode */
  110. 0, /* unsigned char loopback; */
  111. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  112. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  113. 0, /* unsigned long clock_speed; */
  114. 0xff, /* unsigned char addr_filter; */
  115. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  116. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  117. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  118. 9600, /* unsigned long data_rate; */
  119. 8, /* unsigned char data_bits; */
  120. 1, /* unsigned char stop_bits; */
  121. ASYNC_PARITY_NONE /* unsigned char parity; */
  122. };
  123. #define SHARED_MEM_ADDRESS_SIZE 0x40000
  124. #define BUFFERLISTSIZE 4096
  125. #define DMABUFFERSIZE 4096
  126. #define MAXRXFRAMES 7
  127. typedef struct _DMABUFFERENTRY
  128. {
  129. u32 phys_addr; /* 32-bit flat physical address of data buffer */
  130. volatile u16 count; /* buffer size/data count */
  131. volatile u16 status; /* Control/status field */
  132. volatile u16 rcc; /* character count field */
  133. u16 reserved; /* padding required by 16C32 */
  134. u32 link; /* 32-bit flat link to next buffer entry */
  135. char *virt_addr; /* virtual address of data buffer */
  136. u32 phys_entry; /* physical address of this buffer entry */
  137. dma_addr_t dma_addr;
  138. } DMABUFFERENTRY, *DMAPBUFFERENTRY;
  139. /* The queue of BH actions to be performed */
  140. #define BH_RECEIVE 1
  141. #define BH_TRANSMIT 2
  142. #define BH_STATUS 4
  143. #define IO_PIN_SHUTDOWN_LIMIT 100
  144. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  145. struct _input_signal_events {
  146. int ri_up;
  147. int ri_down;
  148. int dsr_up;
  149. int dsr_down;
  150. int dcd_up;
  151. int dcd_down;
  152. int cts_up;
  153. int cts_down;
  154. };
  155. /* transmit holding buffer definitions*/
  156. #define MAX_TX_HOLDING_BUFFERS 5
  157. struct tx_holding_buffer {
  158. int buffer_size;
  159. unsigned char * buffer;
  160. };
  161. /*
  162. * Device instance data structure
  163. */
  164. struct mgsl_struct {
  165. int magic;
  166. int flags;
  167. int count; /* count of opens */
  168. int line;
  169. int hw_version;
  170. unsigned short close_delay;
  171. unsigned short closing_wait; /* time to wait before closing */
  172. struct mgsl_icount icount;
  173. struct tty_struct *tty;
  174. int timeout;
  175. int x_char; /* xon/xoff character */
  176. int blocked_open; /* # of blocked opens */
  177. u16 read_status_mask;
  178. u16 ignore_status_mask;
  179. unsigned char *xmit_buf;
  180. int xmit_head;
  181. int xmit_tail;
  182. int xmit_cnt;
  183. wait_queue_head_t open_wait;
  184. wait_queue_head_t close_wait;
  185. wait_queue_head_t status_event_wait_q;
  186. wait_queue_head_t event_wait_q;
  187. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  188. struct mgsl_struct *next_device; /* device list link */
  189. spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
  190. struct work_struct task; /* task structure for scheduling bh */
  191. u32 EventMask; /* event trigger mask */
  192. u32 RecordedEvents; /* pending events */
  193. u32 max_frame_size; /* as set by device config */
  194. u32 pending_bh;
  195. int bh_running; /* Protection from multiple */
  196. int isr_overflow;
  197. int bh_requested;
  198. int dcd_chkcount; /* check counts to prevent */
  199. int cts_chkcount; /* too many IRQs if a signal */
  200. int dsr_chkcount; /* is floating */
  201. int ri_chkcount;
  202. char *buffer_list; /* virtual address of Rx & Tx buffer lists */
  203. u32 buffer_list_phys;
  204. dma_addr_t buffer_list_dma_addr;
  205. unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
  206. DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
  207. unsigned int current_rx_buffer;
  208. int num_tx_dma_buffers; /* number of tx dma frames required */
  209. int tx_dma_buffers_used;
  210. unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
  211. DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
  212. int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
  213. int current_tx_buffer; /* next tx dma buffer to be loaded */
  214. unsigned char *intermediate_rxbuffer;
  215. int num_tx_holding_buffers; /* number of tx holding buffer allocated */
  216. int get_tx_holding_index; /* next tx holding buffer for adapter to load */
  217. int put_tx_holding_index; /* next tx holding buffer to store user request */
  218. int tx_holding_count; /* number of tx holding buffers waiting */
  219. struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
  220. int rx_enabled;
  221. int rx_overflow;
  222. int rx_rcc_underrun;
  223. int tx_enabled;
  224. int tx_active;
  225. u32 idle_mode;
  226. u16 cmr_value;
  227. u16 tcsr_value;
  228. char device_name[25]; /* device instance name */
  229. unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
  230. unsigned char bus; /* expansion bus number (zero based) */
  231. unsigned char function; /* PCI device number */
  232. unsigned int io_base; /* base I/O address of adapter */
  233. unsigned int io_addr_size; /* size of the I/O address range */
  234. int io_addr_requested; /* nonzero if I/O address requested */
  235. unsigned int irq_level; /* interrupt level */
  236. unsigned long irq_flags;
  237. int irq_requested; /* nonzero if IRQ requested */
  238. unsigned int dma_level; /* DMA channel */
  239. int dma_requested; /* nonzero if dma channel requested */
  240. u16 mbre_bit;
  241. u16 loopback_bits;
  242. u16 usc_idle_mode;
  243. MGSL_PARAMS params; /* communications parameters */
  244. unsigned char serial_signals; /* current serial signal states */
  245. int irq_occurred; /* for diagnostics use */
  246. unsigned int init_error; /* Initialization startup error (DIAGS) */
  247. int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
  248. u32 last_mem_alloc;
  249. unsigned char* memory_base; /* shared memory address (PCI only) */
  250. u32 phys_memory_base;
  251. int shared_mem_requested;
  252. unsigned char* lcr_base; /* local config registers (PCI only) */
  253. u32 phys_lcr_base;
  254. u32 lcr_offset;
  255. int lcr_mem_requested;
  256. u32 misc_ctrl_value;
  257. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  258. char char_buf[MAX_ASYNC_BUFFER_SIZE];
  259. BOOLEAN drop_rts_on_tx_done;
  260. BOOLEAN loopmode_insert_requested;
  261. BOOLEAN loopmode_send_done_requested;
  262. struct _input_signal_events input_signal_events;
  263. /* generic HDLC device parts */
  264. int netcount;
  265. int dosyncppp;
  266. spinlock_t netlock;
  267. #if SYNCLINK_GENERIC_HDLC
  268. struct net_device *netdev;
  269. #endif
  270. };
  271. #define MGSL_MAGIC 0x5401
  272. /*
  273. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  274. */
  275. #ifndef SERIAL_XMIT_SIZE
  276. #define SERIAL_XMIT_SIZE 4096
  277. #endif
  278. /*
  279. * These macros define the offsets used in calculating the
  280. * I/O address of the specified USC registers.
  281. */
  282. #define DCPIN 2 /* Bit 1 of I/O address */
  283. #define SDPIN 4 /* Bit 2 of I/O address */
  284. #define DCAR 0 /* DMA command/address register */
  285. #define CCAR SDPIN /* channel command/address register */
  286. #define DATAREG DCPIN + SDPIN /* serial data register */
  287. #define MSBONLY 0x41
  288. #define LSBONLY 0x40
  289. /*
  290. * These macros define the register address (ordinal number)
  291. * used for writing address/value pairs to the USC.
  292. */
  293. #define CMR 0x02 /* Channel mode Register */
  294. #define CCSR 0x04 /* Channel Command/status Register */
  295. #define CCR 0x06 /* Channel Control Register */
  296. #define PSR 0x08 /* Port status Register */
  297. #define PCR 0x0a /* Port Control Register */
  298. #define TMDR 0x0c /* Test mode Data Register */
  299. #define TMCR 0x0e /* Test mode Control Register */
  300. #define CMCR 0x10 /* Clock mode Control Register */
  301. #define HCR 0x12 /* Hardware Configuration Register */
  302. #define IVR 0x14 /* Interrupt Vector Register */
  303. #define IOCR 0x16 /* Input/Output Control Register */
  304. #define ICR 0x18 /* Interrupt Control Register */
  305. #define DCCR 0x1a /* Daisy Chain Control Register */
  306. #define MISR 0x1c /* Misc Interrupt status Register */
  307. #define SICR 0x1e /* status Interrupt Control Register */
  308. #define RDR 0x20 /* Receive Data Register */
  309. #define RMR 0x22 /* Receive mode Register */
  310. #define RCSR 0x24 /* Receive Command/status Register */
  311. #define RICR 0x26 /* Receive Interrupt Control Register */
  312. #define RSR 0x28 /* Receive Sync Register */
  313. #define RCLR 0x2a /* Receive count Limit Register */
  314. #define RCCR 0x2c /* Receive Character count Register */
  315. #define TC0R 0x2e /* Time Constant 0 Register */
  316. #define TDR 0x30 /* Transmit Data Register */
  317. #define TMR 0x32 /* Transmit mode Register */
  318. #define TCSR 0x34 /* Transmit Command/status Register */
  319. #define TICR 0x36 /* Transmit Interrupt Control Register */
  320. #define TSR 0x38 /* Transmit Sync Register */
  321. #define TCLR 0x3a /* Transmit count Limit Register */
  322. #define TCCR 0x3c /* Transmit Character count Register */
  323. #define TC1R 0x3e /* Time Constant 1 Register */
  324. /*
  325. * MACRO DEFINITIONS FOR DMA REGISTERS
  326. */
  327. #define DCR 0x06 /* DMA Control Register (shared) */
  328. #define DACR 0x08 /* DMA Array count Register (shared) */
  329. #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
  330. #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
  331. #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
  332. #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
  333. #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
  334. #define TDMR 0x02 /* Transmit DMA mode Register */
  335. #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
  336. #define TBCR 0x2a /* Transmit Byte count Register */
  337. #define TARL 0x2c /* Transmit Address Register (low) */
  338. #define TARU 0x2e /* Transmit Address Register (high) */
  339. #define NTBCR 0x3a /* Next Transmit Byte count Register */
  340. #define NTARL 0x3c /* Next Transmit Address Register (low) */
  341. #define NTARU 0x3e /* Next Transmit Address Register (high) */
  342. #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
  343. #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
  344. #define RBCR 0xaa /* Receive Byte count Register */
  345. #define RARL 0xac /* Receive Address Register (low) */
  346. #define RARU 0xae /* Receive Address Register (high) */
  347. #define NRBCR 0xba /* Next Receive Byte count Register */
  348. #define NRARL 0xbc /* Next Receive Address Register (low) */
  349. #define NRARU 0xbe /* Next Receive Address Register (high) */
  350. /*
  351. * MACRO DEFINITIONS FOR MODEM STATUS BITS
  352. */
  353. #define MODEMSTATUS_DTR 0x80
  354. #define MODEMSTATUS_DSR 0x40
  355. #define MODEMSTATUS_RTS 0x20
  356. #define MODEMSTATUS_CTS 0x10
  357. #define MODEMSTATUS_RI 0x04
  358. #define MODEMSTATUS_DCD 0x01
  359. /*
  360. * Channel Command/Address Register (CCAR) Command Codes
  361. */
  362. #define RTCmd_Null 0x0000
  363. #define RTCmd_ResetHighestIus 0x1000
  364. #define RTCmd_TriggerChannelLoadDma 0x2000
  365. #define RTCmd_TriggerRxDma 0x2800
  366. #define RTCmd_TriggerTxDma 0x3000
  367. #define RTCmd_TriggerRxAndTxDma 0x3800
  368. #define RTCmd_PurgeRxFifo 0x4800
  369. #define RTCmd_PurgeTxFifo 0x5000
  370. #define RTCmd_PurgeRxAndTxFifo 0x5800
  371. #define RTCmd_LoadRcc 0x6800
  372. #define RTCmd_LoadTcc 0x7000
  373. #define RTCmd_LoadRccAndTcc 0x7800
  374. #define RTCmd_LoadTC0 0x8800
  375. #define RTCmd_LoadTC1 0x9000
  376. #define RTCmd_LoadTC0AndTC1 0x9800
  377. #define RTCmd_SerialDataLSBFirst 0xa000
  378. #define RTCmd_SerialDataMSBFirst 0xa800
  379. #define RTCmd_SelectBigEndian 0xb000
  380. #define RTCmd_SelectLittleEndian 0xb800
  381. /*
  382. * DMA Command/Address Register (DCAR) Command Codes
  383. */
  384. #define DmaCmd_Null 0x0000
  385. #define DmaCmd_ResetTxChannel 0x1000
  386. #define DmaCmd_ResetRxChannel 0x1200
  387. #define DmaCmd_StartTxChannel 0x2000
  388. #define DmaCmd_StartRxChannel 0x2200
  389. #define DmaCmd_ContinueTxChannel 0x3000
  390. #define DmaCmd_ContinueRxChannel 0x3200
  391. #define DmaCmd_PauseTxChannel 0x4000
  392. #define DmaCmd_PauseRxChannel 0x4200
  393. #define DmaCmd_AbortTxChannel 0x5000
  394. #define DmaCmd_AbortRxChannel 0x5200
  395. #define DmaCmd_InitTxChannel 0x7000
  396. #define DmaCmd_InitRxChannel 0x7200
  397. #define DmaCmd_ResetHighestDmaIus 0x8000
  398. #define DmaCmd_ResetAllChannels 0x9000
  399. #define DmaCmd_StartAllChannels 0xa000
  400. #define DmaCmd_ContinueAllChannels 0xb000
  401. #define DmaCmd_PauseAllChannels 0xc000
  402. #define DmaCmd_AbortAllChannels 0xd000
  403. #define DmaCmd_InitAllChannels 0xf000
  404. #define TCmd_Null 0x0000
  405. #define TCmd_ClearTxCRC 0x2000
  406. #define TCmd_SelectTicrTtsaData 0x4000
  407. #define TCmd_SelectTicrTxFifostatus 0x5000
  408. #define TCmd_SelectTicrIntLevel 0x6000
  409. #define TCmd_SelectTicrdma_level 0x7000
  410. #define TCmd_SendFrame 0x8000
  411. #define TCmd_SendAbort 0x9000
  412. #define TCmd_EnableDleInsertion 0xc000
  413. #define TCmd_DisableDleInsertion 0xd000
  414. #define TCmd_ClearEofEom 0xe000
  415. #define TCmd_SetEofEom 0xf000
  416. #define RCmd_Null 0x0000
  417. #define RCmd_ClearRxCRC 0x2000
  418. #define RCmd_EnterHuntmode 0x3000
  419. #define RCmd_SelectRicrRtsaData 0x4000
  420. #define RCmd_SelectRicrRxFifostatus 0x5000
  421. #define RCmd_SelectRicrIntLevel 0x6000
  422. #define RCmd_SelectRicrdma_level 0x7000
  423. /*
  424. * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
  425. */
  426. #define RECEIVE_STATUS BIT5
  427. #define RECEIVE_DATA BIT4
  428. #define TRANSMIT_STATUS BIT3
  429. #define TRANSMIT_DATA BIT2
  430. #define IO_PIN BIT1
  431. #define MISC BIT0
  432. /*
  433. * Receive status Bits in Receive Command/status Register RCSR
  434. */
  435. #define RXSTATUS_SHORT_FRAME BIT8
  436. #define RXSTATUS_CODE_VIOLATION BIT8
  437. #define RXSTATUS_EXITED_HUNT BIT7
  438. #define RXSTATUS_IDLE_RECEIVED BIT6
  439. #define RXSTATUS_BREAK_RECEIVED BIT5
  440. #define RXSTATUS_ABORT_RECEIVED BIT5
  441. #define RXSTATUS_RXBOUND BIT4
  442. #define RXSTATUS_CRC_ERROR BIT3
  443. #define RXSTATUS_FRAMING_ERROR BIT3
  444. #define RXSTATUS_ABORT BIT2
  445. #define RXSTATUS_PARITY_ERROR BIT2
  446. #define RXSTATUS_OVERRUN BIT1
  447. #define RXSTATUS_DATA_AVAILABLE BIT0
  448. #define RXSTATUS_ALL 0x01f6
  449. #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
  450. /*
  451. * Values for setting transmit idle mode in
  452. * Transmit Control/status Register (TCSR)
  453. */
  454. #define IDLEMODE_FLAGS 0x0000
  455. #define IDLEMODE_ALT_ONE_ZERO 0x0100
  456. #define IDLEMODE_ZERO 0x0200
  457. #define IDLEMODE_ONE 0x0300
  458. #define IDLEMODE_ALT_MARK_SPACE 0x0500
  459. #define IDLEMODE_SPACE 0x0600
  460. #define IDLEMODE_MARK 0x0700
  461. #define IDLEMODE_MASK 0x0700
  462. /*
  463. * IUSC revision identifiers
  464. */
  465. #define IUSC_SL1660 0x4d44
  466. #define IUSC_PRE_SL1660 0x4553
  467. /*
  468. * Transmit status Bits in Transmit Command/status Register (TCSR)
  469. */
  470. #define TCSR_PRESERVE 0x0F00
  471. #define TCSR_UNDERWAIT BIT11
  472. #define TXSTATUS_PREAMBLE_SENT BIT7
  473. #define TXSTATUS_IDLE_SENT BIT6
  474. #define TXSTATUS_ABORT_SENT BIT5
  475. #define TXSTATUS_EOF_SENT BIT4
  476. #define TXSTATUS_EOM_SENT BIT4
  477. #define TXSTATUS_CRC_SENT BIT3
  478. #define TXSTATUS_ALL_SENT BIT2
  479. #define TXSTATUS_UNDERRUN BIT1
  480. #define TXSTATUS_FIFO_EMPTY BIT0
  481. #define TXSTATUS_ALL 0x00fa
  482. #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
  483. #define MISCSTATUS_RXC_LATCHED BIT15
  484. #define MISCSTATUS_RXC BIT14
  485. #define MISCSTATUS_TXC_LATCHED BIT13
  486. #define MISCSTATUS_TXC BIT12
  487. #define MISCSTATUS_RI_LATCHED BIT11
  488. #define MISCSTATUS_RI BIT10
  489. #define MISCSTATUS_DSR_LATCHED BIT9
  490. #define MISCSTATUS_DSR BIT8
  491. #define MISCSTATUS_DCD_LATCHED BIT7
  492. #define MISCSTATUS_DCD BIT6
  493. #define MISCSTATUS_CTS_LATCHED BIT5
  494. #define MISCSTATUS_CTS BIT4
  495. #define MISCSTATUS_RCC_UNDERRUN BIT3
  496. #define MISCSTATUS_DPLL_NO_SYNC BIT2
  497. #define MISCSTATUS_BRG1_ZERO BIT1
  498. #define MISCSTATUS_BRG0_ZERO BIT0
  499. #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
  500. #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
  501. #define SICR_RXC_ACTIVE BIT15
  502. #define SICR_RXC_INACTIVE BIT14
  503. #define SICR_RXC (BIT15+BIT14)
  504. #define SICR_TXC_ACTIVE BIT13
  505. #define SICR_TXC_INACTIVE BIT12
  506. #define SICR_TXC (BIT13+BIT12)
  507. #define SICR_RI_ACTIVE BIT11
  508. #define SICR_RI_INACTIVE BIT10
  509. #define SICR_RI (BIT11+BIT10)
  510. #define SICR_DSR_ACTIVE BIT9
  511. #define SICR_DSR_INACTIVE BIT8
  512. #define SICR_DSR (BIT9+BIT8)
  513. #define SICR_DCD_ACTIVE BIT7
  514. #define SICR_DCD_INACTIVE BIT6
  515. #define SICR_DCD (BIT7+BIT6)
  516. #define SICR_CTS_ACTIVE BIT5
  517. #define SICR_CTS_INACTIVE BIT4
  518. #define SICR_CTS (BIT5+BIT4)
  519. #define SICR_RCC_UNDERFLOW BIT3
  520. #define SICR_DPLL_NO_SYNC BIT2
  521. #define SICR_BRG1_ZERO BIT1
  522. #define SICR_BRG0_ZERO BIT0
  523. void usc_DisableMasterIrqBit( struct mgsl_struct *info );
  524. void usc_EnableMasterIrqBit( struct mgsl_struct *info );
  525. void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
  526. void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
  527. void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
  528. #define usc_EnableInterrupts( a, b ) \
  529. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
  530. #define usc_DisableInterrupts( a, b ) \
  531. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
  532. #define usc_EnableMasterIrqBit(a) \
  533. usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
  534. #define usc_DisableMasterIrqBit(a) \
  535. usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
  536. #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
  537. /*
  538. * Transmit status Bits in Transmit Control status Register (TCSR)
  539. * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
  540. */
  541. #define TXSTATUS_PREAMBLE_SENT BIT7
  542. #define TXSTATUS_IDLE_SENT BIT6
  543. #define TXSTATUS_ABORT_SENT BIT5
  544. #define TXSTATUS_EOF BIT4
  545. #define TXSTATUS_CRC_SENT BIT3
  546. #define TXSTATUS_ALL_SENT BIT2
  547. #define TXSTATUS_UNDERRUN BIT1
  548. #define TXSTATUS_FIFO_EMPTY BIT0
  549. #define DICR_MASTER BIT15
  550. #define DICR_TRANSMIT BIT0
  551. #define DICR_RECEIVE BIT1
  552. #define usc_EnableDmaInterrupts(a,b) \
  553. usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
  554. #define usc_DisableDmaInterrupts(a,b) \
  555. usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
  556. #define usc_EnableStatusIrqs(a,b) \
  557. usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
  558. #define usc_DisablestatusIrqs(a,b) \
  559. usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
  560. /* Transmit status Bits in Transmit Control status Register (TCSR) */
  561. /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
  562. #define DISABLE_UNCONDITIONAL 0
  563. #define DISABLE_END_OF_FRAME 1
  564. #define ENABLE_UNCONDITIONAL 2
  565. #define ENABLE_AUTO_CTS 3
  566. #define ENABLE_AUTO_DCD 3
  567. #define usc_EnableTransmitter(a,b) \
  568. usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
  569. #define usc_EnableReceiver(a,b) \
  570. usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
  571. static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
  572. static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
  573. static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
  574. static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
  575. static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
  576. static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
  577. void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
  578. void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
  579. #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
  580. #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
  581. #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
  582. static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
  583. static void usc_start_receiver( struct mgsl_struct *info );
  584. static void usc_stop_receiver( struct mgsl_struct *info );
  585. static void usc_start_transmitter( struct mgsl_struct *info );
  586. static void usc_stop_transmitter( struct mgsl_struct *info );
  587. static void usc_set_txidle( struct mgsl_struct *info );
  588. static void usc_load_txfifo( struct mgsl_struct *info );
  589. static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
  590. static void usc_enable_loopback( struct mgsl_struct *info, int enable );
  591. static void usc_get_serial_signals( struct mgsl_struct *info );
  592. static void usc_set_serial_signals( struct mgsl_struct *info );
  593. static void usc_reset( struct mgsl_struct *info );
  594. static void usc_set_sync_mode( struct mgsl_struct *info );
  595. static void usc_set_sdlc_mode( struct mgsl_struct *info );
  596. static void usc_set_async_mode( struct mgsl_struct *info );
  597. static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
  598. static void usc_loopback_frame( struct mgsl_struct *info );
  599. static void mgsl_tx_timeout(unsigned long context);
  600. static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
  601. static void usc_loopmode_insert_request( struct mgsl_struct * info );
  602. static int usc_loopmode_active( struct mgsl_struct * info);
  603. static void usc_loopmode_send_done( struct mgsl_struct * info );
  604. static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
  605. #if SYNCLINK_GENERIC_HDLC
  606. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  607. static void hdlcdev_tx_done(struct mgsl_struct *info);
  608. static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
  609. static int hdlcdev_init(struct mgsl_struct *info);
  610. static void hdlcdev_exit(struct mgsl_struct *info);
  611. #endif
  612. /*
  613. * Defines a BUS descriptor value for the PCI adapter
  614. * local bus address ranges.
  615. */
  616. #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
  617. (0x00400020 + \
  618. ((WrHold) << 30) + \
  619. ((WrDly) << 28) + \
  620. ((RdDly) << 26) + \
  621. ((Nwdd) << 20) + \
  622. ((Nwad) << 15) + \
  623. ((Nxda) << 13) + \
  624. ((Nrdd) << 11) + \
  625. ((Nrad) << 6) )
  626. static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
  627. /*
  628. * Adapter diagnostic routines
  629. */
  630. static BOOLEAN mgsl_register_test( struct mgsl_struct *info );
  631. static BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
  632. static BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
  633. static BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
  634. static int mgsl_adapter_test( struct mgsl_struct *info );
  635. /*
  636. * device and resource management routines
  637. */
  638. static int mgsl_claim_resources(struct mgsl_struct *info);
  639. static void mgsl_release_resources(struct mgsl_struct *info);
  640. static void mgsl_add_device(struct mgsl_struct *info);
  641. static struct mgsl_struct* mgsl_allocate_device(void);
  642. /*
  643. * DMA buffer manupulation functions.
  644. */
  645. static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
  646. static int mgsl_get_rx_frame( struct mgsl_struct *info );
  647. static int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
  648. static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
  649. static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
  650. static int num_free_tx_dma_buffers(struct mgsl_struct *info);
  651. static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
  652. static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
  653. /*
  654. * DMA and Shared Memory buffer allocation and formatting
  655. */
  656. static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
  657. static void mgsl_free_dma_buffers(struct mgsl_struct *info);
  658. static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
  659. static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
  660. static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
  661. static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
  662. static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
  663. static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
  664. static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
  665. static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
  666. static int load_next_tx_holding_buffer(struct mgsl_struct *info);
  667. static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
  668. /*
  669. * Bottom half interrupt handlers
  670. */
  671. static void mgsl_bh_handler(struct work_struct *work);
  672. static void mgsl_bh_receive(struct mgsl_struct *info);
  673. static void mgsl_bh_transmit(struct mgsl_struct *info);
  674. static void mgsl_bh_status(struct mgsl_struct *info);
  675. /*
  676. * Interrupt handler routines and dispatch table.
  677. */
  678. static void mgsl_isr_null( struct mgsl_struct *info );
  679. static void mgsl_isr_transmit_data( struct mgsl_struct *info );
  680. static void mgsl_isr_receive_data( struct mgsl_struct *info );
  681. static void mgsl_isr_receive_status( struct mgsl_struct *info );
  682. static void mgsl_isr_transmit_status( struct mgsl_struct *info );
  683. static void mgsl_isr_io_pin( struct mgsl_struct *info );
  684. static void mgsl_isr_misc( struct mgsl_struct *info );
  685. static void mgsl_isr_receive_dma( struct mgsl_struct *info );
  686. static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
  687. typedef void (*isr_dispatch_func)(struct mgsl_struct *);
  688. static isr_dispatch_func UscIsrTable[7] =
  689. {
  690. mgsl_isr_null,
  691. mgsl_isr_misc,
  692. mgsl_isr_io_pin,
  693. mgsl_isr_transmit_data,
  694. mgsl_isr_transmit_status,
  695. mgsl_isr_receive_data,
  696. mgsl_isr_receive_status
  697. };
  698. /*
  699. * ioctl call handlers
  700. */
  701. static int tiocmget(struct tty_struct *tty, struct file *file);
  702. static int tiocmset(struct tty_struct *tty, struct file *file,
  703. unsigned int set, unsigned int clear);
  704. static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
  705. __user *user_icount);
  706. static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
  707. static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
  708. static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
  709. static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
  710. static int mgsl_txenable(struct mgsl_struct * info, int enable);
  711. static int mgsl_txabort(struct mgsl_struct * info);
  712. static int mgsl_rxenable(struct mgsl_struct * info, int enable);
  713. static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
  714. static int mgsl_loopmode_send_done( struct mgsl_struct * info );
  715. /* set non-zero on successful registration with PCI subsystem */
  716. static int pci_registered;
  717. /*
  718. * Global linked list of SyncLink devices
  719. */
  720. static struct mgsl_struct *mgsl_device_list;
  721. static int mgsl_device_count;
  722. /*
  723. * Set this param to non-zero to load eax with the
  724. * .text section address and breakpoint on module load.
  725. * This is useful for use with gdb and add-symbol-file command.
  726. */
  727. static int break_on_load;
  728. /*
  729. * Driver major number, defaults to zero to get auto
  730. * assigned major number. May be forced as module parameter.
  731. */
  732. static int ttymajor;
  733. /*
  734. * Array of user specified options for ISA adapters.
  735. */
  736. static int io[MAX_ISA_DEVICES];
  737. static int irq[MAX_ISA_DEVICES];
  738. static int dma[MAX_ISA_DEVICES];
  739. static int debug_level;
  740. static int maxframe[MAX_TOTAL_DEVICES];
  741. static int dosyncppp[MAX_TOTAL_DEVICES];
  742. static int txdmabufs[MAX_TOTAL_DEVICES];
  743. static int txholdbufs[MAX_TOTAL_DEVICES];
  744. module_param(break_on_load, bool, 0);
  745. module_param(ttymajor, int, 0);
  746. module_param_array(io, int, NULL, 0);
  747. module_param_array(irq, int, NULL, 0);
  748. module_param_array(dma, int, NULL, 0);
  749. module_param(debug_level, int, 0);
  750. module_param_array(maxframe, int, NULL, 0);
  751. module_param_array(dosyncppp, int, NULL, 0);
  752. module_param_array(txdmabufs, int, NULL, 0);
  753. module_param_array(txholdbufs, int, NULL, 0);
  754. static char *driver_name = "SyncLink serial driver";
  755. static char *driver_version = "$Revision: 1.1.1.1 $";
  756. static int synclink_init_one (struct pci_dev *dev,
  757. const struct pci_device_id *ent);
  758. static void synclink_remove_one (struct pci_dev *dev);
  759. static struct pci_device_id synclink_pci_tbl[] = {
  760. { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
  761. { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
  762. { 0, }, /* terminate list */
  763. };
  764. MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
  765. MODULE_LICENSE("GPL");
  766. static struct pci_driver synclink_pci_driver = {
  767. .name = "synclink",
  768. .id_table = synclink_pci_tbl,
  769. .probe = synclink_init_one,
  770. .remove = __devexit_p(synclink_remove_one),
  771. };
  772. static struct tty_driver *serial_driver;
  773. /* number of characters left in xmit buffer before we ask for more */
  774. #define WAKEUP_CHARS 256
  775. static void mgsl_change_params(struct mgsl_struct *info);
  776. static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
  777. /*
  778. * 1st function defined in .text section. Calling this function in
  779. * init_module() followed by a breakpoint allows a remote debugger
  780. * (gdb) to get the .text address for the add-symbol-file command.
  781. * This allows remote debugging of dynamically loadable modules.
  782. */
  783. static void* mgsl_get_text_ptr(void)
  784. {
  785. return mgsl_get_text_ptr;
  786. }
  787. static inline int mgsl_paranoia_check(struct mgsl_struct *info,
  788. char *name, const char *routine)
  789. {
  790. #ifdef MGSL_PARANOIA_CHECK
  791. static const char *badmagic =
  792. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  793. static const char *badinfo =
  794. "Warning: null mgsl_struct for (%s) in %s\n";
  795. if (!info) {
  796. printk(badinfo, name, routine);
  797. return 1;
  798. }
  799. if (info->magic != MGSL_MAGIC) {
  800. printk(badmagic, name, routine);
  801. return 1;
  802. }
  803. #else
  804. if (!info)
  805. return 1;
  806. #endif
  807. return 0;
  808. }
  809. /**
  810. * line discipline callback wrappers
  811. *
  812. * The wrappers maintain line discipline references
  813. * while calling into the line discipline.
  814. *
  815. * ldisc_receive_buf - pass receive data to line discipline
  816. */
  817. static void ldisc_receive_buf(struct tty_struct *tty,
  818. const __u8 *data, char *flags, int count)
  819. {
  820. struct tty_ldisc *ld;
  821. if (!tty)
  822. return;
  823. ld = tty_ldisc_ref(tty);
  824. if (ld) {
  825. if (ld->receive_buf)
  826. ld->receive_buf(tty, data, flags, count);
  827. tty_ldisc_deref(ld);
  828. }
  829. }
  830. /* mgsl_stop() throttle (stop) transmitter
  831. *
  832. * Arguments: tty pointer to tty info structure
  833. * Return Value: None
  834. */
  835. static void mgsl_stop(struct tty_struct *tty)
  836. {
  837. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  838. unsigned long flags;
  839. if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
  840. return;
  841. if ( debug_level >= DEBUG_LEVEL_INFO )
  842. printk("mgsl_stop(%s)\n",info->device_name);
  843. spin_lock_irqsave(&info->irq_spinlock,flags);
  844. if (info->tx_enabled)
  845. usc_stop_transmitter(info);
  846. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  847. } /* end of mgsl_stop() */
  848. /* mgsl_start() release (start) transmitter
  849. *
  850. * Arguments: tty pointer to tty info structure
  851. * Return Value: None
  852. */
  853. static void mgsl_start(struct tty_struct *tty)
  854. {
  855. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  856. unsigned long flags;
  857. if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
  858. return;
  859. if ( debug_level >= DEBUG_LEVEL_INFO )
  860. printk("mgsl_start(%s)\n",info->device_name);
  861. spin_lock_irqsave(&info->irq_spinlock,flags);
  862. if (!info->tx_enabled)
  863. usc_start_transmitter(info);
  864. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  865. } /* end of mgsl_start() */
  866. /*
  867. * Bottom half work queue access functions
  868. */
  869. /* mgsl_bh_action() Return next bottom half action to perform.
  870. * Return Value: BH action code or 0 if nothing to do.
  871. */
  872. static int mgsl_bh_action(struct mgsl_struct *info)
  873. {
  874. unsigned long flags;
  875. int rc = 0;
  876. spin_lock_irqsave(&info->irq_spinlock,flags);
  877. if (info->pending_bh & BH_RECEIVE) {
  878. info->pending_bh &= ~BH_RECEIVE;
  879. rc = BH_RECEIVE;
  880. } else if (info->pending_bh & BH_TRANSMIT) {
  881. info->pending_bh &= ~BH_TRANSMIT;
  882. rc = BH_TRANSMIT;
  883. } else if (info->pending_bh & BH_STATUS) {
  884. info->pending_bh &= ~BH_STATUS;
  885. rc = BH_STATUS;
  886. }
  887. if (!rc) {
  888. /* Mark BH routine as complete */
  889. info->bh_running = 0;
  890. info->bh_requested = 0;
  891. }
  892. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  893. return rc;
  894. }
  895. /*
  896. * Perform bottom half processing of work items queued by ISR.
  897. */
  898. static void mgsl_bh_handler(struct work_struct *work)
  899. {
  900. struct mgsl_struct *info =
  901. container_of(work, struct mgsl_struct, task);
  902. int action;
  903. if (!info)
  904. return;
  905. if ( debug_level >= DEBUG_LEVEL_BH )
  906. printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
  907. __FILE__,__LINE__,info->device_name);
  908. info->bh_running = 1;
  909. while((action = mgsl_bh_action(info)) != 0) {
  910. /* Process work item */
  911. if ( debug_level >= DEBUG_LEVEL_BH )
  912. printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
  913. __FILE__,__LINE__,action);
  914. switch (action) {
  915. case BH_RECEIVE:
  916. mgsl_bh_receive(info);
  917. break;
  918. case BH_TRANSMIT:
  919. mgsl_bh_transmit(info);
  920. break;
  921. case BH_STATUS:
  922. mgsl_bh_status(info);
  923. break;
  924. default:
  925. /* unknown work item ID */
  926. printk("Unknown work item ID=%08X!\n", action);
  927. break;
  928. }
  929. }
  930. if ( debug_level >= DEBUG_LEVEL_BH )
  931. printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
  932. __FILE__,__LINE__,info->device_name);
  933. }
  934. static void mgsl_bh_receive(struct mgsl_struct *info)
  935. {
  936. int (*get_rx_frame)(struct mgsl_struct *info) =
  937. (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
  938. if ( debug_level >= DEBUG_LEVEL_BH )
  939. printk( "%s(%d):mgsl_bh_receive(%s)\n",
  940. __FILE__,__LINE__,info->device_name);
  941. do
  942. {
  943. if (info->rx_rcc_underrun) {
  944. unsigned long flags;
  945. spin_lock_irqsave(&info->irq_spinlock,flags);
  946. usc_start_receiver(info);
  947. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  948. return;
  949. }
  950. } while(get_rx_frame(info));
  951. }
  952. static void mgsl_bh_transmit(struct mgsl_struct *info)
  953. {
  954. struct tty_struct *tty = info->tty;
  955. unsigned long flags;
  956. if ( debug_level >= DEBUG_LEVEL_BH )
  957. printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
  958. __FILE__,__LINE__,info->device_name);
  959. if (tty)
  960. tty_wakeup(tty);
  961. /* if transmitter idle and loopmode_send_done_requested
  962. * then start echoing RxD to TxD
  963. */
  964. spin_lock_irqsave(&info->irq_spinlock,flags);
  965. if ( !info->tx_active && info->loopmode_send_done_requested )
  966. usc_loopmode_send_done( info );
  967. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  968. }
  969. static void mgsl_bh_status(struct mgsl_struct *info)
  970. {
  971. if ( debug_level >= DEBUG_LEVEL_BH )
  972. printk( "%s(%d):mgsl_bh_status() entry on %s\n",
  973. __FILE__,__LINE__,info->device_name);
  974. info->ri_chkcount = 0;
  975. info->dsr_chkcount = 0;
  976. info->dcd_chkcount = 0;
  977. info->cts_chkcount = 0;
  978. }
  979. /* mgsl_isr_receive_status()
  980. *
  981. * Service a receive status interrupt. The type of status
  982. * interrupt is indicated by the state of the RCSR.
  983. * This is only used for HDLC mode.
  984. *
  985. * Arguments: info pointer to device instance data
  986. * Return Value: None
  987. */
  988. static void mgsl_isr_receive_status( struct mgsl_struct *info )
  989. {
  990. u16 status = usc_InReg( info, RCSR );
  991. if ( debug_level >= DEBUG_LEVEL_ISR )
  992. printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
  993. __FILE__,__LINE__,status);
  994. if ( (status & RXSTATUS_ABORT_RECEIVED) &&
  995. info->loopmode_insert_requested &&
  996. usc_loopmode_active(info) )
  997. {
  998. ++info->icount.rxabort;
  999. info->loopmode_insert_requested = FALSE;
  1000. /* clear CMR:13 to start echoing RxD to TxD */
  1001. info->cmr_value &= ~BIT13;
  1002. usc_OutReg(info, CMR, info->cmr_value);
  1003. /* disable received abort irq (no longer required) */
  1004. usc_OutReg(info, RICR,
  1005. (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
  1006. }
  1007. if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
  1008. if (status & RXSTATUS_EXITED_HUNT)
  1009. info->icount.exithunt++;
  1010. if (status & RXSTATUS_IDLE_RECEIVED)
  1011. info->icount.rxidle++;
  1012. wake_up_interruptible(&info->event_wait_q);
  1013. }
  1014. if (status & RXSTATUS_OVERRUN){
  1015. info->icount.rxover++;
  1016. usc_process_rxoverrun_sync( info );
  1017. }
  1018. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  1019. usc_UnlatchRxstatusBits( info, status );
  1020. } /* end of mgsl_isr_receive_status() */
  1021. /* mgsl_isr_transmit_status()
  1022. *
  1023. * Service a transmit status interrupt
  1024. * HDLC mode :end of transmit frame
  1025. * Async mode:all data is sent
  1026. * transmit status is indicated by bits in the TCSR.
  1027. *
  1028. * Arguments: info pointer to device instance data
  1029. * Return Value: None
  1030. */
  1031. static void mgsl_isr_transmit_status( struct mgsl_struct *info )
  1032. {
  1033. u16 status = usc_InReg( info, TCSR );
  1034. if ( debug_level >= DEBUG_LEVEL_ISR )
  1035. printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
  1036. __FILE__,__LINE__,status);
  1037. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  1038. usc_UnlatchTxstatusBits( info, status );
  1039. if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
  1040. {
  1041. /* finished sending HDLC abort. This may leave */
  1042. /* the TxFifo with data from the aborted frame */
  1043. /* so purge the TxFifo. Also shutdown the DMA */
  1044. /* channel in case there is data remaining in */
  1045. /* the DMA buffer */
  1046. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  1047. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  1048. }
  1049. if ( status & TXSTATUS_EOF_SENT )
  1050. info->icount.txok++;
  1051. else if ( status & TXSTATUS_UNDERRUN )
  1052. info->icount.txunder++;
  1053. else if ( status & TXSTATUS_ABORT_SENT )
  1054. info->icount.txabort++;
  1055. else
  1056. info->icount.txunder++;
  1057. info->tx_active = 0;
  1058. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1059. del_timer(&info->tx_timer);
  1060. if ( info->drop_rts_on_tx_done ) {
  1061. usc_get_serial_signals( info );
  1062. if ( info->serial_signals & SerialSignal_RTS ) {
  1063. info->serial_signals &= ~SerialSignal_RTS;
  1064. usc_set_serial_signals( info );
  1065. }
  1066. info->drop_rts_on_tx_done = 0;
  1067. }
  1068. #if SYNCLINK_GENERIC_HDLC
  1069. if (info->netcount)
  1070. hdlcdev_tx_done(info);
  1071. else
  1072. #endif
  1073. {
  1074. if (info->tty->stopped || info->tty->hw_stopped) {
  1075. usc_stop_transmitter(info);
  1076. return;
  1077. }
  1078. info->pending_bh |= BH_TRANSMIT;
  1079. }
  1080. } /* end of mgsl_isr_transmit_status() */
  1081. /* mgsl_isr_io_pin()
  1082. *
  1083. * Service an Input/Output pin interrupt. The type of
  1084. * interrupt is indicated by bits in the MISR
  1085. *
  1086. * Arguments: info pointer to device instance data
  1087. * Return Value: None
  1088. */
  1089. static void mgsl_isr_io_pin( struct mgsl_struct *info )
  1090. {
  1091. struct mgsl_icount *icount;
  1092. u16 status = usc_InReg( info, MISR );
  1093. if ( debug_level >= DEBUG_LEVEL_ISR )
  1094. printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
  1095. __FILE__,__LINE__,status);
  1096. usc_ClearIrqPendingBits( info, IO_PIN );
  1097. usc_UnlatchIostatusBits( info, status );
  1098. if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
  1099. MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
  1100. icount = &info->icount;
  1101. /* update input line counters */
  1102. if (status & MISCSTATUS_RI_LATCHED) {
  1103. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1104. usc_DisablestatusIrqs(info,SICR_RI);
  1105. icount->rng++;
  1106. if ( status & MISCSTATUS_RI )
  1107. info->input_signal_events.ri_up++;
  1108. else
  1109. info->input_signal_events.ri_down++;
  1110. }
  1111. if (status & MISCSTATUS_DSR_LATCHED) {
  1112. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1113. usc_DisablestatusIrqs(info,SICR_DSR);
  1114. icount->dsr++;
  1115. if ( status & MISCSTATUS_DSR )
  1116. info->input_signal_events.dsr_up++;
  1117. else
  1118. info->input_signal_events.dsr_down++;
  1119. }
  1120. if (status & MISCSTATUS_DCD_LATCHED) {
  1121. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1122. usc_DisablestatusIrqs(info,SICR_DCD);
  1123. icount->dcd++;
  1124. if (status & MISCSTATUS_DCD) {
  1125. info->input_signal_events.dcd_up++;
  1126. } else
  1127. info->input_signal_events.dcd_down++;
  1128. #if SYNCLINK_GENERIC_HDLC
  1129. if (info->netcount) {
  1130. if (status & MISCSTATUS_DCD)
  1131. netif_carrier_on(info->netdev);
  1132. else
  1133. netif_carrier_off(info->netdev);
  1134. }
  1135. #endif
  1136. }
  1137. if (status & MISCSTATUS_CTS_LATCHED)
  1138. {
  1139. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1140. usc_DisablestatusIrqs(info,SICR_CTS);
  1141. icount->cts++;
  1142. if ( status & MISCSTATUS_CTS )
  1143. info->input_signal_events.cts_up++;
  1144. else
  1145. info->input_signal_events.cts_down++;
  1146. }
  1147. wake_up_interruptible(&info->status_event_wait_q);
  1148. wake_up_interruptible(&info->event_wait_q);
  1149. if ( (info->flags & ASYNC_CHECK_CD) &&
  1150. (status & MISCSTATUS_DCD_LATCHED) ) {
  1151. if ( debug_level >= DEBUG_LEVEL_ISR )
  1152. printk("%s CD now %s...", info->device_name,
  1153. (status & MISCSTATUS_DCD) ? "on" : "off");
  1154. if (status & MISCSTATUS_DCD)
  1155. wake_up_interruptible(&info->open_wait);
  1156. else {
  1157. if ( debug_level >= DEBUG_LEVEL_ISR )
  1158. printk("doing serial hangup...");
  1159. if (info->tty)
  1160. tty_hangup(info->tty);
  1161. }
  1162. }
  1163. if ( (info->flags & ASYNC_CTS_FLOW) &&
  1164. (status & MISCSTATUS_CTS_LATCHED) ) {
  1165. if (info->tty->hw_stopped) {
  1166. if (status & MISCSTATUS_CTS) {
  1167. if ( debug_level >= DEBUG_LEVEL_ISR )
  1168. printk("CTS tx start...");
  1169. if (info->tty)
  1170. info->tty->hw_stopped = 0;
  1171. usc_start_transmitter(info);
  1172. info->pending_bh |= BH_TRANSMIT;
  1173. return;
  1174. }
  1175. } else {
  1176. if (!(status & MISCSTATUS_CTS)) {
  1177. if ( debug_level >= DEBUG_LEVEL_ISR )
  1178. printk("CTS tx stop...");
  1179. if (info->tty)
  1180. info->tty->hw_stopped = 1;
  1181. usc_stop_transmitter(info);
  1182. }
  1183. }
  1184. }
  1185. }
  1186. info->pending_bh |= BH_STATUS;
  1187. /* for diagnostics set IRQ flag */
  1188. if ( status & MISCSTATUS_TXC_LATCHED ){
  1189. usc_OutReg( info, SICR,
  1190. (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
  1191. usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
  1192. info->irq_occurred = 1;
  1193. }
  1194. } /* end of mgsl_isr_io_pin() */
  1195. /* mgsl_isr_transmit_data()
  1196. *
  1197. * Service a transmit data interrupt (async mode only).
  1198. *
  1199. * Arguments: info pointer to device instance data
  1200. * Return Value: None
  1201. */
  1202. static void mgsl_isr_transmit_data( struct mgsl_struct *info )
  1203. {
  1204. if ( debug_level >= DEBUG_LEVEL_ISR )
  1205. printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
  1206. __FILE__,__LINE__,info->xmit_cnt);
  1207. usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
  1208. if (info->tty->stopped || info->tty->hw_stopped) {
  1209. usc_stop_transmitter(info);
  1210. return;
  1211. }
  1212. if ( info->xmit_cnt )
  1213. usc_load_txfifo( info );
  1214. else
  1215. info->tx_active = 0;
  1216. if (info->xmit_cnt < WAKEUP_CHARS)
  1217. info->pending_bh |= BH_TRANSMIT;
  1218. } /* end of mgsl_isr_transmit_data() */
  1219. /* mgsl_isr_receive_data()
  1220. *
  1221. * Service a receive data interrupt. This occurs
  1222. * when operating in asynchronous interrupt transfer mode.
  1223. * The receive data FIFO is flushed to the receive data buffers.
  1224. *
  1225. * Arguments: info pointer to device instance data
  1226. * Return Value: None
  1227. */
  1228. static void mgsl_isr_receive_data( struct mgsl_struct *info )
  1229. {
  1230. int Fifocount;
  1231. u16 status;
  1232. int work = 0;
  1233. unsigned char DataByte;
  1234. struct tty_struct *tty = info->tty;
  1235. struct mgsl_icount *icount = &info->icount;
  1236. if ( debug_level >= DEBUG_LEVEL_ISR )
  1237. printk("%s(%d):mgsl_isr_receive_data\n",
  1238. __FILE__,__LINE__);
  1239. usc_ClearIrqPendingBits( info, RECEIVE_DATA );
  1240. /* select FIFO status for RICR readback */
  1241. usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
  1242. /* clear the Wordstatus bit so that status readback */
  1243. /* only reflects the status of this byte */
  1244. usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
  1245. /* flush the receive FIFO */
  1246. while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
  1247. int flag;
  1248. /* read one byte from RxFIFO */
  1249. outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
  1250. info->io_base + CCAR );
  1251. DataByte = inb( info->io_base + CCAR );
  1252. /* get the status of the received byte */
  1253. status = usc_InReg(info, RCSR);
  1254. if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
  1255. RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
  1256. usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
  1257. icount->rx++;
  1258. flag = 0;
  1259. if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
  1260. RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
  1261. printk("rxerr=%04X\n",status);
  1262. /* update error statistics */
  1263. if ( status & RXSTATUS_BREAK_RECEIVED ) {
  1264. status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
  1265. icount->brk++;
  1266. } else if (status & RXSTATUS_PARITY_ERROR)
  1267. icount->parity++;
  1268. else if (status & RXSTATUS_FRAMING_ERROR)
  1269. icount->frame++;
  1270. else if (status & RXSTATUS_OVERRUN) {
  1271. /* must issue purge fifo cmd before */
  1272. /* 16C32 accepts more receive chars */
  1273. usc_RTCmd(info,RTCmd_PurgeRxFifo);
  1274. icount->overrun++;
  1275. }
  1276. /* discard char if tty control flags say so */
  1277. if (status & info->ignore_status_mask)
  1278. continue;
  1279. status &= info->read_status_mask;
  1280. if (status & RXSTATUS_BREAK_RECEIVED) {
  1281. flag = TTY_BREAK;
  1282. if (info->flags & ASYNC_SAK)
  1283. do_SAK(tty);
  1284. } else if (status & RXSTATUS_PARITY_ERROR)
  1285. flag = TTY_PARITY;
  1286. else if (status & RXSTATUS_FRAMING_ERROR)
  1287. flag = TTY_FRAME;
  1288. } /* end of if (error) */
  1289. tty_insert_flip_char(tty, DataByte, flag);
  1290. if (status & RXSTATUS_OVERRUN) {
  1291. /* Overrun is special, since it's
  1292. * reported immediately, and doesn't
  1293. * affect the current character
  1294. */
  1295. work += tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  1296. }
  1297. }
  1298. if ( debug_level >= DEBUG_LEVEL_ISR ) {
  1299. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  1300. __FILE__,__LINE__,icount->rx,icount->brk,
  1301. icount->parity,icount->frame,icount->overrun);
  1302. }
  1303. if(work)
  1304. tty_flip_buffer_push(tty);
  1305. }
  1306. /* mgsl_isr_misc()
  1307. *
  1308. * Service a miscellaneos interrupt source.
  1309. *
  1310. * Arguments: info pointer to device extension (instance data)
  1311. * Return Value: None
  1312. */
  1313. static void mgsl_isr_misc( struct mgsl_struct *info )
  1314. {
  1315. u16 status = usc_InReg( info, MISR );
  1316. if ( debug_level >= DEBUG_LEVEL_ISR )
  1317. printk("%s(%d):mgsl_isr_misc status=%04X\n",
  1318. __FILE__,__LINE__,status);
  1319. if ((status & MISCSTATUS_RCC_UNDERRUN) &&
  1320. (info->params.mode == MGSL_MODE_HDLC)) {
  1321. /* turn off receiver and rx DMA */
  1322. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  1323. usc_DmaCmd(info, DmaCmd_ResetRxChannel);
  1324. usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
  1325. usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
  1326. usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
  1327. /* schedule BH handler to restart receiver */
  1328. info->pending_bh |= BH_RECEIVE;
  1329. info->rx_rcc_underrun = 1;
  1330. }
  1331. usc_ClearIrqPendingBits( info, MISC );
  1332. usc_UnlatchMiscstatusBits( info, status );
  1333. } /* end of mgsl_isr_misc() */
  1334. /* mgsl_isr_null()
  1335. *
  1336. * Services undefined interrupt vectors from the
  1337. * USC. (hence this function SHOULD never be called)
  1338. *
  1339. * Arguments: info pointer to device extension (instance data)
  1340. * Return Value: None
  1341. */
  1342. static void mgsl_isr_null( struct mgsl_struct *info )
  1343. {
  1344. } /* end of mgsl_isr_null() */
  1345. /* mgsl_isr_receive_dma()
  1346. *
  1347. * Service a receive DMA channel interrupt.
  1348. * For this driver there are two sources of receive DMA interrupts
  1349. * as identified in the Receive DMA mode Register (RDMR):
  1350. *
  1351. * BIT3 EOA/EOL End of List, all receive buffers in receive
  1352. * buffer list have been filled (no more free buffers
  1353. * available). The DMA controller has shut down.
  1354. *
  1355. * BIT2 EOB End of Buffer. This interrupt occurs when a receive
  1356. * DMA buffer is terminated in response to completion
  1357. * of a good frame or a frame with errors. The status
  1358. * of the frame is stored in the buffer entry in the
  1359. * list of receive buffer entries.
  1360. *
  1361. * Arguments: info pointer to device instance data
  1362. * Return Value: None
  1363. */
  1364. static void mgsl_isr_receive_dma( struct mgsl_struct *info )
  1365. {
  1366. u16 status;
  1367. /* clear interrupt pending and IUS bit for Rx DMA IRQ */
  1368. usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
  1369. /* Read the receive DMA status to identify interrupt type. */
  1370. /* This also clears the status bits. */
  1371. status = usc_InDmaReg( info, RDMR );
  1372. if ( debug_level >= DEBUG_LEVEL_ISR )
  1373. printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
  1374. __FILE__,__LINE__,info->device_name,status);
  1375. info->pending_bh |= BH_RECEIVE;
  1376. if ( status & BIT3 ) {
  1377. info->rx_overflow = 1;
  1378. info->icount.buf_overrun++;
  1379. }
  1380. } /* end of mgsl_isr_receive_dma() */
  1381. /* mgsl_isr_transmit_dma()
  1382. *
  1383. * This function services a transmit DMA channel interrupt.
  1384. *
  1385. * For this driver there is one source of transmit DMA interrupts
  1386. * as identified in the Transmit DMA Mode Register (TDMR):
  1387. *
  1388. * BIT2 EOB End of Buffer. This interrupt occurs when a
  1389. * transmit DMA buffer has been emptied.
  1390. *
  1391. * The driver maintains enough transmit DMA buffers to hold at least
  1392. * one max frame size transmit frame. When operating in a buffered
  1393. * transmit mode, there may be enough transmit DMA buffers to hold at
  1394. * least two or more max frame size frames. On an EOB condition,
  1395. * determine if there are any queued transmit buffers and copy into
  1396. * transmit DMA buffers if we have room.
  1397. *
  1398. * Arguments: info pointer to device instance data
  1399. * Return Value: None
  1400. */
  1401. static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
  1402. {
  1403. u16 status;
  1404. /* clear interrupt pending and IUS bit for Tx DMA IRQ */
  1405. usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
  1406. /* Read the transmit DMA status to identify interrupt type. */
  1407. /* This also clears the status bits. */
  1408. status = usc_InDmaReg( info, TDMR );
  1409. if ( debug_level >= DEBUG_LEVEL_ISR )
  1410. printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
  1411. __FILE__,__LINE__,info->device_name,status);
  1412. if ( status & BIT2 ) {
  1413. --info->tx_dma_buffers_used;
  1414. /* if there are transmit frames queued,
  1415. * try to load the next one
  1416. */
  1417. if ( load_next_tx_holding_buffer(info) ) {
  1418. /* if call returns non-zero value, we have
  1419. * at least one free tx holding buffer
  1420. */
  1421. info->pending_bh |= BH_TRANSMIT;
  1422. }
  1423. }
  1424. } /* end of mgsl_isr_transmit_dma() */
  1425. /* mgsl_interrupt()
  1426. *
  1427. * Interrupt service routine entry point.
  1428. *
  1429. * Arguments:
  1430. *
  1431. * irq interrupt number that caused interrupt
  1432. * dev_id device ID supplied during interrupt registration
  1433. *
  1434. * Return Value: None
  1435. */
  1436. static irqreturn_t mgsl_interrupt(int irq, void *dev_id)
  1437. {
  1438. struct mgsl_struct * info;
  1439. u16 UscVector;
  1440. u16 DmaVector;
  1441. if ( debug_level >= DEBUG_LEVEL_ISR )
  1442. printk("%s(%d):mgsl_interrupt(%d)entry.\n",
  1443. __FILE__,__LINE__,irq);
  1444. info = (struct mgsl_struct *)dev_id;
  1445. if (!info)
  1446. return IRQ_NONE;
  1447. spin_lock(&info->irq_spinlock);
  1448. for(;;) {
  1449. /* Read the interrupt vectors from hardware. */
  1450. UscVector = usc_InReg(info, IVR) >> 9;
  1451. DmaVector = usc_InDmaReg(info, DIVR);
  1452. if ( debug_level >= DEBUG_LEVEL_ISR )
  1453. printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
  1454. __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
  1455. if ( !UscVector && !DmaVector )
  1456. break;
  1457. /* Dispatch interrupt vector */
  1458. if ( UscVector )
  1459. (*UscIsrTable[UscVector])(info);
  1460. else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
  1461. mgsl_isr_transmit_dma(info);
  1462. else
  1463. mgsl_isr_receive_dma(info);
  1464. if ( info->isr_overflow ) {
  1465. printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
  1466. __FILE__,__LINE__,info->device_name, irq);
  1467. usc_DisableMasterIrqBit(info);
  1468. usc_DisableDmaInterrupts(info,DICR_MASTER);
  1469. break;
  1470. }
  1471. }
  1472. /* Request bottom half processing if there's something
  1473. * for it to do and the bh is not already running
  1474. */
  1475. if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
  1476. if ( debug_level >= DEBUG_LEVEL_ISR )
  1477. printk("%s(%d):%s queueing bh task.\n",
  1478. __FILE__,__LINE__,info->device_name);
  1479. schedule_work(&info->task);
  1480. info->bh_requested = 1;
  1481. }
  1482. spin_unlock(&info->irq_spinlock);
  1483. if ( debug_level >= DEBUG_LEVEL_ISR )
  1484. printk("%s(%d):mgsl_interrupt(%d)exit.\n",
  1485. __FILE__,__LINE__,irq);
  1486. return IRQ_HANDLED;
  1487. } /* end of mgsl_interrupt() */
  1488. /* startup()
  1489. *
  1490. * Initialize and start device.
  1491. *
  1492. * Arguments: info pointer to device instance data
  1493. * Return Value: 0 if success, otherwise error code
  1494. */
  1495. static int startup(struct mgsl_struct * info)
  1496. {
  1497. int retval = 0;
  1498. if ( debug_level >= DEBUG_LEVEL_INFO )
  1499. printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1500. if (info->flags & ASYNC_INITIALIZED)
  1501. return 0;
  1502. if (!info->xmit_buf) {
  1503. /* allocate a page of memory for a transmit buffer */
  1504. info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1505. if (!info->xmit_buf) {
  1506. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1507. __FILE__,__LINE__,info->device_name);
  1508. return -ENOMEM;
  1509. }
  1510. }
  1511. info->pending_bh = 0;
  1512. memset(&info->icount, 0, sizeof(info->icount));
  1513. setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
  1514. /* Allocate and claim adapter resources */
  1515. retval = mgsl_claim_resources(info);
  1516. /* perform existence check and diagnostics */
  1517. if ( !retval )
  1518. retval = mgsl_adapter_test(info);
  1519. if ( retval ) {
  1520. if (capable(CAP_SYS_ADMIN) && info->tty)
  1521. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1522. mgsl_release_resources(info);
  1523. return retval;
  1524. }
  1525. /* program hardware for current parameters */
  1526. mgsl_change_params(info);
  1527. if (info->tty)
  1528. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  1529. info->flags |= ASYNC_INITIALIZED;
  1530. return 0;
  1531. } /* end of startup() */
  1532. /* shutdown()
  1533. *
  1534. * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
  1535. *
  1536. * Arguments: info pointer to device instance data
  1537. * Return Value: None
  1538. */
  1539. static void shutdown(struct mgsl_struct * info)
  1540. {
  1541. unsigned long flags;
  1542. if (!(info->flags & ASYNC_INITIALIZED))
  1543. return;
  1544. if (debug_level >= DEBUG_LEVEL_INFO)
  1545. printk("%s(%d):mgsl_shutdown(%s)\n",
  1546. __FILE__,__LINE__, info->device_name );
  1547. /* clear status wait queue because status changes */
  1548. /* can't happen after shutting down the hardware */
  1549. wake_up_interruptible(&info->status_event_wait_q);
  1550. wake_up_interruptible(&info->event_wait_q);
  1551. del_timer_sync(&info->tx_timer);
  1552. if (info->xmit_buf) {
  1553. free_page((unsigned long) info->xmit_buf);
  1554. info->xmit_buf = NULL;
  1555. }
  1556. spin_lock_irqsave(&info->irq_spinlock,flags);
  1557. usc_DisableMasterIrqBit(info);
  1558. usc_stop_receiver(info);
  1559. usc_stop_transmitter(info);
  1560. usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
  1561. TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
  1562. usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
  1563. /* Disable DMAEN (Port 7, Bit 14) */
  1564. /* This disconnects the DMA request signal from the ISA bus */
  1565. /* on the ISA adapter. This has no effect for the PCI adapter */
  1566. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
  1567. /* Disable INTEN (Port 6, Bit12) */
  1568. /* This disconnects the IRQ request signal to the ISA bus */
  1569. /* on the ISA adapter. This has no effect for the PCI adapter */
  1570. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
  1571. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  1572. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1573. usc_set_serial_signals(info);
  1574. }
  1575. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1576. mgsl_release_resources(info);
  1577. if (info->tty)
  1578. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1579. info->flags &= ~ASYNC_INITIALIZED;
  1580. } /* end of shutdown() */
  1581. static void mgsl_program_hw(struct mgsl_struct *info)
  1582. {
  1583. unsigned long flags;
  1584. spin_lock_irqsave(&info->irq_spinlock,flags);
  1585. usc_stop_receiver(info);
  1586. usc_stop_transmitter(info);
  1587. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1588. if (info->params.mode == MGSL_MODE_HDLC ||
  1589. info->params.mode == MGSL_MODE_RAW ||
  1590. info->netcount)
  1591. usc_set_sync_mode(info);
  1592. else
  1593. usc_set_async_mode(info);
  1594. usc_set_serial_signals(info);
  1595. info->dcd_chkcount = 0;
  1596. info->cts_chkcount = 0;
  1597. info->ri_chkcount = 0;
  1598. info->dsr_chkcount = 0;
  1599. usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
  1600. usc_EnableInterrupts(info, IO_PIN);
  1601. usc_get_serial_signals(info);
  1602. if (info->netcount || info->tty->termios->c_cflag & CREAD)
  1603. usc_start_receiver(info);
  1604. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1605. }
  1606. /* Reconfigure adapter based on new parameters
  1607. */
  1608. static void mgsl_change_params(struct mgsl_struct *info)
  1609. {
  1610. unsigned cflag;
  1611. int bits_per_char;
  1612. if (!info->tty || !info->tty->termios)
  1613. return;
  1614. if (debug_level >= DEBUG_LEVEL_INFO)
  1615. printk("%s(%d):mgsl_change_params(%s)\n",
  1616. __FILE__,__LINE__, info->device_name );
  1617. cflag = info->tty->termios->c_cflag;
  1618. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1619. /* otherwise assert DTR and RTS */
  1620. if (cflag & CBAUD)
  1621. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1622. else
  1623. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1624. /* byte size and parity */
  1625. switch (cflag & CSIZE) {
  1626. case CS5: info->params.data_bits = 5; break;
  1627. case CS6: info->params.data_bits = 6; break;
  1628. case CS7: info->params.data_bits = 7; break;
  1629. case CS8: info->params.data_bits = 8; break;
  1630. /* Never happens, but GCC is too dumb to figure it out */
  1631. default: info->params.data_bits = 7; break;
  1632. }
  1633. if (cflag & CSTOPB)
  1634. info->params.stop_bits = 2;
  1635. else
  1636. info->params.stop_bits = 1;
  1637. info->params.parity = ASYNC_PARITY_NONE;
  1638. if (cflag & PARENB) {
  1639. if (cflag & PARODD)
  1640. info->params.parity = ASYNC_PARITY_ODD;
  1641. else
  1642. info->params.parity = ASYNC_PARITY_EVEN;
  1643. #ifdef CMSPAR
  1644. if (cflag & CMSPAR)
  1645. info->params.parity = ASYNC_PARITY_SPACE;
  1646. #endif
  1647. }
  1648. /* calculate number of jiffies to transmit a full
  1649. * FIFO (32 bytes) at specified data rate
  1650. */
  1651. bits_per_char = info->params.data_bits +
  1652. info->params.stop_bits + 1;
  1653. /* if port data rate is set to 460800 or less then
  1654. * allow tty settings to override, otherwise keep the
  1655. * current data rate.
  1656. */
  1657. if (info->params.data_rate <= 460800)
  1658. info->params.data_rate = tty_get_baud_rate(info->tty);
  1659. if ( info->params.data_rate ) {
  1660. info->timeout = (32*HZ*bits_per_char) /
  1661. info->params.data_rate;
  1662. }
  1663. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1664. if (cflag & CRTSCTS)
  1665. info->flags |= ASYNC_CTS_FLOW;
  1666. else
  1667. info->flags &= ~ASYNC_CTS_FLOW;
  1668. if (cflag & CLOCAL)
  1669. info->flags &= ~ASYNC_CHECK_CD;
  1670. else
  1671. info->flags |= ASYNC_CHECK_CD;
  1672. /* process tty input control flags */
  1673. info->read_status_mask = RXSTATUS_OVERRUN;
  1674. if (I_INPCK(info->tty))
  1675. info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
  1676. if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
  1677. info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
  1678. if (I_IGNPAR(info->tty))
  1679. info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
  1680. if (I_IGNBRK(info->tty)) {
  1681. info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
  1682. /* If ignoring parity and break indicators, ignore
  1683. * overruns too. (For real raw support).
  1684. */
  1685. if (I_IGNPAR(info->tty))
  1686. info->ignore_status_mask |= RXSTATUS_OVERRUN;
  1687. }
  1688. mgsl_program_hw(info);
  1689. } /* end of mgsl_change_params() */
  1690. /* mgsl_put_char()
  1691. *
  1692. * Add a character to the transmit buffer.
  1693. *
  1694. * Arguments: tty pointer to tty information structure
  1695. * ch character to add to transmit buffer
  1696. *
  1697. * Return Value: None
  1698. */
  1699. static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
  1700. {
  1701. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1702. unsigned long flags;
  1703. if ( debug_level >= DEBUG_LEVEL_INFO ) {
  1704. printk( "%s(%d):mgsl_put_char(%d) on %s\n",
  1705. __FILE__,__LINE__,ch,info->device_name);
  1706. }
  1707. if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
  1708. return;
  1709. if (!tty || !info->xmit_buf)
  1710. return;
  1711. spin_lock_irqsave(&info->irq_spinlock,flags);
  1712. if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
  1713. if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
  1714. info->xmit_buf[info->xmit_head++] = ch;
  1715. info->xmit_head &= SERIAL_XMIT_SIZE-1;
  1716. info->xmit_cnt++;
  1717. }
  1718. }
  1719. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1720. } /* end of mgsl_put_char() */
  1721. /* mgsl_flush_chars()
  1722. *
  1723. * Enable transmitter so remaining characters in the
  1724. * transmit buffer are sent.
  1725. *
  1726. * Arguments: tty pointer to tty information structure
  1727. * Return Value: None
  1728. */
  1729. static void mgsl_flush_chars(struct tty_struct *tty)
  1730. {
  1731. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1732. unsigned long flags;
  1733. if ( debug_level >= DEBUG_LEVEL_INFO )
  1734. printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
  1735. __FILE__,__LINE__,info->device_name,info->xmit_cnt);
  1736. if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
  1737. return;
  1738. if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
  1739. !info->xmit_buf)
  1740. return;
  1741. if ( debug_level >= DEBUG_LEVEL_INFO )
  1742. printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
  1743. __FILE__,__LINE__,info->device_name );
  1744. spin_lock_irqsave(&info->irq_spinlock,flags);
  1745. if (!info->tx_active) {
  1746. if ( (info->params.mode == MGSL_MODE_HDLC ||
  1747. info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
  1748. /* operating in synchronous (frame oriented) mode */
  1749. /* copy data from circular xmit_buf to */
  1750. /* transmit DMA buffer. */
  1751. mgsl_load_tx_dma_buffer(info,
  1752. info->xmit_buf,info->xmit_cnt);
  1753. }
  1754. usc_start_transmitter(info);
  1755. }
  1756. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1757. } /* end of mgsl_flush_chars() */
  1758. /* mgsl_write()
  1759. *
  1760. * Send a block of data
  1761. *
  1762. * Arguments:
  1763. *
  1764. * tty pointer to tty information structure
  1765. * buf pointer to buffer containing send data
  1766. * count size of send data in bytes
  1767. *
  1768. * Return Value: number of characters written
  1769. */
  1770. static int mgsl_write(struct tty_struct * tty,
  1771. const unsigned char *buf, int count)
  1772. {
  1773. int c, ret = 0;
  1774. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1775. unsigned long flags;
  1776. if ( debug_level >= DEBUG_LEVEL_INFO )
  1777. printk( "%s(%d):mgsl_write(%s) count=%d\n",
  1778. __FILE__,__LINE__,info->device_name,count);
  1779. if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
  1780. goto cleanup;
  1781. if (!tty || !info->xmit_buf)
  1782. goto cleanup;
  1783. if ( info->params.mode == MGSL_MODE_HDLC ||
  1784. info->params.mode == MGSL_MODE_RAW ) {
  1785. /* operating in synchronous (frame oriented) mode */
  1786. /* operating in synchronous (frame oriented) mode */
  1787. if (info->tx_active) {
  1788. if ( info->params.mode == MGSL_MODE_HDLC ) {
  1789. ret = 0;
  1790. goto cleanup;
  1791. }
  1792. /* transmitter is actively sending data -
  1793. * if we have multiple transmit dma and
  1794. * holding buffers, attempt to queue this
  1795. * frame for transmission at a later time.
  1796. */
  1797. if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
  1798. /* no tx holding buffers available */
  1799. ret = 0;
  1800. goto cleanup;
  1801. }
  1802. /* queue transmit frame request */
  1803. ret = count;
  1804. save_tx_buffer_request(info,buf,count);
  1805. /* if we have sufficient tx dma buffers,
  1806. * load the next buffered tx request
  1807. */
  1808. spin_lock_irqsave(&info->irq_spinlock,flags);
  1809. load_next_tx_holding_buffer(info);
  1810. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1811. goto cleanup;
  1812. }
  1813. /* if operating in HDLC LoopMode and the adapter */
  1814. /* has yet to be inserted into the loop, we can't */
  1815. /* transmit */
  1816. if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
  1817. !usc_loopmode_active(info) )
  1818. {
  1819. ret = 0;
  1820. goto cleanup;
  1821. }
  1822. if ( info->xmit_cnt ) {
  1823. /* Send accumulated from send_char() calls */
  1824. /* as frame and wait before accepting more data. */
  1825. ret = 0;
  1826. /* copy data from circular xmit_buf to */
  1827. /* transmit DMA buffer. */
  1828. mgsl_load_tx_dma_buffer(info,
  1829. info->xmit_buf,info->xmit_cnt);
  1830. if ( debug_level >= DEBUG_LEVEL_INFO )
  1831. printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
  1832. __FILE__,__LINE__,info->device_name);
  1833. } else {
  1834. if ( debug_level >= DEBUG_LEVEL_INFO )
  1835. printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
  1836. __FILE__,__LINE__,info->device_name);
  1837. ret = count;
  1838. info->xmit_cnt = count;
  1839. mgsl_load_tx_dma_buffer(info,buf,count);
  1840. }
  1841. } else {
  1842. while (1) {
  1843. spin_lock_irqsave(&info->irq_spinlock,flags);
  1844. c = min_t(int, count,
  1845. min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
  1846. SERIAL_XMIT_SIZE - info->xmit_head));
  1847. if (c <= 0) {
  1848. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1849. break;
  1850. }
  1851. memcpy(info->xmit_buf + info->xmit_head, buf, c);
  1852. info->xmit_head = ((info->xmit_head + c) &
  1853. (SERIAL_XMIT_SIZE-1));
  1854. info->xmit_cnt += c;
  1855. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1856. buf += c;
  1857. count -= c;
  1858. ret += c;
  1859. }
  1860. }
  1861. if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
  1862. spin_lock_irqsave(&info->irq_spinlock,flags);
  1863. if (!info->tx_active)
  1864. usc_start_transmitter(info);
  1865. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1866. }
  1867. cleanup:
  1868. if ( debug_level >= DEBUG_LEVEL_INFO )
  1869. printk( "%s(%d):mgsl_write(%s) returning=%d\n",
  1870. __FILE__,__LINE__,info->device_name,ret);
  1871. return ret;
  1872. } /* end of mgsl_write() */
  1873. /* mgsl_write_room()
  1874. *
  1875. * Return the count of free bytes in transmit buffer
  1876. *
  1877. * Arguments: tty pointer to tty info structure
  1878. * Return Value: None
  1879. */
  1880. static int mgsl_write_room(struct tty_struct *tty)
  1881. {
  1882. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1883. int ret;
  1884. if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
  1885. return 0;
  1886. ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
  1887. if (ret < 0)
  1888. ret = 0;
  1889. if (debug_level >= DEBUG_LEVEL_INFO)
  1890. printk("%s(%d):mgsl_write_room(%s)=%d\n",
  1891. __FILE__,__LINE__, info->device_name,ret );
  1892. if ( info->params.mode == MGSL_MODE_HDLC ||
  1893. info->params.mode == MGSL_MODE_RAW ) {
  1894. /* operating in synchronous (frame oriented) mode */
  1895. if ( info->tx_active )
  1896. return 0;
  1897. else
  1898. return HDLC_MAX_FRAME_SIZE;
  1899. }
  1900. return ret;
  1901. } /* end of mgsl_write_room() */
  1902. /* mgsl_chars_in_buffer()
  1903. *
  1904. * Return the count of bytes in transmit buffer
  1905. *
  1906. * Arguments: tty pointer to tty info structure
  1907. * Return Value: None
  1908. */
  1909. static int mgsl_chars_in_buffer(struct tty_struct *tty)
  1910. {
  1911. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1912. if (debug_level >= DEBUG_LEVEL_INFO)
  1913. printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
  1914. __FILE__,__LINE__, info->device_name );
  1915. if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
  1916. return 0;
  1917. if (debug_level >= DEBUG_LEVEL_INFO)
  1918. printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
  1919. __FILE__,__LINE__, info->device_name,info->xmit_cnt );
  1920. if ( info->params.mode == MGSL_MODE_HDLC ||
  1921. info->params.mode == MGSL_MODE_RAW ) {
  1922. /* operating in synchronous (frame oriented) mode */
  1923. if ( info->tx_active )
  1924. return info->max_frame_size;
  1925. else
  1926. return 0;
  1927. }
  1928. return info->xmit_cnt;
  1929. } /* end of mgsl_chars_in_buffer() */
  1930. /* mgsl_flush_buffer()
  1931. *
  1932. * Discard all data in the send buffer
  1933. *
  1934. * Arguments: tty pointer to tty info structure
  1935. * Return Value: None
  1936. */
  1937. static void mgsl_flush_buffer(struct tty_struct *tty)
  1938. {
  1939. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1940. unsigned long flags;
  1941. if (debug_level >= DEBUG_LEVEL_INFO)
  1942. printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
  1943. __FILE__,__LINE__, info->device_name );
  1944. if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
  1945. return;
  1946. spin_lock_irqsave(&info->irq_spinlock,flags);
  1947. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1948. del_timer(&info->tx_timer);
  1949. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1950. tty_wakeup(tty);
  1951. }
  1952. /* mgsl_send_xchar()
  1953. *
  1954. * Send a high-priority XON/XOFF character
  1955. *
  1956. * Arguments: tty pointer to tty info structure
  1957. * ch character to send
  1958. * Return Value: None
  1959. */
  1960. static void mgsl_send_xchar(struct tty_struct *tty, char ch)
  1961. {
  1962. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1963. unsigned long flags;
  1964. if (debug_level >= DEBUG_LEVEL_INFO)
  1965. printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
  1966. __FILE__,__LINE__, info->device_name, ch );
  1967. if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
  1968. return;
  1969. info->x_char = ch;
  1970. if (ch) {
  1971. /* Make sure transmit interrupts are on */
  1972. spin_lock_irqsave(&info->irq_spinlock,flags);
  1973. if (!info->tx_enabled)
  1974. usc_start_transmitter(info);
  1975. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  1976. }
  1977. } /* end of mgsl_send_xchar() */
  1978. /* mgsl_throttle()
  1979. *
  1980. * Signal remote device to throttle send data (our receive data)
  1981. *
  1982. * Arguments: tty pointer to tty info structure
  1983. * Return Value: None
  1984. */
  1985. static void mgsl_throttle(struct tty_struct * tty)
  1986. {
  1987. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  1988. unsigned long flags;
  1989. if (debug_level >= DEBUG_LEVEL_INFO)
  1990. printk("%s(%d):mgsl_throttle(%s) entry\n",
  1991. __FILE__,__LINE__, info->device_name );
  1992. if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
  1993. return;
  1994. if (I_IXOFF(tty))
  1995. mgsl_send_xchar(tty, STOP_CHAR(tty));
  1996. if (tty->termios->c_cflag & CRTSCTS) {
  1997. spin_lock_irqsave(&info->irq_spinlock,flags);
  1998. info->serial_signals &= ~SerialSignal_RTS;
  1999. usc_set_serial_signals(info);
  2000. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2001. }
  2002. } /* end of mgsl_throttle() */
  2003. /* mgsl_unthrottle()
  2004. *
  2005. * Signal remote device to stop throttling send data (our receive data)
  2006. *
  2007. * Arguments: tty pointer to tty info structure
  2008. * Return Value: None
  2009. */
  2010. static void mgsl_unthrottle(struct tty_struct * tty)
  2011. {
  2012. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  2013. unsigned long flags;
  2014. if (debug_level >= DEBUG_LEVEL_INFO)
  2015. printk("%s(%d):mgsl_unthrottle(%s) entry\n",
  2016. __FILE__,__LINE__, info->device_name );
  2017. if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
  2018. return;
  2019. if (I_IXOFF(tty)) {
  2020. if (info->x_char)
  2021. info->x_char = 0;
  2022. else
  2023. mgsl_send_xchar(tty, START_CHAR(tty));
  2024. }
  2025. if (tty->termios->c_cflag & CRTSCTS) {
  2026. spin_lock_irqsave(&info->irq_spinlock,flags);
  2027. info->serial_signals |= SerialSignal_RTS;
  2028. usc_set_serial_signals(info);
  2029. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2030. }
  2031. } /* end of mgsl_unthrottle() */
  2032. /* mgsl_get_stats()
  2033. *
  2034. * get the current serial parameters information
  2035. *
  2036. * Arguments: info pointer to device instance data
  2037. * user_icount pointer to buffer to hold returned stats
  2038. *
  2039. * Return Value: 0 if success, otherwise error code
  2040. */
  2041. static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
  2042. {
  2043. int err;
  2044. if (debug_level >= DEBUG_LEVEL_INFO)
  2045. printk("%s(%d):mgsl_get_params(%s)\n",
  2046. __FILE__,__LINE__, info->device_name);
  2047. if (!user_icount) {
  2048. memset(&info->icount, 0, sizeof(info->icount));
  2049. } else {
  2050. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  2051. if (err)
  2052. return -EFAULT;
  2053. }
  2054. return 0;
  2055. } /* end of mgsl_get_stats() */
  2056. /* mgsl_get_params()
  2057. *
  2058. * get the current serial parameters information
  2059. *
  2060. * Arguments: info pointer to device instance data
  2061. * user_params pointer to buffer to hold returned params
  2062. *
  2063. * Return Value: 0 if success, otherwise error code
  2064. */
  2065. static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
  2066. {
  2067. int err;
  2068. if (debug_level >= DEBUG_LEVEL_INFO)
  2069. printk("%s(%d):mgsl_get_params(%s)\n",
  2070. __FILE__,__LINE__, info->device_name);
  2071. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  2072. if (err) {
  2073. if ( debug_level >= DEBUG_LEVEL_INFO )
  2074. printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
  2075. __FILE__,__LINE__,info->device_name);
  2076. return -EFAULT;
  2077. }
  2078. return 0;
  2079. } /* end of mgsl_get_params() */
  2080. /* mgsl_set_params()
  2081. *
  2082. * set the serial parameters
  2083. *
  2084. * Arguments:
  2085. *
  2086. * info pointer to device instance data
  2087. * new_params user buffer containing new serial params
  2088. *
  2089. * Return Value: 0 if success, otherwise error code
  2090. */
  2091. static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
  2092. {
  2093. unsigned long flags;
  2094. MGSL_PARAMS tmp_params;
  2095. int err;
  2096. if (debug_level >= DEBUG_LEVEL_INFO)
  2097. printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
  2098. info->device_name );
  2099. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  2100. if (err) {
  2101. if ( debug_level >= DEBUG_LEVEL_INFO )
  2102. printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
  2103. __FILE__,__LINE__,info->device_name);
  2104. return -EFAULT;
  2105. }
  2106. spin_lock_irqsave(&info->irq_spinlock,flags);
  2107. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  2108. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2109. mgsl_change_params(info);
  2110. return 0;
  2111. } /* end of mgsl_set_params() */
  2112. /* mgsl_get_txidle()
  2113. *
  2114. * get the current transmit idle mode
  2115. *
  2116. * Arguments: info pointer to device instance data
  2117. * idle_mode pointer to buffer to hold returned idle mode
  2118. *
  2119. * Return Value: 0 if success, otherwise error code
  2120. */
  2121. static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
  2122. {
  2123. int err;
  2124. if (debug_level >= DEBUG_LEVEL_INFO)
  2125. printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
  2126. __FILE__,__LINE__, info->device_name, info->idle_mode);
  2127. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  2128. if (err) {
  2129. if ( debug_level >= DEBUG_LEVEL_INFO )
  2130. printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
  2131. __FILE__,__LINE__,info->device_name);
  2132. return -EFAULT;
  2133. }
  2134. return 0;
  2135. } /* end of mgsl_get_txidle() */
  2136. /* mgsl_set_txidle() service ioctl to set transmit idle mode
  2137. *
  2138. * Arguments: info pointer to device instance data
  2139. * idle_mode new idle mode
  2140. *
  2141. * Return Value: 0 if success, otherwise error code
  2142. */
  2143. static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
  2144. {
  2145. unsigned long flags;
  2146. if (debug_level >= DEBUG_LEVEL_INFO)
  2147. printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
  2148. info->device_name, idle_mode );
  2149. spin_lock_irqsave(&info->irq_spinlock,flags);
  2150. info->idle_mode = idle_mode;
  2151. usc_set_txidle( info );
  2152. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2153. return 0;
  2154. } /* end of mgsl_set_txidle() */
  2155. /* mgsl_txenable()
  2156. *
  2157. * enable or disable the transmitter
  2158. *
  2159. * Arguments:
  2160. *
  2161. * info pointer to device instance data
  2162. * enable 1 = enable, 0 = disable
  2163. *
  2164. * Return Value: 0 if success, otherwise error code
  2165. */
  2166. static int mgsl_txenable(struct mgsl_struct * info, int enable)
  2167. {
  2168. unsigned long flags;
  2169. if (debug_level >= DEBUG_LEVEL_INFO)
  2170. printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
  2171. info->device_name, enable);
  2172. spin_lock_irqsave(&info->irq_spinlock,flags);
  2173. if ( enable ) {
  2174. if ( !info->tx_enabled ) {
  2175. usc_start_transmitter(info);
  2176. /*--------------------------------------------------
  2177. * if HDLC/SDLC Loop mode, attempt to insert the
  2178. * station in the 'loop' by setting CMR:13. Upon
  2179. * receipt of the next GoAhead (RxAbort) sequence,
  2180. * the OnLoop indicator (CCSR:7) should go active
  2181. * to indicate that we are on the loop
  2182. *--------------------------------------------------*/
  2183. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  2184. usc_loopmode_insert_request( info );
  2185. }
  2186. } else {
  2187. if ( info->tx_enabled )
  2188. usc_stop_transmitter(info);
  2189. }
  2190. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2191. return 0;
  2192. } /* end of mgsl_txenable() */
  2193. /* mgsl_txabort() abort send HDLC frame
  2194. *
  2195. * Arguments: info pointer to device instance data
  2196. * Return Value: 0 if success, otherwise error code
  2197. */
  2198. static int mgsl_txabort(struct mgsl_struct * info)
  2199. {
  2200. unsigned long flags;
  2201. if (debug_level >= DEBUG_LEVEL_INFO)
  2202. printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
  2203. info->device_name);
  2204. spin_lock_irqsave(&info->irq_spinlock,flags);
  2205. if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
  2206. {
  2207. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  2208. usc_loopmode_cancel_transmit( info );
  2209. else
  2210. usc_TCmd(info,TCmd_SendAbort);
  2211. }
  2212. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2213. return 0;
  2214. } /* end of mgsl_txabort() */
  2215. /* mgsl_rxenable() enable or disable the receiver
  2216. *
  2217. * Arguments: info pointer to device instance data
  2218. * enable 1 = enable, 0 = disable
  2219. * Return Value: 0 if success, otherwise error code
  2220. */
  2221. static int mgsl_rxenable(struct mgsl_struct * info, int enable)
  2222. {
  2223. unsigned long flags;
  2224. if (debug_level >= DEBUG_LEVEL_INFO)
  2225. printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
  2226. info->device_name, enable);
  2227. spin_lock_irqsave(&info->irq_spinlock,flags);
  2228. if ( enable ) {
  2229. if ( !info->rx_enabled )
  2230. usc_start_receiver(info);
  2231. } else {
  2232. if ( info->rx_enabled )
  2233. usc_stop_receiver(info);
  2234. }
  2235. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2236. return 0;
  2237. } /* end of mgsl_rxenable() */
  2238. /* mgsl_wait_event() wait for specified event to occur
  2239. *
  2240. * Arguments: info pointer to device instance data
  2241. * mask pointer to bitmask of events to wait for
  2242. * Return Value: 0 if successful and bit mask updated with
  2243. * of events triggerred,
  2244. * otherwise error code
  2245. */
  2246. static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
  2247. {
  2248. unsigned long flags;
  2249. int s;
  2250. int rc=0;
  2251. struct mgsl_icount cprev, cnow;
  2252. int events;
  2253. int mask;
  2254. struct _input_signal_events oldsigs, newsigs;
  2255. DECLARE_WAITQUEUE(wait, current);
  2256. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  2257. if (rc) {
  2258. return -EFAULT;
  2259. }
  2260. if (debug_level >= DEBUG_LEVEL_INFO)
  2261. printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
  2262. info->device_name, mask);
  2263. spin_lock_irqsave(&info->irq_spinlock,flags);
  2264. /* return immediately if state matches requested events */
  2265. usc_get_serial_signals(info);
  2266. s = info->serial_signals;
  2267. events = mask &
  2268. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  2269. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  2270. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  2271. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  2272. if (events) {
  2273. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2274. goto exit;
  2275. }
  2276. /* save current irq counts */
  2277. cprev = info->icount;
  2278. oldsigs = info->input_signal_events;
  2279. /* enable hunt and idle irqs if needed */
  2280. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2281. u16 oldreg = usc_InReg(info,RICR);
  2282. u16 newreg = oldreg +
  2283. (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
  2284. (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
  2285. if (oldreg != newreg)
  2286. usc_OutReg(info, RICR, newreg);
  2287. }
  2288. set_current_state(TASK_INTERRUPTIBLE);
  2289. add_wait_queue(&info->event_wait_q, &wait);
  2290. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2291. for(;;) {
  2292. schedule();
  2293. if (signal_pending(current)) {
  2294. rc = -ERESTARTSYS;
  2295. break;
  2296. }
  2297. /* get current irq counts */
  2298. spin_lock_irqsave(&info->irq_spinlock,flags);
  2299. cnow = info->icount;
  2300. newsigs = info->input_signal_events;
  2301. set_current_state(TASK_INTERRUPTIBLE);
  2302. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2303. /* if no change, wait aborted for some reason */
  2304. if (newsigs.dsr_up == oldsigs.dsr_up &&
  2305. newsigs.dsr_down == oldsigs.dsr_down &&
  2306. newsigs.dcd_up == oldsigs.dcd_up &&
  2307. newsigs.dcd_down == oldsigs.dcd_down &&
  2308. newsigs.cts_up == oldsigs.cts_up &&
  2309. newsigs.cts_down == oldsigs.cts_down &&
  2310. newsigs.ri_up == oldsigs.ri_up &&
  2311. newsigs.ri_down == oldsigs.ri_down &&
  2312. cnow.exithunt == cprev.exithunt &&
  2313. cnow.rxidle == cprev.rxidle) {
  2314. rc = -EIO;
  2315. break;
  2316. }
  2317. events = mask &
  2318. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  2319. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  2320. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  2321. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  2322. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  2323. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  2324. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  2325. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  2326. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  2327. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  2328. if (events)
  2329. break;
  2330. cprev = cnow;
  2331. oldsigs = newsigs;
  2332. }
  2333. remove_wait_queue(&info->event_wait_q, &wait);
  2334. set_current_state(TASK_RUNNING);
  2335. if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
  2336. spin_lock_irqsave(&info->irq_spinlock,flags);
  2337. if (!waitqueue_active(&info->event_wait_q)) {
  2338. /* disable enable exit hunt mode/idle rcvd IRQs */
  2339. usc_OutReg(info, RICR, usc_InReg(info,RICR) &
  2340. ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
  2341. }
  2342. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2343. }
  2344. exit:
  2345. if ( rc == 0 )
  2346. PUT_USER(rc, events, mask_ptr);
  2347. return rc;
  2348. } /* end of mgsl_wait_event() */
  2349. static int modem_input_wait(struct mgsl_struct *info,int arg)
  2350. {
  2351. unsigned long flags;
  2352. int rc;
  2353. struct mgsl_icount cprev, cnow;
  2354. DECLARE_WAITQUEUE(wait, current);
  2355. /* save current irq counts */
  2356. spin_lock_irqsave(&info->irq_spinlock,flags);
  2357. cprev = info->icount;
  2358. add_wait_queue(&info->status_event_wait_q, &wait);
  2359. set_current_state(TASK_INTERRUPTIBLE);
  2360. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2361. for(;;) {
  2362. schedule();
  2363. if (signal_pending(current)) {
  2364. rc = -ERESTARTSYS;
  2365. break;
  2366. }
  2367. /* get new irq counts */
  2368. spin_lock_irqsave(&info->irq_spinlock,flags);
  2369. cnow = info->icount;
  2370. set_current_state(TASK_INTERRUPTIBLE);
  2371. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2372. /* if no change, wait aborted for some reason */
  2373. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  2374. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  2375. rc = -EIO;
  2376. break;
  2377. }
  2378. /* check for change in caller specified modem input */
  2379. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  2380. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  2381. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  2382. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  2383. rc = 0;
  2384. break;
  2385. }
  2386. cprev = cnow;
  2387. }
  2388. remove_wait_queue(&info->status_event_wait_q, &wait);
  2389. set_current_state(TASK_RUNNING);
  2390. return rc;
  2391. }
  2392. /* return the state of the serial control and status signals
  2393. */
  2394. static int tiocmget(struct tty_struct *tty, struct file *file)
  2395. {
  2396. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  2397. unsigned int result;
  2398. unsigned long flags;
  2399. spin_lock_irqsave(&info->irq_spinlock,flags);
  2400. usc_get_serial_signals(info);
  2401. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2402. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  2403. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  2404. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  2405. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  2406. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  2407. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  2408. if (debug_level >= DEBUG_LEVEL_INFO)
  2409. printk("%s(%d):%s tiocmget() value=%08X\n",
  2410. __FILE__,__LINE__, info->device_name, result );
  2411. return result;
  2412. }
  2413. /* set modem control signals (DTR/RTS)
  2414. */
  2415. static int tiocmset(struct tty_struct *tty, struct file *file,
  2416. unsigned int set, unsigned int clear)
  2417. {
  2418. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  2419. unsigned long flags;
  2420. if (debug_level >= DEBUG_LEVEL_INFO)
  2421. printk("%s(%d):%s tiocmset(%x,%x)\n",
  2422. __FILE__,__LINE__,info->device_name, set, clear);
  2423. if (set & TIOCM_RTS)
  2424. info->serial_signals |= SerialSignal_RTS;
  2425. if (set & TIOCM_DTR)
  2426. info->serial_signals |= SerialSignal_DTR;
  2427. if (clear & TIOCM_RTS)
  2428. info->serial_signals &= ~SerialSignal_RTS;
  2429. if (clear & TIOCM_DTR)
  2430. info->serial_signals &= ~SerialSignal_DTR;
  2431. spin_lock_irqsave(&info->irq_spinlock,flags);
  2432. usc_set_serial_signals(info);
  2433. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2434. return 0;
  2435. }
  2436. /* mgsl_break() Set or clear transmit break condition
  2437. *
  2438. * Arguments: tty pointer to tty instance data
  2439. * break_state -1=set break condition, 0=clear
  2440. * Return Value: None
  2441. */
  2442. static void mgsl_break(struct tty_struct *tty, int break_state)
  2443. {
  2444. struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
  2445. unsigned long flags;
  2446. if (debug_level >= DEBUG_LEVEL_INFO)
  2447. printk("%s(%d):mgsl_break(%s,%d)\n",
  2448. __FILE__,__LINE__, info->device_name, break_state);
  2449. if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
  2450. return;
  2451. spin_lock_irqsave(&info->irq_spinlock,flags);
  2452. if (break_state == -1)
  2453. usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
  2454. else
  2455. usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
  2456. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2457. } /* end of mgsl_break() */
  2458. /* mgsl_ioctl() Service an IOCTL request
  2459. *
  2460. * Arguments:
  2461. *
  2462. * tty pointer to tty instance data
  2463. * file pointer to associated file object for device
  2464. * cmd IOCTL command code
  2465. * arg command argument/context
  2466. *
  2467. * Return Value: 0 if success, otherwise error code
  2468. */
  2469. static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
  2470. unsigned int cmd, unsigned long arg)
  2471. {
  2472. struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
  2473. if (debug_level >= DEBUG_LEVEL_INFO)
  2474. printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  2475. info->device_name, cmd );
  2476. if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
  2477. return -ENODEV;
  2478. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  2479. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  2480. if (tty->flags & (1 << TTY_IO_ERROR))
  2481. return -EIO;
  2482. }
  2483. return mgsl_ioctl_common(info, cmd, arg);
  2484. }
  2485. static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
  2486. {
  2487. int error;
  2488. struct mgsl_icount cnow; /* kernel counter temps */
  2489. void __user *argp = (void __user *)arg;
  2490. struct serial_icounter_struct __user *p_cuser; /* user space */
  2491. unsigned long flags;
  2492. switch (cmd) {
  2493. case MGSL_IOCGPARAMS:
  2494. return mgsl_get_params(info, argp);
  2495. case MGSL_IOCSPARAMS:
  2496. return mgsl_set_params(info, argp);
  2497. case MGSL_IOCGTXIDLE:
  2498. return mgsl_get_txidle(info, argp);
  2499. case MGSL_IOCSTXIDLE:
  2500. return mgsl_set_txidle(info,(int)arg);
  2501. case MGSL_IOCTXENABLE:
  2502. return mgsl_txenable(info,(int)arg);
  2503. case MGSL_IOCRXENABLE:
  2504. return mgsl_rxenable(info,(int)arg);
  2505. case MGSL_IOCTXABORT:
  2506. return mgsl_txabort(info);
  2507. case MGSL_IOCGSTATS:
  2508. return mgsl_get_stats(info, argp);
  2509. case MGSL_IOCWAITEVENT:
  2510. return mgsl_wait_event(info, argp);
  2511. case MGSL_IOCLOOPTXDONE:
  2512. return mgsl_loopmode_send_done(info);
  2513. /* Wait for modem input (DCD,RI,DSR,CTS) change
  2514. * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
  2515. */
  2516. case TIOCMIWAIT:
  2517. return modem_input_wait(info,(int)arg);
  2518. /*
  2519. * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
  2520. * Return: write counters to the user passed counter struct
  2521. * NB: both 1->0 and 0->1 transitions are counted except for
  2522. * RI where only 0->1 is counted.
  2523. */
  2524. case TIOCGICOUNT:
  2525. spin_lock_irqsave(&info->irq_spinlock,flags);
  2526. cnow = info->icount;
  2527. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2528. p_cuser = argp;
  2529. PUT_USER(error,cnow.cts, &p_cuser->cts);
  2530. if (error) return error;
  2531. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  2532. if (error) return error;
  2533. PUT_USER(error,cnow.rng, &p_cuser->rng);
  2534. if (error) return error;
  2535. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  2536. if (error) return error;
  2537. PUT_USER(error,cnow.rx, &p_cuser->rx);
  2538. if (error) return error;
  2539. PUT_USER(error,cnow.tx, &p_cuser->tx);
  2540. if (error) return error;
  2541. PUT_USER(error,cnow.frame, &p_cuser->frame);
  2542. if (error) return error;
  2543. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  2544. if (error) return error;
  2545. PUT_USER(error,cnow.parity, &p_cuser->parity);
  2546. if (error) return error;
  2547. PUT_USER(error,cnow.brk, &p_cuser->brk);
  2548. if (error) return error;
  2549. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  2550. if (error) return error;
  2551. return 0;
  2552. default:
  2553. return -ENOIOCTLCMD;
  2554. }
  2555. return 0;
  2556. }
  2557. /* mgsl_set_termios()
  2558. *
  2559. * Set new termios settings
  2560. *
  2561. * Arguments:
  2562. *
  2563. * tty pointer to tty structure
  2564. * termios pointer to buffer to hold returned old termios
  2565. *
  2566. * Return Value: None
  2567. */
  2568. static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
  2569. {
  2570. struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
  2571. unsigned long flags;
  2572. if (debug_level >= DEBUG_LEVEL_INFO)
  2573. printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
  2574. tty->driver->name );
  2575. /* just return if nothing has changed */
  2576. if ((tty->termios->c_cflag == old_termios->c_cflag)
  2577. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  2578. == RELEVANT_IFLAG(old_termios->c_iflag)))
  2579. return;
  2580. mgsl_change_params(info);
  2581. /* Handle transition to B0 status */
  2582. if (old_termios->c_cflag & CBAUD &&
  2583. !(tty->termios->c_cflag & CBAUD)) {
  2584. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2585. spin_lock_irqsave(&info->irq_spinlock,flags);
  2586. usc_set_serial_signals(info);
  2587. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2588. }
  2589. /* Handle transition away from B0 status */
  2590. if (!(old_termios->c_cflag & CBAUD) &&
  2591. tty->termios->c_cflag & CBAUD) {
  2592. info->serial_signals |= SerialSignal_DTR;
  2593. if (!(tty->termios->c_cflag & CRTSCTS) ||
  2594. !test_bit(TTY_THROTTLED, &tty->flags)) {
  2595. info->serial_signals |= SerialSignal_RTS;
  2596. }
  2597. spin_lock_irqsave(&info->irq_spinlock,flags);
  2598. usc_set_serial_signals(info);
  2599. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2600. }
  2601. /* Handle turning off CRTSCTS */
  2602. if (old_termios->c_cflag & CRTSCTS &&
  2603. !(tty->termios->c_cflag & CRTSCTS)) {
  2604. tty->hw_stopped = 0;
  2605. mgsl_start(tty);
  2606. }
  2607. } /* end of mgsl_set_termios() */
  2608. /* mgsl_close()
  2609. *
  2610. * Called when port is closed. Wait for remaining data to be
  2611. * sent. Disable port and free resources.
  2612. *
  2613. * Arguments:
  2614. *
  2615. * tty pointer to open tty structure
  2616. * filp pointer to open file object
  2617. *
  2618. * Return Value: None
  2619. */
  2620. static void mgsl_close(struct tty_struct *tty, struct file * filp)
  2621. {
  2622. struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
  2623. if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
  2624. return;
  2625. if (debug_level >= DEBUG_LEVEL_INFO)
  2626. printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
  2627. __FILE__,__LINE__, info->device_name, info->count);
  2628. if (!info->count)
  2629. return;
  2630. if (tty_hung_up_p(filp))
  2631. goto cleanup;
  2632. if ((tty->count == 1) && (info->count != 1)) {
  2633. /*
  2634. * tty->count is 1 and the tty structure will be freed.
  2635. * info->count should be one in this case.
  2636. * if it's not, correct it so that the port is shutdown.
  2637. */
  2638. printk("mgsl_close: bad refcount; tty->count is 1, "
  2639. "info->count is %d\n", info->count);
  2640. info->count = 1;
  2641. }
  2642. info->count--;
  2643. /* if at least one open remaining, leave hardware active */
  2644. if (info->count)
  2645. goto cleanup;
  2646. info->flags |= ASYNC_CLOSING;
  2647. /* set tty->closing to notify line discipline to
  2648. * only process XON/XOFF characters. Only the N_TTY
  2649. * discipline appears to use this (ppp does not).
  2650. */
  2651. tty->closing = 1;
  2652. /* wait for transmit data to clear all layers */
  2653. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  2654. if (debug_level >= DEBUG_LEVEL_INFO)
  2655. printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
  2656. __FILE__,__LINE__, info->device_name );
  2657. tty_wait_until_sent(tty, info->closing_wait);
  2658. }
  2659. if (info->flags & ASYNC_INITIALIZED)
  2660. mgsl_wait_until_sent(tty, info->timeout);
  2661. if (tty->driver->flush_buffer)
  2662. tty->driver->flush_buffer(tty);
  2663. tty_ldisc_flush(tty);
  2664. shutdown(info);
  2665. tty->closing = 0;
  2666. info->tty = NULL;
  2667. if (info->blocked_open) {
  2668. if (info->close_delay) {
  2669. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  2670. }
  2671. wake_up_interruptible(&info->open_wait);
  2672. }
  2673. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  2674. wake_up_interruptible(&info->close_wait);
  2675. cleanup:
  2676. if (debug_level >= DEBUG_LEVEL_INFO)
  2677. printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2678. tty->driver->name, info->count);
  2679. } /* end of mgsl_close() */
  2680. /* mgsl_wait_until_sent()
  2681. *
  2682. * Wait until the transmitter is empty.
  2683. *
  2684. * Arguments:
  2685. *
  2686. * tty pointer to tty info structure
  2687. * timeout time to wait for send completion
  2688. *
  2689. * Return Value: None
  2690. */
  2691. static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
  2692. {
  2693. struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
  2694. unsigned long orig_jiffies, char_time;
  2695. if (!info )
  2696. return;
  2697. if (debug_level >= DEBUG_LEVEL_INFO)
  2698. printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
  2699. __FILE__,__LINE__, info->device_name );
  2700. if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
  2701. return;
  2702. if (!(info->flags & ASYNC_INITIALIZED))
  2703. goto exit;
  2704. orig_jiffies = jiffies;
  2705. /* Set check interval to 1/5 of estimated time to
  2706. * send a character, and make it at least 1. The check
  2707. * interval should also be less than the timeout.
  2708. * Note: use tight timings here to satisfy the NIST-PCTS.
  2709. */
  2710. if ( info->params.data_rate ) {
  2711. char_time = info->timeout/(32 * 5);
  2712. if (!char_time)
  2713. char_time++;
  2714. } else
  2715. char_time = 1;
  2716. if (timeout)
  2717. char_time = min_t(unsigned long, char_time, timeout);
  2718. if ( info->params.mode == MGSL_MODE_HDLC ||
  2719. info->params.mode == MGSL_MODE_RAW ) {
  2720. while (info->tx_active) {
  2721. msleep_interruptible(jiffies_to_msecs(char_time));
  2722. if (signal_pending(current))
  2723. break;
  2724. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2725. break;
  2726. }
  2727. } else {
  2728. while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
  2729. info->tx_enabled) {
  2730. msleep_interruptible(jiffies_to_msecs(char_time));
  2731. if (signal_pending(current))
  2732. break;
  2733. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2734. break;
  2735. }
  2736. }
  2737. exit:
  2738. if (debug_level >= DEBUG_LEVEL_INFO)
  2739. printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
  2740. __FILE__,__LINE__, info->device_name );
  2741. } /* end of mgsl_wait_until_sent() */
  2742. /* mgsl_hangup()
  2743. *
  2744. * Called by tty_hangup() when a hangup is signaled.
  2745. * This is the same as to closing all open files for the port.
  2746. *
  2747. * Arguments: tty pointer to associated tty object
  2748. * Return Value: None
  2749. */
  2750. static void mgsl_hangup(struct tty_struct *tty)
  2751. {
  2752. struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
  2753. if (debug_level >= DEBUG_LEVEL_INFO)
  2754. printk("%s(%d):mgsl_hangup(%s)\n",
  2755. __FILE__,__LINE__, info->device_name );
  2756. if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
  2757. return;
  2758. mgsl_flush_buffer(tty);
  2759. shutdown(info);
  2760. info->count = 0;
  2761. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  2762. info->tty = NULL;
  2763. wake_up_interruptible(&info->open_wait);
  2764. } /* end of mgsl_hangup() */
  2765. /* block_til_ready()
  2766. *
  2767. * Block the current process until the specified port
  2768. * is ready to be opened.
  2769. *
  2770. * Arguments:
  2771. *
  2772. * tty pointer to tty info structure
  2773. * filp pointer to open file object
  2774. * info pointer to device instance data
  2775. *
  2776. * Return Value: 0 if success, otherwise error code
  2777. */
  2778. static int block_til_ready(struct tty_struct *tty, struct file * filp,
  2779. struct mgsl_struct *info)
  2780. {
  2781. DECLARE_WAITQUEUE(wait, current);
  2782. int retval;
  2783. int do_clocal = 0, extra_count = 0;
  2784. unsigned long flags;
  2785. if (debug_level >= DEBUG_LEVEL_INFO)
  2786. printk("%s(%d):block_til_ready on %s\n",
  2787. __FILE__,__LINE__, tty->driver->name );
  2788. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2789. /* nonblock mode is set or port is not enabled */
  2790. info->flags |= ASYNC_NORMAL_ACTIVE;
  2791. return 0;
  2792. }
  2793. if (tty->termios->c_cflag & CLOCAL)
  2794. do_clocal = 1;
  2795. /* Wait for carrier detect and the line to become
  2796. * free (i.e., not in use by the callout). While we are in
  2797. * this loop, info->count is dropped by one, so that
  2798. * mgsl_close() knows when to free things. We restore it upon
  2799. * exit, either normal or abnormal.
  2800. */
  2801. retval = 0;
  2802. add_wait_queue(&info->open_wait, &wait);
  2803. if (debug_level >= DEBUG_LEVEL_INFO)
  2804. printk("%s(%d):block_til_ready before block on %s count=%d\n",
  2805. __FILE__,__LINE__, tty->driver->name, info->count );
  2806. spin_lock_irqsave(&info->irq_spinlock, flags);
  2807. if (!tty_hung_up_p(filp)) {
  2808. extra_count = 1;
  2809. info->count--;
  2810. }
  2811. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  2812. info->blocked_open++;
  2813. while (1) {
  2814. if (tty->termios->c_cflag & CBAUD) {
  2815. spin_lock_irqsave(&info->irq_spinlock,flags);
  2816. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2817. usc_set_serial_signals(info);
  2818. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2819. }
  2820. set_current_state(TASK_INTERRUPTIBLE);
  2821. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2822. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2823. -EAGAIN : -ERESTARTSYS;
  2824. break;
  2825. }
  2826. spin_lock_irqsave(&info->irq_spinlock,flags);
  2827. usc_get_serial_signals(info);
  2828. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2829. if (!(info->flags & ASYNC_CLOSING) &&
  2830. (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
  2831. break;
  2832. }
  2833. if (signal_pending(current)) {
  2834. retval = -ERESTARTSYS;
  2835. break;
  2836. }
  2837. if (debug_level >= DEBUG_LEVEL_INFO)
  2838. printk("%s(%d):block_til_ready blocking on %s count=%d\n",
  2839. __FILE__,__LINE__, tty->driver->name, info->count );
  2840. schedule();
  2841. }
  2842. set_current_state(TASK_RUNNING);
  2843. remove_wait_queue(&info->open_wait, &wait);
  2844. if (extra_count)
  2845. info->count++;
  2846. info->blocked_open--;
  2847. if (debug_level >= DEBUG_LEVEL_INFO)
  2848. printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
  2849. __FILE__,__LINE__, tty->driver->name, info->count );
  2850. if (!retval)
  2851. info->flags |= ASYNC_NORMAL_ACTIVE;
  2852. return retval;
  2853. } /* end of block_til_ready() */
  2854. /* mgsl_open()
  2855. *
  2856. * Called when a port is opened. Init and enable port.
  2857. * Perform serial-specific initialization for the tty structure.
  2858. *
  2859. * Arguments: tty pointer to tty info structure
  2860. * filp associated file pointer
  2861. *
  2862. * Return Value: 0 if success, otherwise error code
  2863. */
  2864. static int mgsl_open(struct tty_struct *tty, struct file * filp)
  2865. {
  2866. struct mgsl_struct *info;
  2867. int retval, line;
  2868. unsigned long flags;
  2869. /* verify range of specified line number */
  2870. line = tty->index;
  2871. if ((line < 0) || (line >= mgsl_device_count)) {
  2872. printk("%s(%d):mgsl_open with invalid line #%d.\n",
  2873. __FILE__,__LINE__,line);
  2874. return -ENODEV;
  2875. }
  2876. /* find the info structure for the specified line */
  2877. info = mgsl_device_list;
  2878. while(info && info->line != line)
  2879. info = info->next_device;
  2880. if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
  2881. return -ENODEV;
  2882. tty->driver_data = info;
  2883. info->tty = tty;
  2884. if (debug_level >= DEBUG_LEVEL_INFO)
  2885. printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
  2886. __FILE__,__LINE__,tty->driver->name, info->count);
  2887. /* If port is closing, signal caller to try again */
  2888. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  2889. if (info->flags & ASYNC_CLOSING)
  2890. interruptible_sleep_on(&info->close_wait);
  2891. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  2892. -EAGAIN : -ERESTARTSYS);
  2893. goto cleanup;
  2894. }
  2895. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2896. spin_lock_irqsave(&info->netlock, flags);
  2897. if (info->netcount) {
  2898. retval = -EBUSY;
  2899. spin_unlock_irqrestore(&info->netlock, flags);
  2900. goto cleanup;
  2901. }
  2902. info->count++;
  2903. spin_unlock_irqrestore(&info->netlock, flags);
  2904. if (info->count == 1) {
  2905. /* 1st open on this device, init hardware */
  2906. retval = startup(info);
  2907. if (retval < 0)
  2908. goto cleanup;
  2909. }
  2910. retval = block_til_ready(tty, filp, info);
  2911. if (retval) {
  2912. if (debug_level >= DEBUG_LEVEL_INFO)
  2913. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2914. __FILE__,__LINE__, info->device_name, retval);
  2915. goto cleanup;
  2916. }
  2917. if (debug_level >= DEBUG_LEVEL_INFO)
  2918. printk("%s(%d):mgsl_open(%s) success\n",
  2919. __FILE__,__LINE__, info->device_name);
  2920. retval = 0;
  2921. cleanup:
  2922. if (retval) {
  2923. if (tty->count == 1)
  2924. info->tty = NULL; /* tty layer will release tty struct */
  2925. if(info->count)
  2926. info->count--;
  2927. }
  2928. return retval;
  2929. } /* end of mgsl_open() */
  2930. /*
  2931. * /proc fs routines....
  2932. */
  2933. static inline int line_info(char *buf, struct mgsl_struct *info)
  2934. {
  2935. char stat_buf[30];
  2936. int ret;
  2937. unsigned long flags;
  2938. if (info->bus_type == MGSL_BUS_TYPE_PCI) {
  2939. ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
  2940. info->device_name, info->io_base, info->irq_level,
  2941. info->phys_memory_base, info->phys_lcr_base);
  2942. } else {
  2943. ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
  2944. info->device_name, info->io_base,
  2945. info->irq_level, info->dma_level);
  2946. }
  2947. /* output current serial signal states */
  2948. spin_lock_irqsave(&info->irq_spinlock,flags);
  2949. usc_get_serial_signals(info);
  2950. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  2951. stat_buf[0] = 0;
  2952. stat_buf[1] = 0;
  2953. if (info->serial_signals & SerialSignal_RTS)
  2954. strcat(stat_buf, "|RTS");
  2955. if (info->serial_signals & SerialSignal_CTS)
  2956. strcat(stat_buf, "|CTS");
  2957. if (info->serial_signals & SerialSignal_DTR)
  2958. strcat(stat_buf, "|DTR");
  2959. if (info->serial_signals & SerialSignal_DSR)
  2960. strcat(stat_buf, "|DSR");
  2961. if (info->serial_signals & SerialSignal_DCD)
  2962. strcat(stat_buf, "|CD");
  2963. if (info->serial_signals & SerialSignal_RI)
  2964. strcat(stat_buf, "|RI");
  2965. if (info->params.mode == MGSL_MODE_HDLC ||
  2966. info->params.mode == MGSL_MODE_RAW ) {
  2967. ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
  2968. info->icount.txok, info->icount.rxok);
  2969. if (info->icount.txunder)
  2970. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  2971. if (info->icount.txabort)
  2972. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  2973. if (info->icount.rxshort)
  2974. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  2975. if (info->icount.rxlong)
  2976. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  2977. if (info->icount.rxover)
  2978. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  2979. if (info->icount.rxcrc)
  2980. ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
  2981. } else {
  2982. ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
  2983. info->icount.tx, info->icount.rx);
  2984. if (info->icount.frame)
  2985. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  2986. if (info->icount.parity)
  2987. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  2988. if (info->icount.brk)
  2989. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  2990. if (info->icount.overrun)
  2991. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  2992. }
  2993. /* Append serial signal status to end */
  2994. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  2995. ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2996. info->tx_active,info->bh_requested,info->bh_running,
  2997. info->pending_bh);
  2998. spin_lock_irqsave(&info->irq_spinlock,flags);
  2999. {
  3000. u16 Tcsr = usc_InReg( info, TCSR );
  3001. u16 Tdmr = usc_InDmaReg( info, TDMR );
  3002. u16 Ticr = usc_InReg( info, TICR );
  3003. u16 Rscr = usc_InReg( info, RCSR );
  3004. u16 Rdmr = usc_InDmaReg( info, RDMR );
  3005. u16 Ricr = usc_InReg( info, RICR );
  3006. u16 Icr = usc_InReg( info, ICR );
  3007. u16 Dccr = usc_InReg( info, DCCR );
  3008. u16 Tmr = usc_InReg( info, TMR );
  3009. u16 Tccr = usc_InReg( info, TCCR );
  3010. u16 Ccar = inw( info->io_base + CCAR );
  3011. ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
  3012. "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
  3013. Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
  3014. }
  3015. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  3016. return ret;
  3017. } /* end of line_info() */
  3018. /* mgsl_read_proc()
  3019. *
  3020. * Called to print information about devices
  3021. *
  3022. * Arguments:
  3023. * page page of memory to hold returned info
  3024. * start
  3025. * off
  3026. * count
  3027. * eof
  3028. * data
  3029. *
  3030. * Return Value:
  3031. */
  3032. static int mgsl_read_proc(char *page, char **start, off_t off, int count,
  3033. int *eof, void *data)
  3034. {
  3035. int len = 0, l;
  3036. off_t begin = 0;
  3037. struct mgsl_struct *info;
  3038. len += sprintf(page, "synclink driver:%s\n", driver_version);
  3039. info = mgsl_device_list;
  3040. while( info ) {
  3041. l = line_info(page + len, info);
  3042. len += l;
  3043. if (len+begin > off+count)
  3044. goto done;
  3045. if (len+begin < off) {
  3046. begin += len;
  3047. len = 0;
  3048. }
  3049. info = info->next_device;
  3050. }
  3051. *eof = 1;
  3052. done:
  3053. if (off >= len+begin)
  3054. return 0;
  3055. *start = page + (off-begin);
  3056. return ((count < begin+len-off) ? count : begin+len-off);
  3057. } /* end of mgsl_read_proc() */
  3058. /* mgsl_allocate_dma_buffers()
  3059. *
  3060. * Allocate and format DMA buffers (ISA adapter)
  3061. * or format shared memory buffers (PCI adapter).
  3062. *
  3063. * Arguments: info pointer to device instance data
  3064. * Return Value: 0 if success, otherwise error
  3065. */
  3066. static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
  3067. {
  3068. unsigned short BuffersPerFrame;
  3069. info->last_mem_alloc = 0;
  3070. /* Calculate the number of DMA buffers necessary to hold the */
  3071. /* largest allowable frame size. Note: If the max frame size is */
  3072. /* not an even multiple of the DMA buffer size then we need to */
  3073. /* round the buffer count per frame up one. */
  3074. BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
  3075. if ( info->max_frame_size % DMABUFFERSIZE )
  3076. BuffersPerFrame++;
  3077. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  3078. /*
  3079. * The PCI adapter has 256KBytes of shared memory to use.
  3080. * This is 64 PAGE_SIZE buffers.
  3081. *
  3082. * The first page is used for padding at this time so the
  3083. * buffer list does not begin at offset 0 of the PCI
  3084. * adapter's shared memory.
  3085. *
  3086. * The 2nd page is used for the buffer list. A 4K buffer
  3087. * list can hold 128 DMA_BUFFER structures at 32 bytes
  3088. * each.
  3089. *
  3090. * This leaves 62 4K pages.
  3091. *
  3092. * The next N pages are used for transmit frame(s). We
  3093. * reserve enough 4K page blocks to hold the required
  3094. * number of transmit dma buffers (num_tx_dma_buffers),
  3095. * each of MaxFrameSize size.
  3096. *
  3097. * Of the remaining pages (62-N), determine how many can
  3098. * be used to receive full MaxFrameSize inbound frames
  3099. */
  3100. info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
  3101. info->rx_buffer_count = 62 - info->tx_buffer_count;
  3102. } else {
  3103. /* Calculate the number of PAGE_SIZE buffers needed for */
  3104. /* receive and transmit DMA buffers. */
  3105. /* Calculate the number of DMA buffers necessary to */
  3106. /* hold 7 max size receive frames and one max size transmit frame. */
  3107. /* The receive buffer count is bumped by one so we avoid an */
  3108. /* End of List condition if all receive buffers are used when */
  3109. /* using linked list DMA buffers. */
  3110. info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
  3111. info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
  3112. /*
  3113. * limit total TxBuffers & RxBuffers to 62 4K total
  3114. * (ala PCI Allocation)
  3115. */
  3116. if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
  3117. info->rx_buffer_count = 62 - info->tx_buffer_count;
  3118. }
  3119. if ( debug_level >= DEBUG_LEVEL_INFO )
  3120. printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
  3121. __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
  3122. if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
  3123. mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
  3124. mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
  3125. mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
  3126. mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
  3127. printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
  3128. return -ENOMEM;
  3129. }
  3130. mgsl_reset_rx_dma_buffers( info );
  3131. mgsl_reset_tx_dma_buffers( info );
  3132. return 0;
  3133. } /* end of mgsl_allocate_dma_buffers() */
  3134. /*
  3135. * mgsl_alloc_buffer_list_memory()
  3136. *
  3137. * Allocate a common DMA buffer for use as the
  3138. * receive and transmit buffer lists.
  3139. *
  3140. * A buffer list is a set of buffer entries where each entry contains
  3141. * a pointer to an actual buffer and a pointer to the next buffer entry
  3142. * (plus some other info about the buffer).
  3143. *
  3144. * The buffer entries for a list are built to form a circular list so
  3145. * that when the entire list has been traversed you start back at the
  3146. * beginning.
  3147. *
  3148. * This function allocates memory for just the buffer entries.
  3149. * The links (pointer to next entry) are filled in with the physical
  3150. * address of the next entry so the adapter can navigate the list
  3151. * using bus master DMA. The pointers to the actual buffers are filled
  3152. * out later when the actual buffers are allocated.
  3153. *
  3154. * Arguments: info pointer to device instance data
  3155. * Return Value: 0 if success, otherwise error
  3156. */
  3157. static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
  3158. {
  3159. unsigned int i;
  3160. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  3161. /* PCI adapter uses shared memory. */
  3162. info->buffer_list = info->memory_base + info->last_mem_alloc;
  3163. info->buffer_list_phys = info->last_mem_alloc;
  3164. info->last_mem_alloc += BUFFERLISTSIZE;
  3165. } else {
  3166. /* ISA adapter uses system memory. */
  3167. /* The buffer lists are allocated as a common buffer that both */
  3168. /* the processor and adapter can access. This allows the driver to */
  3169. /* inspect portions of the buffer while other portions are being */
  3170. /* updated by the adapter using Bus Master DMA. */
  3171. info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
  3172. if (info->buffer_list == NULL)
  3173. return -ENOMEM;
  3174. info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
  3175. }
  3176. /* We got the memory for the buffer entry lists. */
  3177. /* Initialize the memory block to all zeros. */
  3178. memset( info->buffer_list, 0, BUFFERLISTSIZE );
  3179. /* Save virtual address pointers to the receive and */
  3180. /* transmit buffer lists. (Receive 1st). These pointers will */
  3181. /* be used by the processor to access the lists. */
  3182. info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
  3183. info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
  3184. info->tx_buffer_list += info->rx_buffer_count;
  3185. /*
  3186. * Build the links for the buffer entry lists such that
  3187. * two circular lists are built. (Transmit and Receive).
  3188. *
  3189. * Note: the links are physical addresses
  3190. * which are read by the adapter to determine the next
  3191. * buffer entry to use.
  3192. */
  3193. for ( i = 0; i < info->rx_buffer_count; i++ ) {
  3194. /* calculate and store physical address of this buffer entry */
  3195. info->rx_buffer_list[i].phys_entry =
  3196. info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
  3197. /* calculate and store physical address of */
  3198. /* next entry in cirular list of entries */
  3199. info->rx_buffer_list[i].link = info->buffer_list_phys;
  3200. if ( i < info->rx_buffer_count - 1 )
  3201. info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
  3202. }
  3203. for ( i = 0; i < info->tx_buffer_count; i++ ) {
  3204. /* calculate and store physical address of this buffer entry */
  3205. info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
  3206. ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
  3207. /* calculate and store physical address of */
  3208. /* next entry in cirular list of entries */
  3209. info->tx_buffer_list[i].link = info->buffer_list_phys +
  3210. info->rx_buffer_count * sizeof(DMABUFFERENTRY);
  3211. if ( i < info->tx_buffer_count - 1 )
  3212. info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
  3213. }
  3214. return 0;
  3215. } /* end of mgsl_alloc_buffer_list_memory() */
  3216. /* Free DMA buffers allocated for use as the
  3217. * receive and transmit buffer lists.
  3218. * Warning:
  3219. *
  3220. * The data transfer buffers associated with the buffer list
  3221. * MUST be freed before freeing the buffer list itself because
  3222. * the buffer list contains the information necessary to free
  3223. * the individual buffers!
  3224. */
  3225. static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
  3226. {
  3227. if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
  3228. dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
  3229. info->buffer_list = NULL;
  3230. info->rx_buffer_list = NULL;
  3231. info->tx_buffer_list = NULL;
  3232. } /* end of mgsl_free_buffer_list_memory() */
  3233. /*
  3234. * mgsl_alloc_frame_memory()
  3235. *
  3236. * Allocate the frame DMA buffers used by the specified buffer list.
  3237. * Each DMA buffer will be one memory page in size. This is necessary
  3238. * because memory can fragment enough that it may be impossible
  3239. * contiguous pages.
  3240. *
  3241. * Arguments:
  3242. *
  3243. * info pointer to device instance data
  3244. * BufferList pointer to list of buffer entries
  3245. * Buffercount count of buffer entries in buffer list
  3246. *
  3247. * Return Value: 0 if success, otherwise -ENOMEM
  3248. */
  3249. static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
  3250. {
  3251. int i;
  3252. u32 phys_addr;
  3253. /* Allocate page sized buffers for the receive buffer list */
  3254. for ( i = 0; i < Buffercount; i++ ) {
  3255. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  3256. /* PCI adapter uses shared memory buffers. */
  3257. BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
  3258. phys_addr = info->last_mem_alloc;
  3259. info->last_mem_alloc += DMABUFFERSIZE;
  3260. } else {
  3261. /* ISA adapter uses system memory. */
  3262. BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
  3263. if (BufferList[i].virt_addr == NULL)
  3264. return -ENOMEM;
  3265. phys_addr = (u32)(BufferList[i].dma_addr);
  3266. }
  3267. BufferList[i].phys_addr = phys_addr;
  3268. }
  3269. return 0;
  3270. } /* end of mgsl_alloc_frame_memory() */
  3271. /*
  3272. * mgsl_free_frame_memory()
  3273. *
  3274. * Free the buffers associated with
  3275. * each buffer entry of a buffer list.
  3276. *
  3277. * Arguments:
  3278. *
  3279. * info pointer to device instance data
  3280. * BufferList pointer to list of buffer entries
  3281. * Buffercount count of buffer entries in buffer list
  3282. *
  3283. * Return Value: None
  3284. */
  3285. static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
  3286. {
  3287. int i;
  3288. if ( BufferList ) {
  3289. for ( i = 0 ; i < Buffercount ; i++ ) {
  3290. if ( BufferList[i].virt_addr ) {
  3291. if ( info->bus_type != MGSL_BUS_TYPE_PCI )
  3292. dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
  3293. BufferList[i].virt_addr = NULL;
  3294. }
  3295. }
  3296. }
  3297. } /* end of mgsl_free_frame_memory() */
  3298. /* mgsl_free_dma_buffers()
  3299. *
  3300. * Free DMA buffers
  3301. *
  3302. * Arguments: info pointer to device instance data
  3303. * Return Value: None
  3304. */
  3305. static void mgsl_free_dma_buffers( struct mgsl_struct *info )
  3306. {
  3307. mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
  3308. mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
  3309. mgsl_free_buffer_list_memory( info );
  3310. } /* end of mgsl_free_dma_buffers() */
  3311. /*
  3312. * mgsl_alloc_intermediate_rxbuffer_memory()
  3313. *
  3314. * Allocate a buffer large enough to hold max_frame_size. This buffer
  3315. * is used to pass an assembled frame to the line discipline.
  3316. *
  3317. * Arguments:
  3318. *
  3319. * info pointer to device instance data
  3320. *
  3321. * Return Value: 0 if success, otherwise -ENOMEM
  3322. */
  3323. static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
  3324. {
  3325. info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
  3326. if ( info->intermediate_rxbuffer == NULL )
  3327. return -ENOMEM;
  3328. return 0;
  3329. } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
  3330. /*
  3331. * mgsl_free_intermediate_rxbuffer_memory()
  3332. *
  3333. *
  3334. * Arguments:
  3335. *
  3336. * info pointer to device instance data
  3337. *
  3338. * Return Value: None
  3339. */
  3340. static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
  3341. {
  3342. kfree(info->intermediate_rxbuffer);
  3343. info->intermediate_rxbuffer = NULL;
  3344. } /* end of mgsl_free_intermediate_rxbuffer_memory() */
  3345. /*
  3346. * mgsl_alloc_intermediate_txbuffer_memory()
  3347. *
  3348. * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
  3349. * This buffer is used to load transmit frames into the adapter's dma transfer
  3350. * buffers when there is sufficient space.
  3351. *
  3352. * Arguments:
  3353. *
  3354. * info pointer to device instance data
  3355. *
  3356. * Return Value: 0 if success, otherwise -ENOMEM
  3357. */
  3358. static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
  3359. {
  3360. int i;
  3361. if ( debug_level >= DEBUG_LEVEL_INFO )
  3362. printk("%s %s(%d) allocating %d tx holding buffers\n",
  3363. info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
  3364. memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
  3365. for ( i=0; i<info->num_tx_holding_buffers; ++i) {
  3366. info->tx_holding_buffers[i].buffer =
  3367. kmalloc(info->max_frame_size, GFP_KERNEL);
  3368. if ( info->tx_holding_buffers[i].buffer == NULL )
  3369. return -ENOMEM;
  3370. }
  3371. return 0;
  3372. } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
  3373. /*
  3374. * mgsl_free_intermediate_txbuffer_memory()
  3375. *
  3376. *
  3377. * Arguments:
  3378. *
  3379. * info pointer to device instance data
  3380. *
  3381. * Return Value: None
  3382. */
  3383. static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
  3384. {
  3385. int i;
  3386. for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
  3387. kfree(info->tx_holding_buffers[i].buffer);
  3388. info->tx_holding_buffers[i].buffer = NULL;
  3389. }
  3390. info->get_tx_holding_index = 0;
  3391. info->put_tx_holding_index = 0;
  3392. info->tx_holding_count = 0;
  3393. } /* end of mgsl_free_intermediate_txbuffer_memory() */
  3394. /*
  3395. * load_next_tx_holding_buffer()
  3396. *
  3397. * attempts to load the next buffered tx request into the
  3398. * tx dma buffers
  3399. *
  3400. * Arguments:
  3401. *
  3402. * info pointer to device instance data
  3403. *
  3404. * Return Value: 1 if next buffered tx request loaded
  3405. * into adapter's tx dma buffer,
  3406. * 0 otherwise
  3407. */
  3408. static int load_next_tx_holding_buffer(struct mgsl_struct *info)
  3409. {
  3410. int ret = 0;
  3411. if ( info->tx_holding_count ) {
  3412. /* determine if we have enough tx dma buffers
  3413. * to accommodate the next tx frame
  3414. */
  3415. struct tx_holding_buffer *ptx =
  3416. &info->tx_holding_buffers[info->get_tx_holding_index];
  3417. int num_free = num_free_tx_dma_buffers(info);
  3418. int num_needed = ptx->buffer_size / DMABUFFERSIZE;
  3419. if ( ptx->buffer_size % DMABUFFERSIZE )
  3420. ++num_needed;
  3421. if (num_needed <= num_free) {
  3422. info->xmit_cnt = ptx->buffer_size;
  3423. mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
  3424. --info->tx_holding_count;
  3425. if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
  3426. info->get_tx_holding_index=0;
  3427. /* restart transmit timer */
  3428. mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
  3429. ret = 1;
  3430. }
  3431. }
  3432. return ret;
  3433. }
  3434. /*
  3435. * save_tx_buffer_request()
  3436. *
  3437. * attempt to store transmit frame request for later transmission
  3438. *
  3439. * Arguments:
  3440. *
  3441. * info pointer to device instance data
  3442. * Buffer pointer to buffer containing frame to load
  3443. * BufferSize size in bytes of frame in Buffer
  3444. *
  3445. * Return Value: 1 if able to store, 0 otherwise
  3446. */
  3447. static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
  3448. {
  3449. struct tx_holding_buffer *ptx;
  3450. if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
  3451. return 0; /* all buffers in use */
  3452. }
  3453. ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
  3454. ptx->buffer_size = BufferSize;
  3455. memcpy( ptx->buffer, Buffer, BufferSize);
  3456. ++info->tx_holding_count;
  3457. if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
  3458. info->put_tx_holding_index=0;
  3459. return 1;
  3460. }
  3461. static int mgsl_claim_resources(struct mgsl_struct *info)
  3462. {
  3463. if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
  3464. printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
  3465. __FILE__,__LINE__,info->device_name, info->io_base);
  3466. return -ENODEV;
  3467. }
  3468. info->io_addr_requested = 1;
  3469. if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
  3470. info->device_name, info ) < 0 ) {
  3471. printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
  3472. __FILE__,__LINE__,info->device_name, info->irq_level );
  3473. goto errout;
  3474. }
  3475. info->irq_requested = 1;
  3476. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  3477. if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
  3478. printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
  3479. __FILE__,__LINE__,info->device_name, info->phys_memory_base);
  3480. goto errout;
  3481. }
  3482. info->shared_mem_requested = 1;
  3483. if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
  3484. printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
  3485. __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
  3486. goto errout;
  3487. }
  3488. info->lcr_mem_requested = 1;
  3489. info->memory_base = ioremap(info->phys_memory_base,0x40000);
  3490. if (!info->memory_base) {
  3491. printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
  3492. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3493. goto errout;
  3494. }
  3495. if ( !mgsl_memory_test(info) ) {
  3496. printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
  3497. __FILE__,__LINE__,info->device_name, info->phys_memory_base );
  3498. goto errout;
  3499. }
  3500. info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
  3501. if (!info->lcr_base) {
  3502. printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
  3503. __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
  3504. goto errout;
  3505. }
  3506. } else {
  3507. /* claim DMA channel */
  3508. if (request_dma(info->dma_level,info->device_name) < 0){
  3509. printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
  3510. __FILE__,__LINE__,info->device_name, info->dma_level );
  3511. mgsl_release_resources( info );
  3512. return -ENODEV;
  3513. }
  3514. info->dma_requested = 1;
  3515. /* ISA adapter uses bus master DMA */
  3516. set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
  3517. enable_dma(info->dma_level);
  3518. }
  3519. if ( mgsl_allocate_dma_buffers(info) < 0 ) {
  3520. printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
  3521. __FILE__,__LINE__,info->device_name, info->dma_level );
  3522. goto errout;
  3523. }
  3524. return 0;
  3525. errout:
  3526. mgsl_release_resources(info);
  3527. return -ENODEV;
  3528. } /* end of mgsl_claim_resources() */
  3529. static void mgsl_release_resources(struct mgsl_struct *info)
  3530. {
  3531. if ( debug_level >= DEBUG_LEVEL_INFO )
  3532. printk( "%s(%d):mgsl_release_resources(%s) entry\n",
  3533. __FILE__,__LINE__,info->device_name );
  3534. if ( info->irq_requested ) {
  3535. free_irq(info->irq_level, info);
  3536. info->irq_requested = 0;
  3537. }
  3538. if ( info->dma_requested ) {
  3539. disable_dma(info->dma_level);
  3540. free_dma(info->dma_level);
  3541. info->dma_requested = 0;
  3542. }
  3543. mgsl_free_dma_buffers(info);
  3544. mgsl_free_intermediate_rxbuffer_memory(info);
  3545. mgsl_free_intermediate_txbuffer_memory(info);
  3546. if ( info->io_addr_requested ) {
  3547. release_region(info->io_base,info->io_addr_size);
  3548. info->io_addr_requested = 0;
  3549. }
  3550. if ( info->shared_mem_requested ) {
  3551. release_mem_region(info->phys_memory_base,0x40000);
  3552. info->shared_mem_requested = 0;
  3553. }
  3554. if ( info->lcr_mem_requested ) {
  3555. release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
  3556. info->lcr_mem_requested = 0;
  3557. }
  3558. if (info->memory_base){
  3559. iounmap(info->memory_base);
  3560. info->memory_base = NULL;
  3561. }
  3562. if (info->lcr_base){
  3563. iounmap(info->lcr_base - info->lcr_offset);
  3564. info->lcr_base = NULL;
  3565. }
  3566. if ( debug_level >= DEBUG_LEVEL_INFO )
  3567. printk( "%s(%d):mgsl_release_resources(%s) exit\n",
  3568. __FILE__,__LINE__,info->device_name );
  3569. } /* end of mgsl_release_resources() */
  3570. /* mgsl_add_device()
  3571. *
  3572. * Add the specified device instance data structure to the
  3573. * global linked list of devices and increment the device count.
  3574. *
  3575. * Arguments: info pointer to device instance data
  3576. * Return Value: None
  3577. */
  3578. static void mgsl_add_device( struct mgsl_struct *info )
  3579. {
  3580. info->next_device = NULL;
  3581. info->line = mgsl_device_count;
  3582. sprintf(info->device_name,"ttySL%d",info->line);
  3583. if (info->line < MAX_TOTAL_DEVICES) {
  3584. if (maxframe[info->line])
  3585. info->max_frame_size = maxframe[info->line];
  3586. info->dosyncppp = dosyncppp[info->line];
  3587. if (txdmabufs[info->line]) {
  3588. info->num_tx_dma_buffers = txdmabufs[info->line];
  3589. if (info->num_tx_dma_buffers < 1)
  3590. info->num_tx_dma_buffers = 1;
  3591. }
  3592. if (txholdbufs[info->line]) {
  3593. info->num_tx_holding_buffers = txholdbufs[info->line];
  3594. if (info->num_tx_holding_buffers < 1)
  3595. info->num_tx_holding_buffers = 1;
  3596. else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
  3597. info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
  3598. }
  3599. }
  3600. mgsl_device_count++;
  3601. if ( !mgsl_device_list )
  3602. mgsl_device_list = info;
  3603. else {
  3604. struct mgsl_struct *current_dev = mgsl_device_list;
  3605. while( current_dev->next_device )
  3606. current_dev = current_dev->next_device;
  3607. current_dev->next_device = info;
  3608. }
  3609. if ( info->max_frame_size < 4096 )
  3610. info->max_frame_size = 4096;
  3611. else if ( info->max_frame_size > 65535 )
  3612. info->max_frame_size = 65535;
  3613. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  3614. printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
  3615. info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
  3616. info->phys_memory_base, info->phys_lcr_base,
  3617. info->max_frame_size );
  3618. } else {
  3619. printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
  3620. info->device_name, info->io_base, info->irq_level, info->dma_level,
  3621. info->max_frame_size );
  3622. }
  3623. #if SYNCLINK_GENERIC_HDLC
  3624. hdlcdev_init(info);
  3625. #endif
  3626. } /* end of mgsl_add_device() */
  3627. /* mgsl_allocate_device()
  3628. *
  3629. * Allocate and initialize a device instance structure
  3630. *
  3631. * Arguments: none
  3632. * Return Value: pointer to mgsl_struct if success, otherwise NULL
  3633. */
  3634. static struct mgsl_struct* mgsl_allocate_device(void)
  3635. {
  3636. struct mgsl_struct *info;
  3637. info = kmalloc(sizeof(struct mgsl_struct),
  3638. GFP_KERNEL);
  3639. if (!info) {
  3640. printk("Error can't allocate device instance data\n");
  3641. } else {
  3642. memset(info, 0, sizeof(struct mgsl_struct));
  3643. info->magic = MGSL_MAGIC;
  3644. INIT_WORK(&info->task, mgsl_bh_handler);
  3645. info->max_frame_size = 4096;
  3646. info->close_delay = 5*HZ/10;
  3647. info->closing_wait = 30*HZ;
  3648. init_waitqueue_head(&info->open_wait);
  3649. init_waitqueue_head(&info->close_wait);
  3650. init_waitqueue_head(&info->status_event_wait_q);
  3651. init_waitqueue_head(&info->event_wait_q);
  3652. spin_lock_init(&info->irq_spinlock);
  3653. spin_lock_init(&info->netlock);
  3654. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  3655. info->idle_mode = HDLC_TXIDLE_FLAGS;
  3656. info->num_tx_dma_buffers = 1;
  3657. info->num_tx_holding_buffers = 0;
  3658. }
  3659. return info;
  3660. } /* end of mgsl_allocate_device()*/
  3661. static const struct tty_operations mgsl_ops = {
  3662. .open = mgsl_open,
  3663. .close = mgsl_close,
  3664. .write = mgsl_write,
  3665. .put_char = mgsl_put_char,
  3666. .flush_chars = mgsl_flush_chars,
  3667. .write_room = mgsl_write_room,
  3668. .chars_in_buffer = mgsl_chars_in_buffer,
  3669. .flush_buffer = mgsl_flush_buffer,
  3670. .ioctl = mgsl_ioctl,
  3671. .throttle = mgsl_throttle,
  3672. .unthrottle = mgsl_unthrottle,
  3673. .send_xchar = mgsl_send_xchar,
  3674. .break_ctl = mgsl_break,
  3675. .wait_until_sent = mgsl_wait_until_sent,
  3676. .read_proc = mgsl_read_proc,
  3677. .set_termios = mgsl_set_termios,
  3678. .stop = mgsl_stop,
  3679. .start = mgsl_start,
  3680. .hangup = mgsl_hangup,
  3681. .tiocmget = tiocmget,
  3682. .tiocmset = tiocmset,
  3683. };
  3684. /*
  3685. * perform tty device initialization
  3686. */
  3687. static int mgsl_init_tty(void)
  3688. {
  3689. int rc;
  3690. serial_driver = alloc_tty_driver(128);
  3691. if (!serial_driver)
  3692. return -ENOMEM;
  3693. serial_driver->owner = THIS_MODULE;
  3694. serial_driver->driver_name = "synclink";
  3695. serial_driver->name = "ttySL";
  3696. serial_driver->major = ttymajor;
  3697. serial_driver->minor_start = 64;
  3698. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  3699. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  3700. serial_driver->init_termios = tty_std_termios;
  3701. serial_driver->init_termios.c_cflag =
  3702. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  3703. serial_driver->init_termios.c_ispeed = 9600;
  3704. serial_driver->init_termios.c_ospeed = 9600;
  3705. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  3706. tty_set_operations(serial_driver, &mgsl_ops);
  3707. if ((rc = tty_register_driver(serial_driver)) < 0) {
  3708. printk("%s(%d):Couldn't register serial driver\n",
  3709. __FILE__,__LINE__);
  3710. put_tty_driver(serial_driver);
  3711. serial_driver = NULL;
  3712. return rc;
  3713. }
  3714. printk("%s %s, tty major#%d\n",
  3715. driver_name, driver_version,
  3716. serial_driver->major);
  3717. return 0;
  3718. }
  3719. /* enumerate user specified ISA adapters
  3720. */
  3721. static void mgsl_enum_isa_devices(void)
  3722. {
  3723. struct mgsl_struct *info;
  3724. int i;
  3725. /* Check for user specified ISA devices */
  3726. for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
  3727. if ( debug_level >= DEBUG_LEVEL_INFO )
  3728. printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
  3729. io[i], irq[i], dma[i] );
  3730. info = mgsl_allocate_device();
  3731. if ( !info ) {
  3732. /* error allocating device instance data */
  3733. if ( debug_level >= DEBUG_LEVEL_ERROR )
  3734. printk( "can't allocate device instance data.\n");
  3735. continue;
  3736. }
  3737. /* Copy user configuration info to device instance data */
  3738. info->io_base = (unsigned int)io[i];
  3739. info->irq_level = (unsigned int)irq[i];
  3740. info->irq_level = irq_canonicalize(info->irq_level);
  3741. info->dma_level = (unsigned int)dma[i];
  3742. info->bus_type = MGSL_BUS_TYPE_ISA;
  3743. info->io_addr_size = 16;
  3744. info->irq_flags = 0;
  3745. mgsl_add_device( info );
  3746. }
  3747. }
  3748. static void synclink_cleanup(void)
  3749. {
  3750. int rc;
  3751. struct mgsl_struct *info;
  3752. struct mgsl_struct *tmp;
  3753. printk("Unloading %s: %s\n", driver_name, driver_version);
  3754. if (serial_driver) {
  3755. if ((rc = tty_unregister_driver(serial_driver)))
  3756. printk("%s(%d) failed to unregister tty driver err=%d\n",
  3757. __FILE__,__LINE__,rc);
  3758. put_tty_driver(serial_driver);
  3759. }
  3760. info = mgsl_device_list;
  3761. while(info) {
  3762. #if SYNCLINK_GENERIC_HDLC
  3763. hdlcdev_exit(info);
  3764. #endif
  3765. mgsl_release_resources(info);
  3766. tmp = info;
  3767. info = info->next_device;
  3768. kfree(tmp);
  3769. }
  3770. if (pci_registered)
  3771. pci_unregister_driver(&synclink_pci_driver);
  3772. }
  3773. static int __init synclink_init(void)
  3774. {
  3775. int rc;
  3776. if (break_on_load) {
  3777. mgsl_get_text_ptr();
  3778. BREAKPOINT();
  3779. }
  3780. printk("%s %s\n", driver_name, driver_version);
  3781. mgsl_enum_isa_devices();
  3782. if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
  3783. printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
  3784. else
  3785. pci_registered = 1;
  3786. if ((rc = mgsl_init_tty()) < 0)
  3787. goto error;
  3788. return 0;
  3789. error:
  3790. synclink_cleanup();
  3791. return rc;
  3792. }
  3793. static void __exit synclink_exit(void)
  3794. {
  3795. synclink_cleanup();
  3796. }
  3797. module_init(synclink_init);
  3798. module_exit(synclink_exit);
  3799. /*
  3800. * usc_RTCmd()
  3801. *
  3802. * Issue a USC Receive/Transmit command to the
  3803. * Channel Command/Address Register (CCAR).
  3804. *
  3805. * Notes:
  3806. *
  3807. * The command is encoded in the most significant 5 bits <15..11>
  3808. * of the CCAR value. Bits <10..7> of the CCAR must be preserved
  3809. * and Bits <6..0> must be written as zeros.
  3810. *
  3811. * Arguments:
  3812. *
  3813. * info pointer to device information structure
  3814. * Cmd command mask (use symbolic macros)
  3815. *
  3816. * Return Value:
  3817. *
  3818. * None
  3819. */
  3820. static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
  3821. {
  3822. /* output command to CCAR in bits <15..11> */
  3823. /* preserve bits <10..7>, bits <6..0> must be zero */
  3824. outw( Cmd + info->loopback_bits, info->io_base + CCAR );
  3825. /* Read to flush write to CCAR */
  3826. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  3827. inw( info->io_base + CCAR );
  3828. } /* end of usc_RTCmd() */
  3829. /*
  3830. * usc_DmaCmd()
  3831. *
  3832. * Issue a DMA command to the DMA Command/Address Register (DCAR).
  3833. *
  3834. * Arguments:
  3835. *
  3836. * info pointer to device information structure
  3837. * Cmd DMA command mask (usc_DmaCmd_XX Macros)
  3838. *
  3839. * Return Value:
  3840. *
  3841. * None
  3842. */
  3843. static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
  3844. {
  3845. /* write command mask to DCAR */
  3846. outw( Cmd + info->mbre_bit, info->io_base );
  3847. /* Read to flush write to DCAR */
  3848. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  3849. inw( info->io_base );
  3850. } /* end of usc_DmaCmd() */
  3851. /*
  3852. * usc_OutDmaReg()
  3853. *
  3854. * Write a 16-bit value to a USC DMA register
  3855. *
  3856. * Arguments:
  3857. *
  3858. * info pointer to device info structure
  3859. * RegAddr register address (number) for write
  3860. * RegValue 16-bit value to write to register
  3861. *
  3862. * Return Value:
  3863. *
  3864. * None
  3865. *
  3866. */
  3867. static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
  3868. {
  3869. /* Note: The DCAR is located at the adapter base address */
  3870. /* Note: must preserve state of BIT8 in DCAR */
  3871. outw( RegAddr + info->mbre_bit, info->io_base );
  3872. outw( RegValue, info->io_base );
  3873. /* Read to flush write to DCAR */
  3874. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  3875. inw( info->io_base );
  3876. } /* end of usc_OutDmaReg() */
  3877. /*
  3878. * usc_InDmaReg()
  3879. *
  3880. * Read a 16-bit value from a DMA register
  3881. *
  3882. * Arguments:
  3883. *
  3884. * info pointer to device info structure
  3885. * RegAddr register address (number) to read from
  3886. *
  3887. * Return Value:
  3888. *
  3889. * The 16-bit value read from register
  3890. *
  3891. */
  3892. static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
  3893. {
  3894. /* Note: The DCAR is located at the adapter base address */
  3895. /* Note: must preserve state of BIT8 in DCAR */
  3896. outw( RegAddr + info->mbre_bit, info->io_base );
  3897. return inw( info->io_base );
  3898. } /* end of usc_InDmaReg() */
  3899. /*
  3900. *
  3901. * usc_OutReg()
  3902. *
  3903. * Write a 16-bit value to a USC serial channel register
  3904. *
  3905. * Arguments:
  3906. *
  3907. * info pointer to device info structure
  3908. * RegAddr register address (number) to write to
  3909. * RegValue 16-bit value to write to register
  3910. *
  3911. * Return Value:
  3912. *
  3913. * None
  3914. *
  3915. */
  3916. static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
  3917. {
  3918. outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
  3919. outw( RegValue, info->io_base + CCAR );
  3920. /* Read to flush write to CCAR */
  3921. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  3922. inw( info->io_base + CCAR );
  3923. } /* end of usc_OutReg() */
  3924. /*
  3925. * usc_InReg()
  3926. *
  3927. * Reads a 16-bit value from a USC serial channel register
  3928. *
  3929. * Arguments:
  3930. *
  3931. * info pointer to device extension
  3932. * RegAddr register address (number) to read from
  3933. *
  3934. * Return Value:
  3935. *
  3936. * 16-bit value read from register
  3937. */
  3938. static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
  3939. {
  3940. outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
  3941. return inw( info->io_base + CCAR );
  3942. } /* end of usc_InReg() */
  3943. /* usc_set_sdlc_mode()
  3944. *
  3945. * Set up the adapter for SDLC DMA communications.
  3946. *
  3947. * Arguments: info pointer to device instance data
  3948. * Return Value: NONE
  3949. */
  3950. static void usc_set_sdlc_mode( struct mgsl_struct *info )
  3951. {
  3952. u16 RegValue;
  3953. int PreSL1660;
  3954. /*
  3955. * determine if the IUSC on the adapter is pre-SL1660. If
  3956. * not, take advantage of the UnderWait feature of more
  3957. * modern chips. If an underrun occurs and this bit is set,
  3958. * the transmitter will idle the programmed idle pattern
  3959. * until the driver has time to service the underrun. Otherwise,
  3960. * the dma controller may get the cycles previously requested
  3961. * and begin transmitting queued tx data.
  3962. */
  3963. usc_OutReg(info,TMCR,0x1f);
  3964. RegValue=usc_InReg(info,TMDR);
  3965. if ( RegValue == IUSC_PRE_SL1660 )
  3966. PreSL1660 = 1;
  3967. else
  3968. PreSL1660 = 0;
  3969. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  3970. {
  3971. /*
  3972. ** Channel Mode Register (CMR)
  3973. **
  3974. ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
  3975. ** <13> 0 0 = Transmit Disabled (initially)
  3976. ** <12> 0 1 = Consecutive Idles share common 0
  3977. ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
  3978. ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
  3979. ** <3..0> 0110 Receiver Mode = HDLC/SDLC
  3980. **
  3981. ** 1000 1110 0000 0110 = 0x8e06
  3982. */
  3983. RegValue = 0x8e06;
  3984. /*--------------------------------------------------
  3985. * ignore user options for UnderRun Actions and
  3986. * preambles
  3987. *--------------------------------------------------*/
  3988. }
  3989. else
  3990. {
  3991. /* Channel mode Register (CMR)
  3992. *
  3993. * <15..14> 00 Tx Sub modes, Underrun Action
  3994. * <13> 0 1 = Send Preamble before opening flag
  3995. * <12> 0 1 = Consecutive Idles share common 0
  3996. * <11..8> 0110 Transmitter mode = HDLC/SDLC
  3997. * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
  3998. * <3..0> 0110 Receiver mode = HDLC/SDLC
  3999. *
  4000. * 0000 0110 0000 0110 = 0x0606
  4001. */
  4002. if (info->params.mode == MGSL_MODE_RAW) {
  4003. RegValue = 0x0001; /* Set Receive mode = external sync */
  4004. usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
  4005. (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
  4006. /*
  4007. * TxSubMode:
  4008. * CMR <15> 0 Don't send CRC on Tx Underrun
  4009. * CMR <14> x undefined
  4010. * CMR <13> 0 Send preamble before openning sync
  4011. * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
  4012. *
  4013. * TxMode:
  4014. * CMR <11-8) 0100 MonoSync
  4015. *
  4016. * 0x00 0100 xxxx xxxx 04xx
  4017. */
  4018. RegValue |= 0x0400;
  4019. }
  4020. else {
  4021. RegValue = 0x0606;
  4022. if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
  4023. RegValue |= BIT14;
  4024. else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
  4025. RegValue |= BIT15;
  4026. else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
  4027. RegValue |= BIT15 + BIT14;
  4028. }
  4029. if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
  4030. RegValue |= BIT13;
  4031. }
  4032. if ( info->params.mode == MGSL_MODE_HDLC &&
  4033. (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
  4034. RegValue |= BIT12;
  4035. if ( info->params.addr_filter != 0xff )
  4036. {
  4037. /* set up receive address filtering */
  4038. usc_OutReg( info, RSR, info->params.addr_filter );
  4039. RegValue |= BIT4;
  4040. }
  4041. usc_OutReg( info, CMR, RegValue );
  4042. info->cmr_value = RegValue;
  4043. /* Receiver mode Register (RMR)
  4044. *
  4045. * <15..13> 000 encoding
  4046. * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
  4047. * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
  4048. * <9> 0 1 = Include Receive chars in CRC
  4049. * <8> 1 1 = Use Abort/PE bit as abort indicator
  4050. * <7..6> 00 Even parity
  4051. * <5> 0 parity disabled
  4052. * <4..2> 000 Receive Char Length = 8 bits
  4053. * <1..0> 00 Disable Receiver
  4054. *
  4055. * 0000 0101 0000 0000 = 0x0500
  4056. */
  4057. RegValue = 0x0500;
  4058. switch ( info->params.encoding ) {
  4059. case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
  4060. case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
  4061. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
  4062. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
  4063. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
  4064. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
  4065. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
  4066. }
  4067. if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
  4068. RegValue |= BIT9;
  4069. else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
  4070. RegValue |= ( BIT12 | BIT10 | BIT9 );
  4071. usc_OutReg( info, RMR, RegValue );
  4072. /* Set the Receive count Limit Register (RCLR) to 0xffff. */
  4073. /* When an opening flag of an SDLC frame is recognized the */
  4074. /* Receive Character count (RCC) is loaded with the value in */
  4075. /* RCLR. The RCC is decremented for each received byte. The */
  4076. /* value of RCC is stored after the closing flag of the frame */
  4077. /* allowing the frame size to be computed. */
  4078. usc_OutReg( info, RCLR, RCLRVALUE );
  4079. usc_RCmd( info, RCmd_SelectRicrdma_level );
  4080. /* Receive Interrupt Control Register (RICR)
  4081. *
  4082. * <15..8> ? RxFIFO DMA Request Level
  4083. * <7> 0 Exited Hunt IA (Interrupt Arm)
  4084. * <6> 0 Idle Received IA
  4085. * <5> 0 Break/Abort IA
  4086. * <4> 0 Rx Bound IA
  4087. * <3> 1 Queued status reflects oldest 2 bytes in FIFO
  4088. * <2> 0 Abort/PE IA
  4089. * <1> 1 Rx Overrun IA
  4090. * <0> 0 Select TC0 value for readback
  4091. *
  4092. * 0000 0000 0000 1000 = 0x000a
  4093. */
  4094. /* Carry over the Exit Hunt and Idle Received bits */
  4095. /* in case they have been armed by usc_ArmEvents. */
  4096. RegValue = usc_InReg( info, RICR ) & 0xc0;
  4097. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  4098. usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
  4099. else
  4100. usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
  4101. /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
  4102. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4103. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  4104. /* Transmit mode Register (TMR)
  4105. *
  4106. * <15..13> 000 encoding
  4107. * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
  4108. * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
  4109. * <9> 0 1 = Tx CRC Enabled
  4110. * <8> 0 1 = Append CRC to end of transmit frame
  4111. * <7..6> 00 Transmit parity Even
  4112. * <5> 0 Transmit parity Disabled
  4113. * <4..2> 000 Tx Char Length = 8 bits
  4114. * <1..0> 00 Disable Transmitter
  4115. *
  4116. * 0000 0100 0000 0000 = 0x0400
  4117. */
  4118. RegValue = 0x0400;
  4119. switch ( info->params.encoding ) {
  4120. case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
  4121. case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
  4122. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
  4123. case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
  4124. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
  4125. case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
  4126. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
  4127. }
  4128. if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
  4129. RegValue |= BIT9 + BIT8;
  4130. else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
  4131. RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
  4132. usc_OutReg( info, TMR, RegValue );
  4133. usc_set_txidle( info );
  4134. usc_TCmd( info, TCmd_SelectTicrdma_level );
  4135. /* Transmit Interrupt Control Register (TICR)
  4136. *
  4137. * <15..8> ? Transmit FIFO DMA Level
  4138. * <7> 0 Present IA (Interrupt Arm)
  4139. * <6> 0 Idle Sent IA
  4140. * <5> 1 Abort Sent IA
  4141. * <4> 1 EOF/EOM Sent IA
  4142. * <3> 0 CRC Sent IA
  4143. * <2> 1 1 = Wait for SW Trigger to Start Frame
  4144. * <1> 1 Tx Underrun IA
  4145. * <0> 0 TC0 constant on read back
  4146. *
  4147. * 0000 0000 0011 0110 = 0x0036
  4148. */
  4149. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  4150. usc_OutReg( info, TICR, 0x0736 );
  4151. else
  4152. usc_OutReg( info, TICR, 0x1436 );
  4153. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4154. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  4155. /*
  4156. ** Transmit Command/Status Register (TCSR)
  4157. **
  4158. ** <15..12> 0000 TCmd
  4159. ** <11> 0/1 UnderWait
  4160. ** <10..08> 000 TxIdle
  4161. ** <7> x PreSent
  4162. ** <6> x IdleSent
  4163. ** <5> x AbortSent
  4164. ** <4> x EOF/EOM Sent
  4165. ** <3> x CRC Sent
  4166. ** <2> x All Sent
  4167. ** <1> x TxUnder
  4168. ** <0> x TxEmpty
  4169. **
  4170. ** 0000 0000 0000 0000 = 0x0000
  4171. */
  4172. info->tcsr_value = 0;
  4173. if ( !PreSL1660 )
  4174. info->tcsr_value |= TCSR_UNDERWAIT;
  4175. usc_OutReg( info, TCSR, info->tcsr_value );
  4176. /* Clock mode Control Register (CMCR)
  4177. *
  4178. * <15..14> 00 counter 1 Source = Disabled
  4179. * <13..12> 00 counter 0 Source = Disabled
  4180. * <11..10> 11 BRG1 Input is TxC Pin
  4181. * <9..8> 11 BRG0 Input is TxC Pin
  4182. * <7..6> 01 DPLL Input is BRG1 Output
  4183. * <5..3> XXX TxCLK comes from Port 0
  4184. * <2..0> XXX RxCLK comes from Port 1
  4185. *
  4186. * 0000 1111 0111 0111 = 0x0f77
  4187. */
  4188. RegValue = 0x0f40;
  4189. if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
  4190. RegValue |= 0x0003; /* RxCLK from DPLL */
  4191. else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
  4192. RegValue |= 0x0004; /* RxCLK from BRG0 */
  4193. else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
  4194. RegValue |= 0x0006; /* RxCLK from TXC Input */
  4195. else
  4196. RegValue |= 0x0007; /* RxCLK from Port1 */
  4197. if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
  4198. RegValue |= 0x0018; /* TxCLK from DPLL */
  4199. else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
  4200. RegValue |= 0x0020; /* TxCLK from BRG0 */
  4201. else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
  4202. RegValue |= 0x0038; /* RxCLK from TXC Input */
  4203. else
  4204. RegValue |= 0x0030; /* TxCLK from Port0 */
  4205. usc_OutReg( info, CMCR, RegValue );
  4206. /* Hardware Configuration Register (HCR)
  4207. *
  4208. * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
  4209. * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
  4210. * <12> 0 CVOK:0=report code violation in biphase
  4211. * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
  4212. * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
  4213. * <7..6> 00 reserved
  4214. * <5> 0 BRG1 mode:0=continuous,1=single cycle
  4215. * <4> X BRG1 Enable
  4216. * <3..2> 00 reserved
  4217. * <1> 0 BRG0 mode:0=continuous,1=single cycle
  4218. * <0> 0 BRG0 Enable
  4219. */
  4220. RegValue = 0x0000;
  4221. if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
  4222. u32 XtalSpeed;
  4223. u32 DpllDivisor;
  4224. u16 Tc;
  4225. /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
  4226. /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
  4227. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  4228. XtalSpeed = 11059200;
  4229. else
  4230. XtalSpeed = 14745600;
  4231. if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
  4232. DpllDivisor = 16;
  4233. RegValue |= BIT10;
  4234. }
  4235. else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
  4236. DpllDivisor = 8;
  4237. RegValue |= BIT11;
  4238. }
  4239. else
  4240. DpllDivisor = 32;
  4241. /* Tc = (Xtal/Speed) - 1 */
  4242. /* If twice the remainder of (Xtal/Speed) is greater than Speed */
  4243. /* then rounding up gives a more precise time constant. Instead */
  4244. /* of rounding up and then subtracting 1 we just don't subtract */
  4245. /* the one in this case. */
  4246. /*--------------------------------------------------
  4247. * ejz: for DPLL mode, application should use the
  4248. * same clock speed as the partner system, even
  4249. * though clocking is derived from the input RxData.
  4250. * In case the user uses a 0 for the clock speed,
  4251. * default to 0xffffffff and don't try to divide by
  4252. * zero
  4253. *--------------------------------------------------*/
  4254. if ( info->params.clock_speed )
  4255. {
  4256. Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
  4257. if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
  4258. / info->params.clock_speed) )
  4259. Tc--;
  4260. }
  4261. else
  4262. Tc = -1;
  4263. /* Write 16-bit Time Constant for BRG1 */
  4264. usc_OutReg( info, TC1R, Tc );
  4265. RegValue |= BIT4; /* enable BRG1 */
  4266. switch ( info->params.encoding ) {
  4267. case HDLC_ENCODING_NRZ:
  4268. case HDLC_ENCODING_NRZB:
  4269. case HDLC_ENCODING_NRZI_MARK:
  4270. case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
  4271. case HDLC_ENCODING_BIPHASE_MARK:
  4272. case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
  4273. case HDLC_ENCODING_BIPHASE_LEVEL:
  4274. case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
  4275. }
  4276. }
  4277. usc_OutReg( info, HCR, RegValue );
  4278. /* Channel Control/status Register (CCSR)
  4279. *
  4280. * <15> X RCC FIFO Overflow status (RO)
  4281. * <14> X RCC FIFO Not Empty status (RO)
  4282. * <13> 0 1 = Clear RCC FIFO (WO)
  4283. * <12> X DPLL Sync (RW)
  4284. * <11> X DPLL 2 Missed Clocks status (RO)
  4285. * <10> X DPLL 1 Missed Clock status (RO)
  4286. * <9..8> 00 DPLL Resync on rising and falling edges (RW)
  4287. * <7> X SDLC Loop On status (RO)
  4288. * <6> X SDLC Loop Send status (RO)
  4289. * <5> 1 Bypass counters for TxClk and RxClk (RW)
  4290. * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
  4291. * <1..0> 00 reserved
  4292. *
  4293. * 0000 0000 0010 0000 = 0x0020
  4294. */
  4295. usc_OutReg( info, CCSR, 0x1020 );
  4296. if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
  4297. usc_OutReg( info, SICR,
  4298. (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
  4299. }
  4300. /* enable Master Interrupt Enable bit (MIE) */
  4301. usc_EnableMasterIrqBit( info );
  4302. usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
  4303. TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
  4304. /* arm RCC underflow interrupt */
  4305. usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
  4306. usc_EnableInterrupts(info, MISC);
  4307. info->mbre_bit = 0;
  4308. outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
  4309. usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
  4310. info->mbre_bit = BIT8;
  4311. outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
  4312. if (info->bus_type == MGSL_BUS_TYPE_ISA) {
  4313. /* Enable DMAEN (Port 7, Bit 14) */
  4314. /* This connects the DMA request signal to the ISA bus */
  4315. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
  4316. }
  4317. /* DMA Control Register (DCR)
  4318. *
  4319. * <15..14> 10 Priority mode = Alternating Tx/Rx
  4320. * 01 Rx has priority
  4321. * 00 Tx has priority
  4322. *
  4323. * <13> 1 Enable Priority Preempt per DCR<15..14>
  4324. * (WARNING DCR<11..10> must be 00 when this is 1)
  4325. * 0 Choose activate channel per DCR<11..10>
  4326. *
  4327. * <12> 0 Little Endian for Array/List
  4328. * <11..10> 00 Both Channels can use each bus grant
  4329. * <9..6> 0000 reserved
  4330. * <5> 0 7 CLK - Minimum Bus Re-request Interval
  4331. * <4> 0 1 = drive D/C and S/D pins
  4332. * <3> 1 1 = Add one wait state to all DMA cycles.
  4333. * <2> 0 1 = Strobe /UAS on every transfer.
  4334. * <1..0> 11 Addr incrementing only affects LS24 bits
  4335. *
  4336. * 0110 0000 0000 1011 = 0x600b
  4337. */
  4338. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  4339. /* PCI adapter does not need DMA wait state */
  4340. usc_OutDmaReg( info, DCR, 0xa00b );
  4341. }
  4342. else
  4343. usc_OutDmaReg( info, DCR, 0x800b );
  4344. /* Receive DMA mode Register (RDMR)
  4345. *
  4346. * <15..14> 11 DMA mode = Linked List Buffer mode
  4347. * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
  4348. * <12> 1 Clear count of List Entry after fetching
  4349. * <11..10> 00 Address mode = Increment
  4350. * <9> 1 Terminate Buffer on RxBound
  4351. * <8> 0 Bus Width = 16bits
  4352. * <7..0> ? status Bits (write as 0s)
  4353. *
  4354. * 1111 0010 0000 0000 = 0xf200
  4355. */
  4356. usc_OutDmaReg( info, RDMR, 0xf200 );
  4357. /* Transmit DMA mode Register (TDMR)
  4358. *
  4359. * <15..14> 11 DMA mode = Linked List Buffer mode
  4360. * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
  4361. * <12> 1 Clear count of List Entry after fetching
  4362. * <11..10> 00 Address mode = Increment
  4363. * <9> 1 Terminate Buffer on end of frame
  4364. * <8> 0 Bus Width = 16bits
  4365. * <7..0> ? status Bits (Read Only so write as 0)
  4366. *
  4367. * 1111 0010 0000 0000 = 0xf200
  4368. */
  4369. usc_OutDmaReg( info, TDMR, 0xf200 );
  4370. /* DMA Interrupt Control Register (DICR)
  4371. *
  4372. * <15> 1 DMA Interrupt Enable
  4373. * <14> 0 1 = Disable IEO from USC
  4374. * <13> 0 1 = Don't provide vector during IntAck
  4375. * <12> 1 1 = Include status in Vector
  4376. * <10..2> 0 reserved, Must be 0s
  4377. * <1> 0 1 = Rx DMA Interrupt Enabled
  4378. * <0> 0 1 = Tx DMA Interrupt Enabled
  4379. *
  4380. * 1001 0000 0000 0000 = 0x9000
  4381. */
  4382. usc_OutDmaReg( info, DICR, 0x9000 );
  4383. usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
  4384. usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
  4385. usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
  4386. /* Channel Control Register (CCR)
  4387. *
  4388. * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
  4389. * <13> 0 Trigger Tx on SW Command Disabled
  4390. * <12> 0 Flag Preamble Disabled
  4391. * <11..10> 00 Preamble Length
  4392. * <9..8> 00 Preamble Pattern
  4393. * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
  4394. * <5> 0 Trigger Rx on SW Command Disabled
  4395. * <4..0> 0 reserved
  4396. *
  4397. * 1000 0000 1000 0000 = 0x8080
  4398. */
  4399. RegValue = 0x8080;
  4400. switch ( info->params.preamble_length ) {
  4401. case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
  4402. case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
  4403. case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
  4404. }
  4405. switch ( info->params.preamble ) {
  4406. case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
  4407. case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
  4408. case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
  4409. case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
  4410. }
  4411. usc_OutReg( info, CCR, RegValue );
  4412. /*
  4413. * Burst/Dwell Control Register
  4414. *
  4415. * <15..8> 0x20 Maximum number of transfers per bus grant
  4416. * <7..0> 0x00 Maximum number of clock cycles per bus grant
  4417. */
  4418. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  4419. /* don't limit bus occupancy on PCI adapter */
  4420. usc_OutDmaReg( info, BDCR, 0x0000 );
  4421. }
  4422. else
  4423. usc_OutDmaReg( info, BDCR, 0x2000 );
  4424. usc_stop_transmitter(info);
  4425. usc_stop_receiver(info);
  4426. } /* end of usc_set_sdlc_mode() */
  4427. /* usc_enable_loopback()
  4428. *
  4429. * Set the 16C32 for internal loopback mode.
  4430. * The TxCLK and RxCLK signals are generated from the BRG0 and
  4431. * the TxD is looped back to the RxD internally.
  4432. *
  4433. * Arguments: info pointer to device instance data
  4434. * enable 1 = enable loopback, 0 = disable
  4435. * Return Value: None
  4436. */
  4437. static void usc_enable_loopback(struct mgsl_struct *info, int enable)
  4438. {
  4439. if (enable) {
  4440. /* blank external TXD output */
  4441. usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
  4442. /* Clock mode Control Register (CMCR)
  4443. *
  4444. * <15..14> 00 counter 1 Disabled
  4445. * <13..12> 00 counter 0 Disabled
  4446. * <11..10> 11 BRG1 Input is TxC Pin
  4447. * <9..8> 11 BRG0 Input is TxC Pin
  4448. * <7..6> 01 DPLL Input is BRG1 Output
  4449. * <5..3> 100 TxCLK comes from BRG0
  4450. * <2..0> 100 RxCLK comes from BRG0
  4451. *
  4452. * 0000 1111 0110 0100 = 0x0f64
  4453. */
  4454. usc_OutReg( info, CMCR, 0x0f64 );
  4455. /* Write 16-bit Time Constant for BRG0 */
  4456. /* use clock speed if available, otherwise use 8 for diagnostics */
  4457. if (info->params.clock_speed) {
  4458. if (info->bus_type == MGSL_BUS_TYPE_PCI)
  4459. usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
  4460. else
  4461. usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
  4462. } else
  4463. usc_OutReg(info, TC0R, (u16)8);
  4464. /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
  4465. mode = Continuous Set Bit 0 to enable BRG0. */
  4466. usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  4467. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  4468. usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
  4469. /* set Internal Data loopback mode */
  4470. info->loopback_bits = 0x300;
  4471. outw( 0x0300, info->io_base + CCAR );
  4472. } else {
  4473. /* enable external TXD output */
  4474. usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
  4475. /* clear Internal Data loopback mode */
  4476. info->loopback_bits = 0;
  4477. outw( 0,info->io_base + CCAR );
  4478. }
  4479. } /* end of usc_enable_loopback() */
  4480. /* usc_enable_aux_clock()
  4481. *
  4482. * Enabled the AUX clock output at the specified frequency.
  4483. *
  4484. * Arguments:
  4485. *
  4486. * info pointer to device extension
  4487. * data_rate data rate of clock in bits per second
  4488. * A data rate of 0 disables the AUX clock.
  4489. *
  4490. * Return Value: None
  4491. */
  4492. static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
  4493. {
  4494. u32 XtalSpeed;
  4495. u16 Tc;
  4496. if ( data_rate ) {
  4497. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  4498. XtalSpeed = 11059200;
  4499. else
  4500. XtalSpeed = 14745600;
  4501. /* Tc = (Xtal/Speed) - 1 */
  4502. /* If twice the remainder of (Xtal/Speed) is greater than Speed */
  4503. /* then rounding up gives a more precise time constant. Instead */
  4504. /* of rounding up and then subtracting 1 we just don't subtract */
  4505. /* the one in this case. */
  4506. Tc = (u16)(XtalSpeed/data_rate);
  4507. if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
  4508. Tc--;
  4509. /* Write 16-bit Time Constant for BRG0 */
  4510. usc_OutReg( info, TC0R, Tc );
  4511. /*
  4512. * Hardware Configuration Register (HCR)
  4513. * Clear Bit 1, BRG0 mode = Continuous
  4514. * Set Bit 0 to enable BRG0.
  4515. */
  4516. usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  4517. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  4518. usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
  4519. } else {
  4520. /* data rate == 0 so turn off BRG0 */
  4521. usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
  4522. }
  4523. } /* end of usc_enable_aux_clock() */
  4524. /*
  4525. *
  4526. * usc_process_rxoverrun_sync()
  4527. *
  4528. * This function processes a receive overrun by resetting the
  4529. * receive DMA buffers and issuing a Purge Rx FIFO command
  4530. * to allow the receiver to continue receiving.
  4531. *
  4532. * Arguments:
  4533. *
  4534. * info pointer to device extension
  4535. *
  4536. * Return Value: None
  4537. */
  4538. static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
  4539. {
  4540. int start_index;
  4541. int end_index;
  4542. int frame_start_index;
  4543. int start_of_frame_found = FALSE;
  4544. int end_of_frame_found = FALSE;
  4545. int reprogram_dma = FALSE;
  4546. DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
  4547. u32 phys_addr;
  4548. usc_DmaCmd( info, DmaCmd_PauseRxChannel );
  4549. usc_RCmd( info, RCmd_EnterHuntmode );
  4550. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4551. /* CurrentRxBuffer points to the 1st buffer of the next */
  4552. /* possibly available receive frame. */
  4553. frame_start_index = start_index = end_index = info->current_rx_buffer;
  4554. /* Search for an unfinished string of buffers. This means */
  4555. /* that a receive frame started (at least one buffer with */
  4556. /* count set to zero) but there is no terminiting buffer */
  4557. /* (status set to non-zero). */
  4558. while( !buffer_list[end_index].count )
  4559. {
  4560. /* Count field has been reset to zero by 16C32. */
  4561. /* This buffer is currently in use. */
  4562. if ( !start_of_frame_found )
  4563. {
  4564. start_of_frame_found = TRUE;
  4565. frame_start_index = end_index;
  4566. end_of_frame_found = FALSE;
  4567. }
  4568. if ( buffer_list[end_index].status )
  4569. {
  4570. /* Status field has been set by 16C32. */
  4571. /* This is the last buffer of a received frame. */
  4572. /* We want to leave the buffers for this frame intact. */
  4573. /* Move on to next possible frame. */
  4574. start_of_frame_found = FALSE;
  4575. end_of_frame_found = TRUE;
  4576. }
  4577. /* advance to next buffer entry in linked list */
  4578. end_index++;
  4579. if ( end_index == info->rx_buffer_count )
  4580. end_index = 0;
  4581. if ( start_index == end_index )
  4582. {
  4583. /* The entire list has been searched with all Counts == 0 and */
  4584. /* all Status == 0. The receive buffers are */
  4585. /* completely screwed, reset all receive buffers! */
  4586. mgsl_reset_rx_dma_buffers( info );
  4587. frame_start_index = 0;
  4588. start_of_frame_found = FALSE;
  4589. reprogram_dma = TRUE;
  4590. break;
  4591. }
  4592. }
  4593. if ( start_of_frame_found && !end_of_frame_found )
  4594. {
  4595. /* There is an unfinished string of receive DMA buffers */
  4596. /* as a result of the receiver overrun. */
  4597. /* Reset the buffers for the unfinished frame */
  4598. /* and reprogram the receive DMA controller to start */
  4599. /* at the 1st buffer of unfinished frame. */
  4600. start_index = frame_start_index;
  4601. do
  4602. {
  4603. *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
  4604. /* Adjust index for wrap around. */
  4605. if ( start_index == info->rx_buffer_count )
  4606. start_index = 0;
  4607. } while( start_index != end_index );
  4608. reprogram_dma = TRUE;
  4609. }
  4610. if ( reprogram_dma )
  4611. {
  4612. usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
  4613. usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
  4614. usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
  4615. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  4616. /* This empties the receive FIFO and loads the RCC with RCLR */
  4617. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4618. /* program 16C32 with physical address of 1st DMA buffer entry */
  4619. phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
  4620. usc_OutDmaReg( info, NRARL, (u16)phys_addr );
  4621. usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
  4622. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4623. usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
  4624. usc_EnableInterrupts( info, RECEIVE_STATUS );
  4625. /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
  4626. /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
  4627. usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
  4628. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
  4629. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  4630. if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
  4631. usc_EnableReceiver(info,ENABLE_AUTO_DCD);
  4632. else
  4633. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4634. }
  4635. else
  4636. {
  4637. /* This empties the receive FIFO and loads the RCC with RCLR */
  4638. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4639. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4640. }
  4641. } /* end of usc_process_rxoverrun_sync() */
  4642. /* usc_stop_receiver()
  4643. *
  4644. * Disable USC receiver
  4645. *
  4646. * Arguments: info pointer to device instance data
  4647. * Return Value: None
  4648. */
  4649. static void usc_stop_receiver( struct mgsl_struct *info )
  4650. {
  4651. if (debug_level >= DEBUG_LEVEL_ISR)
  4652. printk("%s(%d):usc_stop_receiver(%s)\n",
  4653. __FILE__,__LINE__, info->device_name );
  4654. /* Disable receive DMA channel. */
  4655. /* This also disables receive DMA channel interrupts */
  4656. usc_DmaCmd( info, DmaCmd_ResetRxChannel );
  4657. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4658. usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
  4659. usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
  4660. usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
  4661. /* This empties the receive FIFO and loads the RCC with RCLR */
  4662. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4663. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4664. info->rx_enabled = 0;
  4665. info->rx_overflow = 0;
  4666. info->rx_rcc_underrun = 0;
  4667. } /* end of stop_receiver() */
  4668. /* usc_start_receiver()
  4669. *
  4670. * Enable the USC receiver
  4671. *
  4672. * Arguments: info pointer to device instance data
  4673. * Return Value: None
  4674. */
  4675. static void usc_start_receiver( struct mgsl_struct *info )
  4676. {
  4677. u32 phys_addr;
  4678. if (debug_level >= DEBUG_LEVEL_ISR)
  4679. printk("%s(%d):usc_start_receiver(%s)\n",
  4680. __FILE__,__LINE__, info->device_name );
  4681. mgsl_reset_rx_dma_buffers( info );
  4682. usc_stop_receiver( info );
  4683. usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
  4684. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4685. if ( info->params.mode == MGSL_MODE_HDLC ||
  4686. info->params.mode == MGSL_MODE_RAW ) {
  4687. /* DMA mode Transfers */
  4688. /* Program the DMA controller. */
  4689. /* Enable the DMA controller end of buffer interrupt. */
  4690. /* program 16C32 with physical address of 1st DMA buffer entry */
  4691. phys_addr = info->rx_buffer_list[0].phys_entry;
  4692. usc_OutDmaReg( info, NRARL, (u16)phys_addr );
  4693. usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
  4694. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  4695. usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
  4696. usc_EnableInterrupts( info, RECEIVE_STATUS );
  4697. /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
  4698. /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
  4699. usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
  4700. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
  4701. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  4702. if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
  4703. usc_EnableReceiver(info,ENABLE_AUTO_DCD);
  4704. else
  4705. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4706. } else {
  4707. usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
  4708. usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
  4709. usc_EnableInterrupts(info, RECEIVE_DATA);
  4710. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  4711. usc_RCmd( info, RCmd_EnterHuntmode );
  4712. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  4713. }
  4714. usc_OutReg( info, CCSR, 0x1020 );
  4715. info->rx_enabled = 1;
  4716. } /* end of usc_start_receiver() */
  4717. /* usc_start_transmitter()
  4718. *
  4719. * Enable the USC transmitter and send a transmit frame if
  4720. * one is loaded in the DMA buffers.
  4721. *
  4722. * Arguments: info pointer to device instance data
  4723. * Return Value: None
  4724. */
  4725. static void usc_start_transmitter( struct mgsl_struct *info )
  4726. {
  4727. u32 phys_addr;
  4728. unsigned int FrameSize;
  4729. if (debug_level >= DEBUG_LEVEL_ISR)
  4730. printk("%s(%d):usc_start_transmitter(%s)\n",
  4731. __FILE__,__LINE__, info->device_name );
  4732. if ( info->xmit_cnt ) {
  4733. /* If auto RTS enabled and RTS is inactive, then assert */
  4734. /* RTS and set a flag indicating that the driver should */
  4735. /* negate RTS when the transmission completes. */
  4736. info->drop_rts_on_tx_done = 0;
  4737. if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
  4738. usc_get_serial_signals( info );
  4739. if ( !(info->serial_signals & SerialSignal_RTS) ) {
  4740. info->serial_signals |= SerialSignal_RTS;
  4741. usc_set_serial_signals( info );
  4742. info->drop_rts_on_tx_done = 1;
  4743. }
  4744. }
  4745. if ( info->params.mode == MGSL_MODE_ASYNC ) {
  4746. if ( !info->tx_active ) {
  4747. usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
  4748. usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
  4749. usc_EnableInterrupts(info, TRANSMIT_DATA);
  4750. usc_load_txfifo(info);
  4751. }
  4752. } else {
  4753. /* Disable transmit DMA controller while programming. */
  4754. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  4755. /* Transmit DMA buffer is loaded, so program USC */
  4756. /* to send the frame contained in the buffers. */
  4757. FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
  4758. /* if operating in Raw sync mode, reset the rcc component
  4759. * of the tx dma buffer entry, otherwise, the serial controller
  4760. * will send a closing sync char after this count.
  4761. */
  4762. if ( info->params.mode == MGSL_MODE_RAW )
  4763. info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
  4764. /* Program the Transmit Character Length Register (TCLR) */
  4765. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  4766. usc_OutReg( info, TCLR, (u16)FrameSize );
  4767. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  4768. /* Program the address of the 1st DMA Buffer Entry in linked list */
  4769. phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
  4770. usc_OutDmaReg( info, NTARL, (u16)phys_addr );
  4771. usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
  4772. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4773. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  4774. usc_EnableInterrupts( info, TRANSMIT_STATUS );
  4775. if ( info->params.mode == MGSL_MODE_RAW &&
  4776. info->num_tx_dma_buffers > 1 ) {
  4777. /* When running external sync mode, attempt to 'stream' transmit */
  4778. /* by filling tx dma buffers as they become available. To do this */
  4779. /* we need to enable Tx DMA EOB Status interrupts : */
  4780. /* */
  4781. /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
  4782. /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
  4783. usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
  4784. usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
  4785. }
  4786. /* Initialize Transmit DMA Channel */
  4787. usc_DmaCmd( info, DmaCmd_InitTxChannel );
  4788. usc_TCmd( info, TCmd_SendFrame );
  4789. mod_timer(&info->tx_timer, jiffies +
  4790. msecs_to_jiffies(5000));
  4791. }
  4792. info->tx_active = 1;
  4793. }
  4794. if ( !info->tx_enabled ) {
  4795. info->tx_enabled = 1;
  4796. if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
  4797. usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
  4798. else
  4799. usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
  4800. }
  4801. } /* end of usc_start_transmitter() */
  4802. /* usc_stop_transmitter()
  4803. *
  4804. * Stops the transmitter and DMA
  4805. *
  4806. * Arguments: info pointer to device isntance data
  4807. * Return Value: None
  4808. */
  4809. static void usc_stop_transmitter( struct mgsl_struct *info )
  4810. {
  4811. if (debug_level >= DEBUG_LEVEL_ISR)
  4812. printk("%s(%d):usc_stop_transmitter(%s)\n",
  4813. __FILE__,__LINE__, info->device_name );
  4814. del_timer(&info->tx_timer);
  4815. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  4816. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
  4817. usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
  4818. usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
  4819. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  4820. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  4821. info->tx_enabled = 0;
  4822. info->tx_active = 0;
  4823. } /* end of usc_stop_transmitter() */
  4824. /* usc_load_txfifo()
  4825. *
  4826. * Fill the transmit FIFO until the FIFO is full or
  4827. * there is no more data to load.
  4828. *
  4829. * Arguments: info pointer to device extension (instance data)
  4830. * Return Value: None
  4831. */
  4832. static void usc_load_txfifo( struct mgsl_struct *info )
  4833. {
  4834. int Fifocount;
  4835. u8 TwoBytes[2];
  4836. if ( !info->xmit_cnt && !info->x_char )
  4837. return;
  4838. /* Select transmit FIFO status readback in TICR */
  4839. usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
  4840. /* load the Transmit FIFO until FIFOs full or all data sent */
  4841. while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
  4842. /* there is more space in the transmit FIFO and */
  4843. /* there is more data in transmit buffer */
  4844. if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
  4845. /* write a 16-bit word from transmit buffer to 16C32 */
  4846. TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
  4847. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4848. TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
  4849. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4850. outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
  4851. info->xmit_cnt -= 2;
  4852. info->icount.tx += 2;
  4853. } else {
  4854. /* only 1 byte left to transmit or 1 FIFO slot left */
  4855. outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
  4856. info->io_base + CCAR );
  4857. if (info->x_char) {
  4858. /* transmit pending high priority char */
  4859. outw( info->x_char,info->io_base + CCAR );
  4860. info->x_char = 0;
  4861. } else {
  4862. outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
  4863. info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
  4864. info->xmit_cnt--;
  4865. }
  4866. info->icount.tx++;
  4867. }
  4868. }
  4869. } /* end of usc_load_txfifo() */
  4870. /* usc_reset()
  4871. *
  4872. * Reset the adapter to a known state and prepare it for further use.
  4873. *
  4874. * Arguments: info pointer to device instance data
  4875. * Return Value: None
  4876. */
  4877. static void usc_reset( struct mgsl_struct *info )
  4878. {
  4879. if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
  4880. int i;
  4881. u32 readval;
  4882. /* Set BIT30 of Misc Control Register */
  4883. /* (Local Control Register 0x50) to force reset of USC. */
  4884. volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
  4885. u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
  4886. info->misc_ctrl_value |= BIT30;
  4887. *MiscCtrl = info->misc_ctrl_value;
  4888. /*
  4889. * Force at least 170ns delay before clearing
  4890. * reset bit. Each read from LCR takes at least
  4891. * 30ns so 10 times for 300ns to be safe.
  4892. */
  4893. for(i=0;i<10;i++)
  4894. readval = *MiscCtrl;
  4895. info->misc_ctrl_value &= ~BIT30;
  4896. *MiscCtrl = info->misc_ctrl_value;
  4897. *LCR0BRDR = BUS_DESCRIPTOR(
  4898. 1, // Write Strobe Hold (0-3)
  4899. 2, // Write Strobe Delay (0-3)
  4900. 2, // Read Strobe Delay (0-3)
  4901. 0, // NWDD (Write data-data) (0-3)
  4902. 4, // NWAD (Write Addr-data) (0-31)
  4903. 0, // NXDA (Read/Write Data-Addr) (0-3)
  4904. 0, // NRDD (Read Data-Data) (0-3)
  4905. 5 // NRAD (Read Addr-Data) (0-31)
  4906. );
  4907. } else {
  4908. /* do HW reset */
  4909. outb( 0,info->io_base + 8 );
  4910. }
  4911. info->mbre_bit = 0;
  4912. info->loopback_bits = 0;
  4913. info->usc_idle_mode = 0;
  4914. /*
  4915. * Program the Bus Configuration Register (BCR)
  4916. *
  4917. * <15> 0 Don't use separate address
  4918. * <14..6> 0 reserved
  4919. * <5..4> 00 IAckmode = Default, don't care
  4920. * <3> 1 Bus Request Totem Pole output
  4921. * <2> 1 Use 16 Bit data bus
  4922. * <1> 0 IRQ Totem Pole output
  4923. * <0> 0 Don't Shift Right Addr
  4924. *
  4925. * 0000 0000 0000 1100 = 0x000c
  4926. *
  4927. * By writing to io_base + SDPIN the Wait/Ack pin is
  4928. * programmed to work as a Wait pin.
  4929. */
  4930. outw( 0x000c,info->io_base + SDPIN );
  4931. outw( 0,info->io_base );
  4932. outw( 0,info->io_base + CCAR );
  4933. /* select little endian byte ordering */
  4934. usc_RTCmd( info, RTCmd_SelectLittleEndian );
  4935. /* Port Control Register (PCR)
  4936. *
  4937. * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
  4938. * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
  4939. * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
  4940. * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
  4941. * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
  4942. * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
  4943. * <3..2> 01 Port 1 is Input (Dedicated RxC)
  4944. * <1..0> 01 Port 0 is Input (Dedicated TxC)
  4945. *
  4946. * 1111 0000 1111 0101 = 0xf0f5
  4947. */
  4948. usc_OutReg( info, PCR, 0xf0f5 );
  4949. /*
  4950. * Input/Output Control Register
  4951. *
  4952. * <15..14> 00 CTS is active low input
  4953. * <13..12> 00 DCD is active low input
  4954. * <11..10> 00 TxREQ pin is input (DSR)
  4955. * <9..8> 00 RxREQ pin is input (RI)
  4956. * <7..6> 00 TxD is output (Transmit Data)
  4957. * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
  4958. * <2..0> 100 RxC is Output (drive with BRG0)
  4959. *
  4960. * 0000 0000 0000 0100 = 0x0004
  4961. */
  4962. usc_OutReg( info, IOCR, 0x0004 );
  4963. } /* end of usc_reset() */
  4964. /* usc_set_async_mode()
  4965. *
  4966. * Program adapter for asynchronous communications.
  4967. *
  4968. * Arguments: info pointer to device instance data
  4969. * Return Value: None
  4970. */
  4971. static void usc_set_async_mode( struct mgsl_struct *info )
  4972. {
  4973. u16 RegValue;
  4974. /* disable interrupts while programming USC */
  4975. usc_DisableMasterIrqBit( info );
  4976. outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
  4977. usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
  4978. usc_loopback_frame( info );
  4979. /* Channel mode Register (CMR)
  4980. *
  4981. * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
  4982. * <13..12> 00 00 = 16X Clock
  4983. * <11..8> 0000 Transmitter mode = Asynchronous
  4984. * <7..6> 00 reserved?
  4985. * <5..4> 00 Rx Sub modes, 00 = 16X Clock
  4986. * <3..0> 0000 Receiver mode = Asynchronous
  4987. *
  4988. * 0000 0000 0000 0000 = 0x0
  4989. */
  4990. RegValue = 0;
  4991. if ( info->params.stop_bits != 1 )
  4992. RegValue |= BIT14;
  4993. usc_OutReg( info, CMR, RegValue );
  4994. /* Receiver mode Register (RMR)
  4995. *
  4996. * <15..13> 000 encoding = None
  4997. * <12..08> 00000 reserved (Sync Only)
  4998. * <7..6> 00 Even parity
  4999. * <5> 0 parity disabled
  5000. * <4..2> 000 Receive Char Length = 8 bits
  5001. * <1..0> 00 Disable Receiver
  5002. *
  5003. * 0000 0000 0000 0000 = 0x0
  5004. */
  5005. RegValue = 0;
  5006. if ( info->params.data_bits != 8 )
  5007. RegValue |= BIT4+BIT3+BIT2;
  5008. if ( info->params.parity != ASYNC_PARITY_NONE ) {
  5009. RegValue |= BIT5;
  5010. if ( info->params.parity != ASYNC_PARITY_ODD )
  5011. RegValue |= BIT6;
  5012. }
  5013. usc_OutReg( info, RMR, RegValue );
  5014. /* Set IRQ trigger level */
  5015. usc_RCmd( info, RCmd_SelectRicrIntLevel );
  5016. /* Receive Interrupt Control Register (RICR)
  5017. *
  5018. * <15..8> ? RxFIFO IRQ Request Level
  5019. *
  5020. * Note: For async mode the receive FIFO level must be set
  5021. * to 0 to avoid the situation where the FIFO contains fewer bytes
  5022. * than the trigger level and no more data is expected.
  5023. *
  5024. * <7> 0 Exited Hunt IA (Interrupt Arm)
  5025. * <6> 0 Idle Received IA
  5026. * <5> 0 Break/Abort IA
  5027. * <4> 0 Rx Bound IA
  5028. * <3> 0 Queued status reflects oldest byte in FIFO
  5029. * <2> 0 Abort/PE IA
  5030. * <1> 0 Rx Overrun IA
  5031. * <0> 0 Select TC0 value for readback
  5032. *
  5033. * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
  5034. */
  5035. usc_OutReg( info, RICR, 0x0000 );
  5036. usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
  5037. usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
  5038. /* Transmit mode Register (TMR)
  5039. *
  5040. * <15..13> 000 encoding = None
  5041. * <12..08> 00000 reserved (Sync Only)
  5042. * <7..6> 00 Transmit parity Even
  5043. * <5> 0 Transmit parity Disabled
  5044. * <4..2> 000 Tx Char Length = 8 bits
  5045. * <1..0> 00 Disable Transmitter
  5046. *
  5047. * 0000 0000 0000 0000 = 0x0
  5048. */
  5049. RegValue = 0;
  5050. if ( info->params.data_bits != 8 )
  5051. RegValue |= BIT4+BIT3+BIT2;
  5052. if ( info->params.parity != ASYNC_PARITY_NONE ) {
  5053. RegValue |= BIT5;
  5054. if ( info->params.parity != ASYNC_PARITY_ODD )
  5055. RegValue |= BIT6;
  5056. }
  5057. usc_OutReg( info, TMR, RegValue );
  5058. usc_set_txidle( info );
  5059. /* Set IRQ trigger level */
  5060. usc_TCmd( info, TCmd_SelectTicrIntLevel );
  5061. /* Transmit Interrupt Control Register (TICR)
  5062. *
  5063. * <15..8> ? Transmit FIFO IRQ Level
  5064. * <7> 0 Present IA (Interrupt Arm)
  5065. * <6> 1 Idle Sent IA
  5066. * <5> 0 Abort Sent IA
  5067. * <4> 0 EOF/EOM Sent IA
  5068. * <3> 0 CRC Sent IA
  5069. * <2> 0 1 = Wait for SW Trigger to Start Frame
  5070. * <1> 0 Tx Underrun IA
  5071. * <0> 0 TC0 constant on read back
  5072. *
  5073. * 0000 0000 0100 0000 = 0x0040
  5074. */
  5075. usc_OutReg( info, TICR, 0x1f40 );
  5076. usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
  5077. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
  5078. usc_enable_async_clock( info, info->params.data_rate );
  5079. /* Channel Control/status Register (CCSR)
  5080. *
  5081. * <15> X RCC FIFO Overflow status (RO)
  5082. * <14> X RCC FIFO Not Empty status (RO)
  5083. * <13> 0 1 = Clear RCC FIFO (WO)
  5084. * <12> X DPLL in Sync status (RO)
  5085. * <11> X DPLL 2 Missed Clocks status (RO)
  5086. * <10> X DPLL 1 Missed Clock status (RO)
  5087. * <9..8> 00 DPLL Resync on rising and falling edges (RW)
  5088. * <7> X SDLC Loop On status (RO)
  5089. * <6> X SDLC Loop Send status (RO)
  5090. * <5> 1 Bypass counters for TxClk and RxClk (RW)
  5091. * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
  5092. * <1..0> 00 reserved
  5093. *
  5094. * 0000 0000 0010 0000 = 0x0020
  5095. */
  5096. usc_OutReg( info, CCSR, 0x0020 );
  5097. usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
  5098. RECEIVE_DATA + RECEIVE_STATUS );
  5099. usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
  5100. RECEIVE_DATA + RECEIVE_STATUS );
  5101. usc_EnableMasterIrqBit( info );
  5102. if (info->bus_type == MGSL_BUS_TYPE_ISA) {
  5103. /* Enable INTEN (Port 6, Bit12) */
  5104. /* This connects the IRQ request signal to the ISA bus */
  5105. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
  5106. }
  5107. if (info->params.loopback) {
  5108. info->loopback_bits = 0x300;
  5109. outw(0x0300, info->io_base + CCAR);
  5110. }
  5111. } /* end of usc_set_async_mode() */
  5112. /* usc_loopback_frame()
  5113. *
  5114. * Loop back a small (2 byte) dummy SDLC frame.
  5115. * Interrupts and DMA are NOT used. The purpose of this is to
  5116. * clear any 'stale' status info left over from running in async mode.
  5117. *
  5118. * The 16C32 shows the strange behaviour of marking the 1st
  5119. * received SDLC frame with a CRC error even when there is no
  5120. * CRC error. To get around this a small dummy from of 2 bytes
  5121. * is looped back when switching from async to sync mode.
  5122. *
  5123. * Arguments: info pointer to device instance data
  5124. * Return Value: None
  5125. */
  5126. static void usc_loopback_frame( struct mgsl_struct *info )
  5127. {
  5128. int i;
  5129. unsigned long oldmode = info->params.mode;
  5130. info->params.mode = MGSL_MODE_HDLC;
  5131. usc_DisableMasterIrqBit( info );
  5132. usc_set_sdlc_mode( info );
  5133. usc_enable_loopback( info, 1 );
  5134. /* Write 16-bit Time Constant for BRG0 */
  5135. usc_OutReg( info, TC0R, 0 );
  5136. /* Channel Control Register (CCR)
  5137. *
  5138. * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
  5139. * <13> 0 Trigger Tx on SW Command Disabled
  5140. * <12> 0 Flag Preamble Disabled
  5141. * <11..10> 00 Preamble Length = 8-Bits
  5142. * <9..8> 01 Preamble Pattern = flags
  5143. * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
  5144. * <5> 0 Trigger Rx on SW Command Disabled
  5145. * <4..0> 0 reserved
  5146. *
  5147. * 0000 0001 0000 0000 = 0x0100
  5148. */
  5149. usc_OutReg( info, CCR, 0x0100 );
  5150. /* SETUP RECEIVER */
  5151. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  5152. usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
  5153. /* SETUP TRANSMITTER */
  5154. /* Program the Transmit Character Length Register (TCLR) */
  5155. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  5156. usc_OutReg( info, TCLR, 2 );
  5157. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  5158. /* unlatch Tx status bits, and start transmit channel. */
  5159. usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
  5160. outw(0,info->io_base + DATAREG);
  5161. /* ENABLE TRANSMITTER */
  5162. usc_TCmd( info, TCmd_SendFrame );
  5163. usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
  5164. /* WAIT FOR RECEIVE COMPLETE */
  5165. for (i=0 ; i<1000 ; i++)
  5166. if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
  5167. break;
  5168. /* clear Internal Data loopback mode */
  5169. usc_enable_loopback(info, 0);
  5170. usc_EnableMasterIrqBit(info);
  5171. info->params.mode = oldmode;
  5172. } /* end of usc_loopback_frame() */
  5173. /* usc_set_sync_mode() Programs the USC for SDLC communications.
  5174. *
  5175. * Arguments: info pointer to adapter info structure
  5176. * Return Value: None
  5177. */
  5178. static void usc_set_sync_mode( struct mgsl_struct *info )
  5179. {
  5180. usc_loopback_frame( info );
  5181. usc_set_sdlc_mode( info );
  5182. if (info->bus_type == MGSL_BUS_TYPE_ISA) {
  5183. /* Enable INTEN (Port 6, Bit12) */
  5184. /* This connects the IRQ request signal to the ISA bus */
  5185. usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
  5186. }
  5187. usc_enable_aux_clock(info, info->params.clock_speed);
  5188. if (info->params.loopback)
  5189. usc_enable_loopback(info,1);
  5190. } /* end of mgsl_set_sync_mode() */
  5191. /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
  5192. *
  5193. * Arguments: info pointer to device instance data
  5194. * Return Value: None
  5195. */
  5196. static void usc_set_txidle( struct mgsl_struct *info )
  5197. {
  5198. u16 usc_idle_mode = IDLEMODE_FLAGS;
  5199. /* Map API idle mode to USC register bits */
  5200. switch( info->idle_mode ){
  5201. case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
  5202. case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
  5203. case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
  5204. case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
  5205. case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
  5206. case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
  5207. case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
  5208. }
  5209. info->usc_idle_mode = usc_idle_mode;
  5210. //usc_OutReg(info, TCSR, usc_idle_mode);
  5211. info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
  5212. info->tcsr_value += usc_idle_mode;
  5213. usc_OutReg(info, TCSR, info->tcsr_value);
  5214. /*
  5215. * if SyncLink WAN adapter is running in external sync mode, the
  5216. * transmitter has been set to Monosync in order to try to mimic
  5217. * a true raw outbound bit stream. Monosync still sends an open/close
  5218. * sync char at the start/end of a frame. Try to match those sync
  5219. * patterns to the idle mode set here
  5220. */
  5221. if ( info->params.mode == MGSL_MODE_RAW ) {
  5222. unsigned char syncpat = 0;
  5223. switch( info->idle_mode ) {
  5224. case HDLC_TXIDLE_FLAGS:
  5225. syncpat = 0x7e;
  5226. break;
  5227. case HDLC_TXIDLE_ALT_ZEROS_ONES:
  5228. syncpat = 0x55;
  5229. break;
  5230. case HDLC_TXIDLE_ZEROS:
  5231. case HDLC_TXIDLE_SPACE:
  5232. syncpat = 0x00;
  5233. break;
  5234. case HDLC_TXIDLE_ONES:
  5235. case HDLC_TXIDLE_MARK:
  5236. syncpat = 0xff;
  5237. break;
  5238. case HDLC_TXIDLE_ALT_MARK_SPACE:
  5239. syncpat = 0xaa;
  5240. break;
  5241. }
  5242. usc_SetTransmitSyncChars(info,syncpat,syncpat);
  5243. }
  5244. } /* end of usc_set_txidle() */
  5245. /* usc_get_serial_signals()
  5246. *
  5247. * Query the adapter for the state of the V24 status (input) signals.
  5248. *
  5249. * Arguments: info pointer to device instance data
  5250. * Return Value: None
  5251. */
  5252. static void usc_get_serial_signals( struct mgsl_struct *info )
  5253. {
  5254. u16 status;
  5255. /* clear all serial signals except DTR and RTS */
  5256. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  5257. /* Read the Misc Interrupt status Register (MISR) to get */
  5258. /* the V24 status signals. */
  5259. status = usc_InReg( info, MISR );
  5260. /* set serial signal bits to reflect MISR */
  5261. if ( status & MISCSTATUS_CTS )
  5262. info->serial_signals |= SerialSignal_CTS;
  5263. if ( status & MISCSTATUS_DCD )
  5264. info->serial_signals |= SerialSignal_DCD;
  5265. if ( status & MISCSTATUS_RI )
  5266. info->serial_signals |= SerialSignal_RI;
  5267. if ( status & MISCSTATUS_DSR )
  5268. info->serial_signals |= SerialSignal_DSR;
  5269. } /* end of usc_get_serial_signals() */
  5270. /* usc_set_serial_signals()
  5271. *
  5272. * Set the state of DTR and RTS based on contents of
  5273. * serial_signals member of device extension.
  5274. *
  5275. * Arguments: info pointer to device instance data
  5276. * Return Value: None
  5277. */
  5278. static void usc_set_serial_signals( struct mgsl_struct *info )
  5279. {
  5280. u16 Control;
  5281. unsigned char V24Out = info->serial_signals;
  5282. /* get the current value of the Port Control Register (PCR) */
  5283. Control = usc_InReg( info, PCR );
  5284. if ( V24Out & SerialSignal_RTS )
  5285. Control &= ~(BIT6);
  5286. else
  5287. Control |= BIT6;
  5288. if ( V24Out & SerialSignal_DTR )
  5289. Control &= ~(BIT4);
  5290. else
  5291. Control |= BIT4;
  5292. usc_OutReg( info, PCR, Control );
  5293. } /* end of usc_set_serial_signals() */
  5294. /* usc_enable_async_clock()
  5295. *
  5296. * Enable the async clock at the specified frequency.
  5297. *
  5298. * Arguments: info pointer to device instance data
  5299. * data_rate data rate of clock in bps
  5300. * 0 disables the AUX clock.
  5301. * Return Value: None
  5302. */
  5303. static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
  5304. {
  5305. if ( data_rate ) {
  5306. /*
  5307. * Clock mode Control Register (CMCR)
  5308. *
  5309. * <15..14> 00 counter 1 Disabled
  5310. * <13..12> 00 counter 0 Disabled
  5311. * <11..10> 11 BRG1 Input is TxC Pin
  5312. * <9..8> 11 BRG0 Input is TxC Pin
  5313. * <7..6> 01 DPLL Input is BRG1 Output
  5314. * <5..3> 100 TxCLK comes from BRG0
  5315. * <2..0> 100 RxCLK comes from BRG0
  5316. *
  5317. * 0000 1111 0110 0100 = 0x0f64
  5318. */
  5319. usc_OutReg( info, CMCR, 0x0f64 );
  5320. /*
  5321. * Write 16-bit Time Constant for BRG0
  5322. * Time Constant = (ClkSpeed / data_rate) - 1
  5323. * ClkSpeed = 921600 (ISA), 691200 (PCI)
  5324. */
  5325. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  5326. usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
  5327. else
  5328. usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
  5329. /*
  5330. * Hardware Configuration Register (HCR)
  5331. * Clear Bit 1, BRG0 mode = Continuous
  5332. * Set Bit 0 to enable BRG0.
  5333. */
  5334. usc_OutReg( info, HCR,
  5335. (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
  5336. /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
  5337. usc_OutReg( info, IOCR,
  5338. (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
  5339. } else {
  5340. /* data rate == 0 so turn off BRG0 */
  5341. usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
  5342. }
  5343. } /* end of usc_enable_async_clock() */
  5344. /*
  5345. * Buffer Structures:
  5346. *
  5347. * Normal memory access uses virtual addresses that can make discontiguous
  5348. * physical memory pages appear to be contiguous in the virtual address
  5349. * space (the processors memory mapping handles the conversions).
  5350. *
  5351. * DMA transfers require physically contiguous memory. This is because
  5352. * the DMA system controller and DMA bus masters deal with memory using
  5353. * only physical addresses.
  5354. *
  5355. * This causes a problem under Windows NT when large DMA buffers are
  5356. * needed. Fragmentation of the nonpaged pool prevents allocations of
  5357. * physically contiguous buffers larger than the PAGE_SIZE.
  5358. *
  5359. * However the 16C32 supports Bus Master Scatter/Gather DMA which
  5360. * allows DMA transfers to physically discontiguous buffers. Information
  5361. * about each data transfer buffer is contained in a memory structure
  5362. * called a 'buffer entry'. A list of buffer entries is maintained
  5363. * to track and control the use of the data transfer buffers.
  5364. *
  5365. * To support this strategy we will allocate sufficient PAGE_SIZE
  5366. * contiguous memory buffers to allow for the total required buffer
  5367. * space.
  5368. *
  5369. * The 16C32 accesses the list of buffer entries using Bus Master
  5370. * DMA. Control information is read from the buffer entries by the
  5371. * 16C32 to control data transfers. status information is written to
  5372. * the buffer entries by the 16C32 to indicate the status of completed
  5373. * transfers.
  5374. *
  5375. * The CPU writes control information to the buffer entries to control
  5376. * the 16C32 and reads status information from the buffer entries to
  5377. * determine information about received and transmitted frames.
  5378. *
  5379. * Because the CPU and 16C32 (adapter) both need simultaneous access
  5380. * to the buffer entries, the buffer entry memory is allocated with
  5381. * HalAllocateCommonBuffer(). This restricts the size of the buffer
  5382. * entry list to PAGE_SIZE.
  5383. *
  5384. * The actual data buffers on the other hand will only be accessed
  5385. * by the CPU or the adapter but not by both simultaneously. This allows
  5386. * Scatter/Gather packet based DMA procedures for using physically
  5387. * discontiguous pages.
  5388. */
  5389. /*
  5390. * mgsl_reset_tx_dma_buffers()
  5391. *
  5392. * Set the count for all transmit buffers to 0 to indicate the
  5393. * buffer is available for use and set the current buffer to the
  5394. * first buffer. This effectively makes all buffers free and
  5395. * discards any data in buffers.
  5396. *
  5397. * Arguments: info pointer to device instance data
  5398. * Return Value: None
  5399. */
  5400. static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
  5401. {
  5402. unsigned int i;
  5403. for ( i = 0; i < info->tx_buffer_count; i++ ) {
  5404. *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
  5405. }
  5406. info->current_tx_buffer = 0;
  5407. info->start_tx_dma_buffer = 0;
  5408. info->tx_dma_buffers_used = 0;
  5409. info->get_tx_holding_index = 0;
  5410. info->put_tx_holding_index = 0;
  5411. info->tx_holding_count = 0;
  5412. } /* end of mgsl_reset_tx_dma_buffers() */
  5413. /*
  5414. * num_free_tx_dma_buffers()
  5415. *
  5416. * returns the number of free tx dma buffers available
  5417. *
  5418. * Arguments: info pointer to device instance data
  5419. * Return Value: number of free tx dma buffers
  5420. */
  5421. static int num_free_tx_dma_buffers(struct mgsl_struct *info)
  5422. {
  5423. return info->tx_buffer_count - info->tx_dma_buffers_used;
  5424. }
  5425. /*
  5426. * mgsl_reset_rx_dma_buffers()
  5427. *
  5428. * Set the count for all receive buffers to DMABUFFERSIZE
  5429. * and set the current buffer to the first buffer. This effectively
  5430. * makes all buffers free and discards any data in buffers.
  5431. *
  5432. * Arguments: info pointer to device instance data
  5433. * Return Value: None
  5434. */
  5435. static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
  5436. {
  5437. unsigned int i;
  5438. for ( i = 0; i < info->rx_buffer_count; i++ ) {
  5439. *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
  5440. // info->rx_buffer_list[i].count = DMABUFFERSIZE;
  5441. // info->rx_buffer_list[i].status = 0;
  5442. }
  5443. info->current_rx_buffer = 0;
  5444. } /* end of mgsl_reset_rx_dma_buffers() */
  5445. /*
  5446. * mgsl_free_rx_frame_buffers()
  5447. *
  5448. * Free the receive buffers used by a received SDLC
  5449. * frame such that the buffers can be reused.
  5450. *
  5451. * Arguments:
  5452. *
  5453. * info pointer to device instance data
  5454. * StartIndex index of 1st receive buffer of frame
  5455. * EndIndex index of last receive buffer of frame
  5456. *
  5457. * Return Value: None
  5458. */
  5459. static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
  5460. {
  5461. int Done = 0;
  5462. DMABUFFERENTRY *pBufEntry;
  5463. unsigned int Index;
  5464. /* Starting with 1st buffer entry of the frame clear the status */
  5465. /* field and set the count field to DMA Buffer Size. */
  5466. Index = StartIndex;
  5467. while( !Done ) {
  5468. pBufEntry = &(info->rx_buffer_list[Index]);
  5469. if ( Index == EndIndex ) {
  5470. /* This is the last buffer of the frame! */
  5471. Done = 1;
  5472. }
  5473. /* reset current buffer for reuse */
  5474. // pBufEntry->status = 0;
  5475. // pBufEntry->count = DMABUFFERSIZE;
  5476. *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
  5477. /* advance to next buffer entry in linked list */
  5478. Index++;
  5479. if ( Index == info->rx_buffer_count )
  5480. Index = 0;
  5481. }
  5482. /* set current buffer to next buffer after last buffer of frame */
  5483. info->current_rx_buffer = Index;
  5484. } /* end of free_rx_frame_buffers() */
  5485. /* mgsl_get_rx_frame()
  5486. *
  5487. * This function attempts to return a received SDLC frame from the
  5488. * receive DMA buffers. Only frames received without errors are returned.
  5489. *
  5490. * Arguments: info pointer to device extension
  5491. * Return Value: 1 if frame returned, otherwise 0
  5492. */
  5493. static int mgsl_get_rx_frame(struct mgsl_struct *info)
  5494. {
  5495. unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
  5496. unsigned short status;
  5497. DMABUFFERENTRY *pBufEntry;
  5498. unsigned int framesize = 0;
  5499. int ReturnCode = 0;
  5500. unsigned long flags;
  5501. struct tty_struct *tty = info->tty;
  5502. int return_frame = 0;
  5503. /*
  5504. * current_rx_buffer points to the 1st buffer of the next available
  5505. * receive frame. To find the last buffer of the frame look for
  5506. * a non-zero status field in the buffer entries. (The status
  5507. * field is set by the 16C32 after completing a receive frame.
  5508. */
  5509. StartIndex = EndIndex = info->current_rx_buffer;
  5510. while( !info->rx_buffer_list[EndIndex].status ) {
  5511. /*
  5512. * If the count field of the buffer entry is non-zero then
  5513. * this buffer has not been used. (The 16C32 clears the count
  5514. * field when it starts using the buffer.) If an unused buffer
  5515. * is encountered then there are no frames available.
  5516. */
  5517. if ( info->rx_buffer_list[EndIndex].count )
  5518. goto Cleanup;
  5519. /* advance to next buffer entry in linked list */
  5520. EndIndex++;
  5521. if ( EndIndex == info->rx_buffer_count )
  5522. EndIndex = 0;
  5523. /* if entire list searched then no frame available */
  5524. if ( EndIndex == StartIndex ) {
  5525. /* If this occurs then something bad happened,
  5526. * all buffers have been 'used' but none mark
  5527. * the end of a frame. Reset buffers and receiver.
  5528. */
  5529. if ( info->rx_enabled ){
  5530. spin_lock_irqsave(&info->irq_spinlock,flags);
  5531. usc_start_receiver(info);
  5532. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5533. }
  5534. goto Cleanup;
  5535. }
  5536. }
  5537. /* check status of receive frame */
  5538. status = info->rx_buffer_list[EndIndex].status;
  5539. if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
  5540. RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
  5541. if ( status & RXSTATUS_SHORT_FRAME )
  5542. info->icount.rxshort++;
  5543. else if ( status & RXSTATUS_ABORT )
  5544. info->icount.rxabort++;
  5545. else if ( status & RXSTATUS_OVERRUN )
  5546. info->icount.rxover++;
  5547. else {
  5548. info->icount.rxcrc++;
  5549. if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
  5550. return_frame = 1;
  5551. }
  5552. framesize = 0;
  5553. #if SYNCLINK_GENERIC_HDLC
  5554. {
  5555. struct net_device_stats *stats = hdlc_stats(info->netdev);
  5556. stats->rx_errors++;
  5557. stats->rx_frame_errors++;
  5558. }
  5559. #endif
  5560. } else
  5561. return_frame = 1;
  5562. if ( return_frame ) {
  5563. /* receive frame has no errors, get frame size.
  5564. * The frame size is the starting value of the RCC (which was
  5565. * set to 0xffff) minus the ending value of the RCC (decremented
  5566. * once for each receive character) minus 2 for the 16-bit CRC.
  5567. */
  5568. framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
  5569. /* adjust frame size for CRC if any */
  5570. if ( info->params.crc_type == HDLC_CRC_16_CCITT )
  5571. framesize -= 2;
  5572. else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
  5573. framesize -= 4;
  5574. }
  5575. if ( debug_level >= DEBUG_LEVEL_BH )
  5576. printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
  5577. __FILE__,__LINE__,info->device_name,status,framesize);
  5578. if ( debug_level >= DEBUG_LEVEL_DATA )
  5579. mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
  5580. min_t(int, framesize, DMABUFFERSIZE),0);
  5581. if (framesize) {
  5582. if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
  5583. ((framesize+1) > info->max_frame_size) ) ||
  5584. (framesize > info->max_frame_size) )
  5585. info->icount.rxlong++;
  5586. else {
  5587. /* copy dma buffer(s) to contiguous intermediate buffer */
  5588. int copy_count = framesize;
  5589. int index = StartIndex;
  5590. unsigned char *ptmp = info->intermediate_rxbuffer;
  5591. if ( !(status & RXSTATUS_CRC_ERROR))
  5592. info->icount.rxok++;
  5593. while(copy_count) {
  5594. int partial_count;
  5595. if ( copy_count > DMABUFFERSIZE )
  5596. partial_count = DMABUFFERSIZE;
  5597. else
  5598. partial_count = copy_count;
  5599. pBufEntry = &(info->rx_buffer_list[index]);
  5600. memcpy( ptmp, pBufEntry->virt_addr, partial_count );
  5601. ptmp += partial_count;
  5602. copy_count -= partial_count;
  5603. if ( ++index == info->rx_buffer_count )
  5604. index = 0;
  5605. }
  5606. if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
  5607. ++framesize;
  5608. *ptmp = (status & RXSTATUS_CRC_ERROR ?
  5609. RX_CRC_ERROR :
  5610. RX_OK);
  5611. if ( debug_level >= DEBUG_LEVEL_DATA )
  5612. printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
  5613. __FILE__,__LINE__,info->device_name,
  5614. *ptmp);
  5615. }
  5616. #if SYNCLINK_GENERIC_HDLC
  5617. if (info->netcount)
  5618. hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
  5619. else
  5620. #endif
  5621. ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
  5622. }
  5623. }
  5624. /* Free the buffers used by this frame. */
  5625. mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
  5626. ReturnCode = 1;
  5627. Cleanup:
  5628. if ( info->rx_enabled && info->rx_overflow ) {
  5629. /* The receiver needs to restarted because of
  5630. * a receive overflow (buffer or FIFO). If the
  5631. * receive buffers are now empty, then restart receiver.
  5632. */
  5633. if ( !info->rx_buffer_list[EndIndex].status &&
  5634. info->rx_buffer_list[EndIndex].count ) {
  5635. spin_lock_irqsave(&info->irq_spinlock,flags);
  5636. usc_start_receiver(info);
  5637. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5638. }
  5639. }
  5640. return ReturnCode;
  5641. } /* end of mgsl_get_rx_frame() */
  5642. /* mgsl_get_raw_rx_frame()
  5643. *
  5644. * This function attempts to return a received frame from the
  5645. * receive DMA buffers when running in external loop mode. In this mode,
  5646. * we will return at most one DMABUFFERSIZE frame to the application.
  5647. * The USC receiver is triggering off of DCD going active to start a new
  5648. * frame, and DCD going inactive to terminate the frame (similar to
  5649. * processing a closing flag character).
  5650. *
  5651. * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
  5652. * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
  5653. * status field and the RCC field will indicate the length of the
  5654. * entire received frame. We take this RCC field and get the modulus
  5655. * of RCC and DMABUFFERSIZE to determine if number of bytes in the
  5656. * last Rx DMA buffer and return that last portion of the frame.
  5657. *
  5658. * Arguments: info pointer to device extension
  5659. * Return Value: 1 if frame returned, otherwise 0
  5660. */
  5661. static int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
  5662. {
  5663. unsigned int CurrentIndex, NextIndex;
  5664. unsigned short status;
  5665. DMABUFFERENTRY *pBufEntry;
  5666. unsigned int framesize = 0;
  5667. int ReturnCode = 0;
  5668. unsigned long flags;
  5669. struct tty_struct *tty = info->tty;
  5670. /*
  5671. * current_rx_buffer points to the 1st buffer of the next available
  5672. * receive frame. The status field is set by the 16C32 after
  5673. * completing a receive frame. If the status field of this buffer
  5674. * is zero, either the USC is still filling this buffer or this
  5675. * is one of a series of buffers making up a received frame.
  5676. *
  5677. * If the count field of this buffer is zero, the USC is either
  5678. * using this buffer or has used this buffer. Look at the count
  5679. * field of the next buffer. If that next buffer's count is
  5680. * non-zero, the USC is still actively using the current buffer.
  5681. * Otherwise, if the next buffer's count field is zero, the
  5682. * current buffer is complete and the USC is using the next
  5683. * buffer.
  5684. */
  5685. CurrentIndex = NextIndex = info->current_rx_buffer;
  5686. ++NextIndex;
  5687. if ( NextIndex == info->rx_buffer_count )
  5688. NextIndex = 0;
  5689. if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
  5690. (info->rx_buffer_list[CurrentIndex].count == 0 &&
  5691. info->rx_buffer_list[NextIndex].count == 0)) {
  5692. /*
  5693. * Either the status field of this dma buffer is non-zero
  5694. * (indicating the last buffer of a receive frame) or the next
  5695. * buffer is marked as in use -- implying this buffer is complete
  5696. * and an intermediate buffer for this received frame.
  5697. */
  5698. status = info->rx_buffer_list[CurrentIndex].status;
  5699. if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
  5700. RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
  5701. if ( status & RXSTATUS_SHORT_FRAME )
  5702. info->icount.rxshort++;
  5703. else if ( status & RXSTATUS_ABORT )
  5704. info->icount.rxabort++;
  5705. else if ( status & RXSTATUS_OVERRUN )
  5706. info->icount.rxover++;
  5707. else
  5708. info->icount.rxcrc++;
  5709. framesize = 0;
  5710. } else {
  5711. /*
  5712. * A receive frame is available, get frame size and status.
  5713. *
  5714. * The frame size is the starting value of the RCC (which was
  5715. * set to 0xffff) minus the ending value of the RCC (decremented
  5716. * once for each receive character) minus 2 or 4 for the 16-bit
  5717. * or 32-bit CRC.
  5718. *
  5719. * If the status field is zero, this is an intermediate buffer.
  5720. * It's size is 4K.
  5721. *
  5722. * If the DMA Buffer Entry's Status field is non-zero, the
  5723. * receive operation completed normally (ie: DCD dropped). The
  5724. * RCC field is valid and holds the received frame size.
  5725. * It is possible that the RCC field will be zero on a DMA buffer
  5726. * entry with a non-zero status. This can occur if the total
  5727. * frame size (number of bytes between the time DCD goes active
  5728. * to the time DCD goes inactive) exceeds 65535 bytes. In this
  5729. * case the 16C32 has underrun on the RCC count and appears to
  5730. * stop updating this counter to let us know the actual received
  5731. * frame size. If this happens (non-zero status and zero RCC),
  5732. * simply return the entire RxDMA Buffer
  5733. */
  5734. if ( status ) {
  5735. /*
  5736. * In the event that the final RxDMA Buffer is
  5737. * terminated with a non-zero status and the RCC
  5738. * field is zero, we interpret this as the RCC
  5739. * having underflowed (received frame > 65535 bytes).
  5740. *
  5741. * Signal the event to the user by passing back
  5742. * a status of RxStatus_CrcError returning the full
  5743. * buffer and let the app figure out what data is
  5744. * actually valid
  5745. */
  5746. if ( info->rx_buffer_list[CurrentIndex].rcc )
  5747. framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
  5748. else
  5749. framesize = DMABUFFERSIZE;
  5750. }
  5751. else
  5752. framesize = DMABUFFERSIZE;
  5753. }
  5754. if ( framesize > DMABUFFERSIZE ) {
  5755. /*
  5756. * if running in raw sync mode, ISR handler for
  5757. * End Of Buffer events terminates all buffers at 4K.
  5758. * If this frame size is said to be >4K, get the
  5759. * actual number of bytes of the frame in this buffer.
  5760. */
  5761. framesize = framesize % DMABUFFERSIZE;
  5762. }
  5763. if ( debug_level >= DEBUG_LEVEL_BH )
  5764. printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
  5765. __FILE__,__LINE__,info->device_name,status,framesize);
  5766. if ( debug_level >= DEBUG_LEVEL_DATA )
  5767. mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
  5768. min_t(int, framesize, DMABUFFERSIZE),0);
  5769. if (framesize) {
  5770. /* copy dma buffer(s) to contiguous intermediate buffer */
  5771. /* NOTE: we never copy more than DMABUFFERSIZE bytes */
  5772. pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
  5773. memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
  5774. info->icount.rxok++;
  5775. ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
  5776. }
  5777. /* Free the buffers used by this frame. */
  5778. mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
  5779. ReturnCode = 1;
  5780. }
  5781. if ( info->rx_enabled && info->rx_overflow ) {
  5782. /* The receiver needs to restarted because of
  5783. * a receive overflow (buffer or FIFO). If the
  5784. * receive buffers are now empty, then restart receiver.
  5785. */
  5786. if ( !info->rx_buffer_list[CurrentIndex].status &&
  5787. info->rx_buffer_list[CurrentIndex].count ) {
  5788. spin_lock_irqsave(&info->irq_spinlock,flags);
  5789. usc_start_receiver(info);
  5790. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5791. }
  5792. }
  5793. return ReturnCode;
  5794. } /* end of mgsl_get_raw_rx_frame() */
  5795. /* mgsl_load_tx_dma_buffer()
  5796. *
  5797. * Load the transmit DMA buffer with the specified data.
  5798. *
  5799. * Arguments:
  5800. *
  5801. * info pointer to device extension
  5802. * Buffer pointer to buffer containing frame to load
  5803. * BufferSize size in bytes of frame in Buffer
  5804. *
  5805. * Return Value: None
  5806. */
  5807. static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
  5808. const char *Buffer, unsigned int BufferSize)
  5809. {
  5810. unsigned short Copycount;
  5811. unsigned int i = 0;
  5812. DMABUFFERENTRY *pBufEntry;
  5813. if ( debug_level >= DEBUG_LEVEL_DATA )
  5814. mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
  5815. if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
  5816. /* set CMR:13 to start transmit when
  5817. * next GoAhead (abort) is received
  5818. */
  5819. info->cmr_value |= BIT13;
  5820. }
  5821. /* begin loading the frame in the next available tx dma
  5822. * buffer, remember it's starting location for setting
  5823. * up tx dma operation
  5824. */
  5825. i = info->current_tx_buffer;
  5826. info->start_tx_dma_buffer = i;
  5827. /* Setup the status and RCC (Frame Size) fields of the 1st */
  5828. /* buffer entry in the transmit DMA buffer list. */
  5829. info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
  5830. info->tx_buffer_list[i].rcc = BufferSize;
  5831. info->tx_buffer_list[i].count = BufferSize;
  5832. /* Copy frame data from 1st source buffer to the DMA buffers. */
  5833. /* The frame data may span multiple DMA buffers. */
  5834. while( BufferSize ){
  5835. /* Get a pointer to next DMA buffer entry. */
  5836. pBufEntry = &info->tx_buffer_list[i++];
  5837. if ( i == info->tx_buffer_count )
  5838. i=0;
  5839. /* Calculate the number of bytes that can be copied from */
  5840. /* the source buffer to this DMA buffer. */
  5841. if ( BufferSize > DMABUFFERSIZE )
  5842. Copycount = DMABUFFERSIZE;
  5843. else
  5844. Copycount = BufferSize;
  5845. /* Actually copy data from source buffer to DMA buffer. */
  5846. /* Also set the data count for this individual DMA buffer. */
  5847. if ( info->bus_type == MGSL_BUS_TYPE_PCI )
  5848. mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
  5849. else
  5850. memcpy(pBufEntry->virt_addr, Buffer, Copycount);
  5851. pBufEntry->count = Copycount;
  5852. /* Advance source pointer and reduce remaining data count. */
  5853. Buffer += Copycount;
  5854. BufferSize -= Copycount;
  5855. ++info->tx_dma_buffers_used;
  5856. }
  5857. /* remember next available tx dma buffer */
  5858. info->current_tx_buffer = i;
  5859. } /* end of mgsl_load_tx_dma_buffer() */
  5860. /*
  5861. * mgsl_register_test()
  5862. *
  5863. * Performs a register test of the 16C32.
  5864. *
  5865. * Arguments: info pointer to device instance data
  5866. * Return Value: TRUE if test passed, otherwise FALSE
  5867. */
  5868. static BOOLEAN mgsl_register_test( struct mgsl_struct *info )
  5869. {
  5870. static unsigned short BitPatterns[] =
  5871. { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
  5872. static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
  5873. unsigned int i;
  5874. BOOLEAN rc = TRUE;
  5875. unsigned long flags;
  5876. spin_lock_irqsave(&info->irq_spinlock,flags);
  5877. usc_reset(info);
  5878. /* Verify the reset state of some registers. */
  5879. if ( (usc_InReg( info, SICR ) != 0) ||
  5880. (usc_InReg( info, IVR ) != 0) ||
  5881. (usc_InDmaReg( info, DIVR ) != 0) ){
  5882. rc = FALSE;
  5883. }
  5884. if ( rc == TRUE ){
  5885. /* Write bit patterns to various registers but do it out of */
  5886. /* sync, then read back and verify values. */
  5887. for ( i = 0 ; i < Patterncount ; i++ ) {
  5888. usc_OutReg( info, TC0R, BitPatterns[i] );
  5889. usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
  5890. usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
  5891. usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
  5892. usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
  5893. usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
  5894. if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
  5895. (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
  5896. (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
  5897. (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
  5898. (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
  5899. (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
  5900. rc = FALSE;
  5901. break;
  5902. }
  5903. }
  5904. }
  5905. usc_reset(info);
  5906. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5907. return rc;
  5908. } /* end of mgsl_register_test() */
  5909. /* mgsl_irq_test() Perform interrupt test of the 16C32.
  5910. *
  5911. * Arguments: info pointer to device instance data
  5912. * Return Value: TRUE if test passed, otherwise FALSE
  5913. */
  5914. static BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
  5915. {
  5916. unsigned long EndTime;
  5917. unsigned long flags;
  5918. spin_lock_irqsave(&info->irq_spinlock,flags);
  5919. usc_reset(info);
  5920. /*
  5921. * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
  5922. * The ISR sets irq_occurred to 1.
  5923. */
  5924. info->irq_occurred = FALSE;
  5925. /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
  5926. /* Enable INTEN (Port 6, Bit12) */
  5927. /* This connects the IRQ request signal to the ISA bus */
  5928. /* on the ISA adapter. This has no effect for the PCI adapter */
  5929. usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
  5930. usc_EnableMasterIrqBit(info);
  5931. usc_EnableInterrupts(info, IO_PIN);
  5932. usc_ClearIrqPendingBits(info, IO_PIN);
  5933. usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
  5934. usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
  5935. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5936. EndTime=100;
  5937. while( EndTime-- && !info->irq_occurred ) {
  5938. msleep_interruptible(10);
  5939. }
  5940. spin_lock_irqsave(&info->irq_spinlock,flags);
  5941. usc_reset(info);
  5942. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5943. if ( !info->irq_occurred )
  5944. return FALSE;
  5945. else
  5946. return TRUE;
  5947. } /* end of mgsl_irq_test() */
  5948. /* mgsl_dma_test()
  5949. *
  5950. * Perform a DMA test of the 16C32. A small frame is
  5951. * transmitted via DMA from a transmit buffer to a receive buffer
  5952. * using single buffer DMA mode.
  5953. *
  5954. * Arguments: info pointer to device instance data
  5955. * Return Value: TRUE if test passed, otherwise FALSE
  5956. */
  5957. static BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
  5958. {
  5959. unsigned short FifoLevel;
  5960. unsigned long phys_addr;
  5961. unsigned int FrameSize;
  5962. unsigned int i;
  5963. char *TmpPtr;
  5964. BOOLEAN rc = TRUE;
  5965. unsigned short status=0;
  5966. unsigned long EndTime;
  5967. unsigned long flags;
  5968. MGSL_PARAMS tmp_params;
  5969. /* save current port options */
  5970. memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
  5971. /* load default port options */
  5972. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  5973. #define TESTFRAMESIZE 40
  5974. spin_lock_irqsave(&info->irq_spinlock,flags);
  5975. /* setup 16C32 for SDLC DMA transfer mode */
  5976. usc_reset(info);
  5977. usc_set_sdlc_mode(info);
  5978. usc_enable_loopback(info,1);
  5979. /* Reprogram the RDMR so that the 16C32 does NOT clear the count
  5980. * field of the buffer entry after fetching buffer address. This
  5981. * way we can detect a DMA failure for a DMA read (which should be
  5982. * non-destructive to system memory) before we try and write to
  5983. * memory (where a failure could corrupt system memory).
  5984. */
  5985. /* Receive DMA mode Register (RDMR)
  5986. *
  5987. * <15..14> 11 DMA mode = Linked List Buffer mode
  5988. * <13> 1 RSBinA/L = store Rx status Block in List entry
  5989. * <12> 0 1 = Clear count of List Entry after fetching
  5990. * <11..10> 00 Address mode = Increment
  5991. * <9> 1 Terminate Buffer on RxBound
  5992. * <8> 0 Bus Width = 16bits
  5993. * <7..0> ? status Bits (write as 0s)
  5994. *
  5995. * 1110 0010 0000 0000 = 0xe200
  5996. */
  5997. usc_OutDmaReg( info, RDMR, 0xe200 );
  5998. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  5999. /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
  6000. FrameSize = TESTFRAMESIZE;
  6001. /* setup 1st transmit buffer entry: */
  6002. /* with frame size and transmit control word */
  6003. info->tx_buffer_list[0].count = FrameSize;
  6004. info->tx_buffer_list[0].rcc = FrameSize;
  6005. info->tx_buffer_list[0].status = 0x4000;
  6006. /* build a transmit frame in 1st transmit DMA buffer */
  6007. TmpPtr = info->tx_buffer_list[0].virt_addr;
  6008. for (i = 0; i < FrameSize; i++ )
  6009. *TmpPtr++ = i;
  6010. /* setup 1st receive buffer entry: */
  6011. /* clear status, set max receive buffer size */
  6012. info->rx_buffer_list[0].status = 0;
  6013. info->rx_buffer_list[0].count = FrameSize + 4;
  6014. /* zero out the 1st receive buffer */
  6015. memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
  6016. /* Set count field of next buffer entries to prevent */
  6017. /* 16C32 from using buffers after the 1st one. */
  6018. info->tx_buffer_list[1].count = 0;
  6019. info->rx_buffer_list[1].count = 0;
  6020. /***************************/
  6021. /* Program 16C32 receiver. */
  6022. /***************************/
  6023. spin_lock_irqsave(&info->irq_spinlock,flags);
  6024. /* setup DMA transfers */
  6025. usc_RTCmd( info, RTCmd_PurgeRxFifo );
  6026. /* program 16C32 receiver with physical address of 1st DMA buffer entry */
  6027. phys_addr = info->rx_buffer_list[0].phys_entry;
  6028. usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
  6029. usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
  6030. /* Clear the Rx DMA status bits (read RDMR) and start channel */
  6031. usc_InDmaReg( info, RDMR );
  6032. usc_DmaCmd( info, DmaCmd_InitRxChannel );
  6033. /* Enable Receiver (RMR <1..0> = 10) */
  6034. usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
  6035. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6036. /*************************************************************/
  6037. /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
  6038. /*************************************************************/
  6039. /* Wait 100ms for interrupt. */
  6040. EndTime = jiffies + msecs_to_jiffies(100);
  6041. for(;;) {
  6042. if (time_after(jiffies, EndTime)) {
  6043. rc = FALSE;
  6044. break;
  6045. }
  6046. spin_lock_irqsave(&info->irq_spinlock,flags);
  6047. status = usc_InDmaReg( info, RDMR );
  6048. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6049. if ( !(status & BIT4) && (status & BIT5) ) {
  6050. /* INITG (BIT 4) is inactive (no entry read in progress) AND */
  6051. /* BUSY (BIT 5) is active (channel still active). */
  6052. /* This means the buffer entry read has completed. */
  6053. break;
  6054. }
  6055. }
  6056. /******************************/
  6057. /* Program 16C32 transmitter. */
  6058. /******************************/
  6059. spin_lock_irqsave(&info->irq_spinlock,flags);
  6060. /* Program the Transmit Character Length Register (TCLR) */
  6061. /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
  6062. usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
  6063. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  6064. /* Program the address of the 1st DMA Buffer Entry in linked list */
  6065. phys_addr = info->tx_buffer_list[0].phys_entry;
  6066. usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
  6067. usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
  6068. /* unlatch Tx status bits, and start transmit channel. */
  6069. usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
  6070. usc_DmaCmd( info, DmaCmd_InitTxChannel );
  6071. /* wait for DMA controller to fill transmit FIFO */
  6072. usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
  6073. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6074. /**********************************/
  6075. /* WAIT FOR TRANSMIT FIFO TO FILL */
  6076. /**********************************/
  6077. /* Wait 100ms */
  6078. EndTime = jiffies + msecs_to_jiffies(100);
  6079. for(;;) {
  6080. if (time_after(jiffies, EndTime)) {
  6081. rc = FALSE;
  6082. break;
  6083. }
  6084. spin_lock_irqsave(&info->irq_spinlock,flags);
  6085. FifoLevel = usc_InReg(info, TICR) >> 8;
  6086. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6087. if ( FifoLevel < 16 )
  6088. break;
  6089. else
  6090. if ( FrameSize < 32 ) {
  6091. /* This frame is smaller than the entire transmit FIFO */
  6092. /* so wait for the entire frame to be loaded. */
  6093. if ( FifoLevel <= (32 - FrameSize) )
  6094. break;
  6095. }
  6096. }
  6097. if ( rc == TRUE )
  6098. {
  6099. /* Enable 16C32 transmitter. */
  6100. spin_lock_irqsave(&info->irq_spinlock,flags);
  6101. /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
  6102. usc_TCmd( info, TCmd_SendFrame );
  6103. usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
  6104. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6105. /******************************/
  6106. /* WAIT FOR TRANSMIT COMPLETE */
  6107. /******************************/
  6108. /* Wait 100ms */
  6109. EndTime = jiffies + msecs_to_jiffies(100);
  6110. /* While timer not expired wait for transmit complete */
  6111. spin_lock_irqsave(&info->irq_spinlock,flags);
  6112. status = usc_InReg( info, TCSR );
  6113. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6114. while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
  6115. if (time_after(jiffies, EndTime)) {
  6116. rc = FALSE;
  6117. break;
  6118. }
  6119. spin_lock_irqsave(&info->irq_spinlock,flags);
  6120. status = usc_InReg( info, TCSR );
  6121. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6122. }
  6123. }
  6124. if ( rc == TRUE ){
  6125. /* CHECK FOR TRANSMIT ERRORS */
  6126. if ( status & (BIT5 + BIT1) )
  6127. rc = FALSE;
  6128. }
  6129. if ( rc == TRUE ) {
  6130. /* WAIT FOR RECEIVE COMPLETE */
  6131. /* Wait 100ms */
  6132. EndTime = jiffies + msecs_to_jiffies(100);
  6133. /* Wait for 16C32 to write receive status to buffer entry. */
  6134. status=info->rx_buffer_list[0].status;
  6135. while ( status == 0 ) {
  6136. if (time_after(jiffies, EndTime)) {
  6137. rc = FALSE;
  6138. break;
  6139. }
  6140. status=info->rx_buffer_list[0].status;
  6141. }
  6142. }
  6143. if ( rc == TRUE ) {
  6144. /* CHECK FOR RECEIVE ERRORS */
  6145. status = info->rx_buffer_list[0].status;
  6146. if ( status & (BIT8 + BIT3 + BIT1) ) {
  6147. /* receive error has occurred */
  6148. rc = FALSE;
  6149. } else {
  6150. if ( memcmp( info->tx_buffer_list[0].virt_addr ,
  6151. info->rx_buffer_list[0].virt_addr, FrameSize ) ){
  6152. rc = FALSE;
  6153. }
  6154. }
  6155. }
  6156. spin_lock_irqsave(&info->irq_spinlock,flags);
  6157. usc_reset( info );
  6158. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6159. /* restore current port options */
  6160. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  6161. return rc;
  6162. } /* end of mgsl_dma_test() */
  6163. /* mgsl_adapter_test()
  6164. *
  6165. * Perform the register, IRQ, and DMA tests for the 16C32.
  6166. *
  6167. * Arguments: info pointer to device instance data
  6168. * Return Value: 0 if success, otherwise -ENODEV
  6169. */
  6170. static int mgsl_adapter_test( struct mgsl_struct *info )
  6171. {
  6172. if ( debug_level >= DEBUG_LEVEL_INFO )
  6173. printk( "%s(%d):Testing device %s\n",
  6174. __FILE__,__LINE__,info->device_name );
  6175. if ( !mgsl_register_test( info ) ) {
  6176. info->init_error = DiagStatus_AddressFailure;
  6177. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  6178. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  6179. return -ENODEV;
  6180. }
  6181. if ( !mgsl_irq_test( info ) ) {
  6182. info->init_error = DiagStatus_IrqFailure;
  6183. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  6184. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  6185. return -ENODEV;
  6186. }
  6187. if ( !mgsl_dma_test( info ) ) {
  6188. info->init_error = DiagStatus_DmaFailure;
  6189. printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
  6190. __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
  6191. return -ENODEV;
  6192. }
  6193. if ( debug_level >= DEBUG_LEVEL_INFO )
  6194. printk( "%s(%d):device %s passed diagnostics\n",
  6195. __FILE__,__LINE__,info->device_name );
  6196. return 0;
  6197. } /* end of mgsl_adapter_test() */
  6198. /* mgsl_memory_test()
  6199. *
  6200. * Test the shared memory on a PCI adapter.
  6201. *
  6202. * Arguments: info pointer to device instance data
  6203. * Return Value: TRUE if test passed, otherwise FALSE
  6204. */
  6205. static BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
  6206. {
  6207. static unsigned long BitPatterns[] =
  6208. { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
  6209. unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
  6210. unsigned long i;
  6211. unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
  6212. unsigned long * TestAddr;
  6213. if ( info->bus_type != MGSL_BUS_TYPE_PCI )
  6214. return TRUE;
  6215. TestAddr = (unsigned long *)info->memory_base;
  6216. /* Test data lines with test pattern at one location. */
  6217. for ( i = 0 ; i < Patterncount ; i++ ) {
  6218. *TestAddr = BitPatterns[i];
  6219. if ( *TestAddr != BitPatterns[i] )
  6220. return FALSE;
  6221. }
  6222. /* Test address lines with incrementing pattern over */
  6223. /* entire address range. */
  6224. for ( i = 0 ; i < TestLimit ; i++ ) {
  6225. *TestAddr = i * 4;
  6226. TestAddr++;
  6227. }
  6228. TestAddr = (unsigned long *)info->memory_base;
  6229. for ( i = 0 ; i < TestLimit ; i++ ) {
  6230. if ( *TestAddr != i * 4 )
  6231. return FALSE;
  6232. TestAddr++;
  6233. }
  6234. memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
  6235. return TRUE;
  6236. } /* End Of mgsl_memory_test() */
  6237. /* mgsl_load_pci_memory()
  6238. *
  6239. * Load a large block of data into the PCI shared memory.
  6240. * Use this instead of memcpy() or memmove() to move data
  6241. * into the PCI shared memory.
  6242. *
  6243. * Notes:
  6244. *
  6245. * This function prevents the PCI9050 interface chip from hogging
  6246. * the adapter local bus, which can starve the 16C32 by preventing
  6247. * 16C32 bus master cycles.
  6248. *
  6249. * The PCI9050 documentation says that the 9050 will always release
  6250. * control of the local bus after completing the current read
  6251. * or write operation.
  6252. *
  6253. * It appears that as long as the PCI9050 write FIFO is full, the
  6254. * PCI9050 treats all of the writes as a single burst transaction
  6255. * and will not release the bus. This causes DMA latency problems
  6256. * at high speeds when copying large data blocks to the shared
  6257. * memory.
  6258. *
  6259. * This function in effect, breaks the a large shared memory write
  6260. * into multiple transations by interleaving a shared memory read
  6261. * which will flush the write FIFO and 'complete' the write
  6262. * transation. This allows any pending DMA request to gain control
  6263. * of the local bus in a timely fasion.
  6264. *
  6265. * Arguments:
  6266. *
  6267. * TargetPtr pointer to target address in PCI shared memory
  6268. * SourcePtr pointer to source buffer for data
  6269. * count count in bytes of data to copy
  6270. *
  6271. * Return Value: None
  6272. */
  6273. static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
  6274. unsigned short count )
  6275. {
  6276. /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
  6277. #define PCI_LOAD_INTERVAL 64
  6278. unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
  6279. unsigned short Index;
  6280. unsigned long Dummy;
  6281. for ( Index = 0 ; Index < Intervalcount ; Index++ )
  6282. {
  6283. memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
  6284. Dummy = *((volatile unsigned long *)TargetPtr);
  6285. TargetPtr += PCI_LOAD_INTERVAL;
  6286. SourcePtr += PCI_LOAD_INTERVAL;
  6287. }
  6288. memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
  6289. } /* End Of mgsl_load_pci_memory() */
  6290. static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
  6291. {
  6292. int i;
  6293. int linecount;
  6294. if (xmit)
  6295. printk("%s tx data:\n",info->device_name);
  6296. else
  6297. printk("%s rx data:\n",info->device_name);
  6298. while(count) {
  6299. if (count > 16)
  6300. linecount = 16;
  6301. else
  6302. linecount = count;
  6303. for(i=0;i<linecount;i++)
  6304. printk("%02X ",(unsigned char)data[i]);
  6305. for(;i<17;i++)
  6306. printk(" ");
  6307. for(i=0;i<linecount;i++) {
  6308. if (data[i]>=040 && data[i]<=0176)
  6309. printk("%c",data[i]);
  6310. else
  6311. printk(".");
  6312. }
  6313. printk("\n");
  6314. data += linecount;
  6315. count -= linecount;
  6316. }
  6317. } /* end of mgsl_trace_block() */
  6318. /* mgsl_tx_timeout()
  6319. *
  6320. * called when HDLC frame times out
  6321. * update stats and do tx completion processing
  6322. *
  6323. * Arguments: context pointer to device instance data
  6324. * Return Value: None
  6325. */
  6326. static void mgsl_tx_timeout(unsigned long context)
  6327. {
  6328. struct mgsl_struct *info = (struct mgsl_struct*)context;
  6329. unsigned long flags;
  6330. if ( debug_level >= DEBUG_LEVEL_INFO )
  6331. printk( "%s(%d):mgsl_tx_timeout(%s)\n",
  6332. __FILE__,__LINE__,info->device_name);
  6333. if(info->tx_active &&
  6334. (info->params.mode == MGSL_MODE_HDLC ||
  6335. info->params.mode == MGSL_MODE_RAW) ) {
  6336. info->icount.txtimeout++;
  6337. }
  6338. spin_lock_irqsave(&info->irq_spinlock,flags);
  6339. info->tx_active = 0;
  6340. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  6341. if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
  6342. usc_loopmode_cancel_transmit( info );
  6343. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6344. #if SYNCLINK_GENERIC_HDLC
  6345. if (info->netcount)
  6346. hdlcdev_tx_done(info);
  6347. else
  6348. #endif
  6349. mgsl_bh_transmit(info);
  6350. } /* end of mgsl_tx_timeout() */
  6351. /* signal that there are no more frames to send, so that
  6352. * line is 'released' by echoing RxD to TxD when current
  6353. * transmission is complete (or immediately if no tx in progress).
  6354. */
  6355. static int mgsl_loopmode_send_done( struct mgsl_struct * info )
  6356. {
  6357. unsigned long flags;
  6358. spin_lock_irqsave(&info->irq_spinlock,flags);
  6359. if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
  6360. if (info->tx_active)
  6361. info->loopmode_send_done_requested = TRUE;
  6362. else
  6363. usc_loopmode_send_done(info);
  6364. }
  6365. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6366. return 0;
  6367. }
  6368. /* release the line by echoing RxD to TxD
  6369. * upon completion of a transmit frame
  6370. */
  6371. static void usc_loopmode_send_done( struct mgsl_struct * info )
  6372. {
  6373. info->loopmode_send_done_requested = FALSE;
  6374. /* clear CMR:13 to 0 to start echoing RxData to TxData */
  6375. info->cmr_value &= ~BIT13;
  6376. usc_OutReg(info, CMR, info->cmr_value);
  6377. }
  6378. /* abort a transmit in progress while in HDLC LoopMode
  6379. */
  6380. static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
  6381. {
  6382. /* reset tx dma channel and purge TxFifo */
  6383. usc_RTCmd( info, RTCmd_PurgeTxFifo );
  6384. usc_DmaCmd( info, DmaCmd_ResetTxChannel );
  6385. usc_loopmode_send_done( info );
  6386. }
  6387. /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
  6388. * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
  6389. * we must clear CMR:13 to begin repeating TxData to RxData
  6390. */
  6391. static void usc_loopmode_insert_request( struct mgsl_struct * info )
  6392. {
  6393. info->loopmode_insert_requested = TRUE;
  6394. /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
  6395. * begin repeating TxData on RxData (complete insertion)
  6396. */
  6397. usc_OutReg( info, RICR,
  6398. (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
  6399. /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
  6400. info->cmr_value |= BIT13;
  6401. usc_OutReg(info, CMR, info->cmr_value);
  6402. }
  6403. /* return 1 if station is inserted into the loop, otherwise 0
  6404. */
  6405. static int usc_loopmode_active( struct mgsl_struct * info)
  6406. {
  6407. return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
  6408. }
  6409. #if SYNCLINK_GENERIC_HDLC
  6410. /**
  6411. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  6412. * set encoding and frame check sequence (FCS) options
  6413. *
  6414. * dev pointer to network device structure
  6415. * encoding serial encoding setting
  6416. * parity FCS setting
  6417. *
  6418. * returns 0 if success, otherwise error code
  6419. */
  6420. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  6421. unsigned short parity)
  6422. {
  6423. struct mgsl_struct *info = dev_to_port(dev);
  6424. unsigned char new_encoding;
  6425. unsigned short new_crctype;
  6426. /* return error if TTY interface open */
  6427. if (info->count)
  6428. return -EBUSY;
  6429. switch (encoding)
  6430. {
  6431. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  6432. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  6433. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  6434. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  6435. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  6436. default: return -EINVAL;
  6437. }
  6438. switch (parity)
  6439. {
  6440. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  6441. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  6442. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  6443. default: return -EINVAL;
  6444. }
  6445. info->params.encoding = new_encoding;
  6446. info->params.crc_type = new_crctype;
  6447. /* if network interface up, reprogram hardware */
  6448. if (info->netcount)
  6449. mgsl_program_hw(info);
  6450. return 0;
  6451. }
  6452. /**
  6453. * called by generic HDLC layer to send frame
  6454. *
  6455. * skb socket buffer containing HDLC frame
  6456. * dev pointer to network device structure
  6457. *
  6458. * returns 0 if success, otherwise error code
  6459. */
  6460. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  6461. {
  6462. struct mgsl_struct *info = dev_to_port(dev);
  6463. struct net_device_stats *stats = hdlc_stats(dev);
  6464. unsigned long flags;
  6465. if (debug_level >= DEBUG_LEVEL_INFO)
  6466. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  6467. /* stop sending until this frame completes */
  6468. netif_stop_queue(dev);
  6469. /* copy data to device buffers */
  6470. info->xmit_cnt = skb->len;
  6471. mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
  6472. /* update network statistics */
  6473. stats->tx_packets++;
  6474. stats->tx_bytes += skb->len;
  6475. /* done with socket buffer, so free it */
  6476. dev_kfree_skb(skb);
  6477. /* save start time for transmit timeout detection */
  6478. dev->trans_start = jiffies;
  6479. /* start hardware transmitter if necessary */
  6480. spin_lock_irqsave(&info->irq_spinlock,flags);
  6481. if (!info->tx_active)
  6482. usc_start_transmitter(info);
  6483. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6484. return 0;
  6485. }
  6486. /**
  6487. * called by network layer when interface enabled
  6488. * claim resources and initialize hardware
  6489. *
  6490. * dev pointer to network device structure
  6491. *
  6492. * returns 0 if success, otherwise error code
  6493. */
  6494. static int hdlcdev_open(struct net_device *dev)
  6495. {
  6496. struct mgsl_struct *info = dev_to_port(dev);
  6497. int rc;
  6498. unsigned long flags;
  6499. if (debug_level >= DEBUG_LEVEL_INFO)
  6500. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  6501. /* generic HDLC layer open processing */
  6502. if ((rc = hdlc_open(dev)))
  6503. return rc;
  6504. /* arbitrate between network and tty opens */
  6505. spin_lock_irqsave(&info->netlock, flags);
  6506. if (info->count != 0 || info->netcount != 0) {
  6507. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  6508. spin_unlock_irqrestore(&info->netlock, flags);
  6509. return -EBUSY;
  6510. }
  6511. info->netcount=1;
  6512. spin_unlock_irqrestore(&info->netlock, flags);
  6513. /* claim resources and init adapter */
  6514. if ((rc = startup(info)) != 0) {
  6515. spin_lock_irqsave(&info->netlock, flags);
  6516. info->netcount=0;
  6517. spin_unlock_irqrestore(&info->netlock, flags);
  6518. return rc;
  6519. }
  6520. /* assert DTR and RTS, apply hardware settings */
  6521. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  6522. mgsl_program_hw(info);
  6523. /* enable network layer transmit */
  6524. dev->trans_start = jiffies;
  6525. netif_start_queue(dev);
  6526. /* inform generic HDLC layer of current DCD status */
  6527. spin_lock_irqsave(&info->irq_spinlock, flags);
  6528. usc_get_serial_signals(info);
  6529. spin_unlock_irqrestore(&info->irq_spinlock, flags);
  6530. if (info->serial_signals & SerialSignal_DCD)
  6531. netif_carrier_on(dev);
  6532. else
  6533. netif_carrier_off(dev);
  6534. return 0;
  6535. }
  6536. /**
  6537. * called by network layer when interface is disabled
  6538. * shutdown hardware and release resources
  6539. *
  6540. * dev pointer to network device structure
  6541. *
  6542. * returns 0 if success, otherwise error code
  6543. */
  6544. static int hdlcdev_close(struct net_device *dev)
  6545. {
  6546. struct mgsl_struct *info = dev_to_port(dev);
  6547. unsigned long flags;
  6548. if (debug_level >= DEBUG_LEVEL_INFO)
  6549. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  6550. netif_stop_queue(dev);
  6551. /* shutdown adapter and release resources */
  6552. shutdown(info);
  6553. hdlc_close(dev);
  6554. spin_lock_irqsave(&info->netlock, flags);
  6555. info->netcount=0;
  6556. spin_unlock_irqrestore(&info->netlock, flags);
  6557. return 0;
  6558. }
  6559. /**
  6560. * called by network layer to process IOCTL call to network device
  6561. *
  6562. * dev pointer to network device structure
  6563. * ifr pointer to network interface request structure
  6564. * cmd IOCTL command code
  6565. *
  6566. * returns 0 if success, otherwise error code
  6567. */
  6568. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  6569. {
  6570. const size_t size = sizeof(sync_serial_settings);
  6571. sync_serial_settings new_line;
  6572. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  6573. struct mgsl_struct *info = dev_to_port(dev);
  6574. unsigned int flags;
  6575. if (debug_level >= DEBUG_LEVEL_INFO)
  6576. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  6577. /* return error if TTY interface open */
  6578. if (info->count)
  6579. return -EBUSY;
  6580. if (cmd != SIOCWANDEV)
  6581. return hdlc_ioctl(dev, ifr, cmd);
  6582. switch(ifr->ifr_settings.type) {
  6583. case IF_GET_IFACE: /* return current sync_serial_settings */
  6584. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  6585. if (ifr->ifr_settings.size < size) {
  6586. ifr->ifr_settings.size = size; /* data size wanted */
  6587. return -ENOBUFS;
  6588. }
  6589. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6590. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6591. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6592. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  6593. switch (flags){
  6594. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  6595. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  6596. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  6597. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  6598. default: new_line.clock_type = CLOCK_DEFAULT;
  6599. }
  6600. new_line.clock_rate = info->params.clock_speed;
  6601. new_line.loopback = info->params.loopback ? 1:0;
  6602. if (copy_to_user(line, &new_line, size))
  6603. return -EFAULT;
  6604. return 0;
  6605. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  6606. if(!capable(CAP_NET_ADMIN))
  6607. return -EPERM;
  6608. if (copy_from_user(&new_line, line, size))
  6609. return -EFAULT;
  6610. switch (new_line.clock_type)
  6611. {
  6612. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  6613. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  6614. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  6615. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  6616. case CLOCK_DEFAULT: flags = info->params.flags &
  6617. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6618. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6619. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6620. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  6621. default: return -EINVAL;
  6622. }
  6623. if (new_line.loopback != 0 && new_line.loopback != 1)
  6624. return -EINVAL;
  6625. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  6626. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  6627. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  6628. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  6629. info->params.flags |= flags;
  6630. info->params.loopback = new_line.loopback;
  6631. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  6632. info->params.clock_speed = new_line.clock_rate;
  6633. else
  6634. info->params.clock_speed = 0;
  6635. /* if network interface up, reprogram hardware */
  6636. if (info->netcount)
  6637. mgsl_program_hw(info);
  6638. return 0;
  6639. default:
  6640. return hdlc_ioctl(dev, ifr, cmd);
  6641. }
  6642. }
  6643. /**
  6644. * called by network layer when transmit timeout is detected
  6645. *
  6646. * dev pointer to network device structure
  6647. */
  6648. static void hdlcdev_tx_timeout(struct net_device *dev)
  6649. {
  6650. struct mgsl_struct *info = dev_to_port(dev);
  6651. struct net_device_stats *stats = hdlc_stats(dev);
  6652. unsigned long flags;
  6653. if (debug_level >= DEBUG_LEVEL_INFO)
  6654. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  6655. stats->tx_errors++;
  6656. stats->tx_aborted_errors++;
  6657. spin_lock_irqsave(&info->irq_spinlock,flags);
  6658. usc_stop_transmitter(info);
  6659. spin_unlock_irqrestore(&info->irq_spinlock,flags);
  6660. netif_wake_queue(dev);
  6661. }
  6662. /**
  6663. * called by device driver when transmit completes
  6664. * reenable network layer transmit if stopped
  6665. *
  6666. * info pointer to device instance information
  6667. */
  6668. static void hdlcdev_tx_done(struct mgsl_struct *info)
  6669. {
  6670. if (netif_queue_stopped(info->netdev))
  6671. netif_wake_queue(info->netdev);
  6672. }
  6673. /**
  6674. * called by device driver when frame received
  6675. * pass frame to network layer
  6676. *
  6677. * info pointer to device instance information
  6678. * buf pointer to buffer contianing frame data
  6679. * size count of data bytes in buf
  6680. */
  6681. static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
  6682. {
  6683. struct sk_buff *skb = dev_alloc_skb(size);
  6684. struct net_device *dev = info->netdev;
  6685. struct net_device_stats *stats = hdlc_stats(dev);
  6686. if (debug_level >= DEBUG_LEVEL_INFO)
  6687. printk("hdlcdev_rx(%s)\n",dev->name);
  6688. if (skb == NULL) {
  6689. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  6690. stats->rx_dropped++;
  6691. return;
  6692. }
  6693. memcpy(skb_put(skb, size),buf,size);
  6694. skb->protocol = hdlc_type_trans(skb, info->netdev);
  6695. stats->rx_packets++;
  6696. stats->rx_bytes += size;
  6697. netif_rx(skb);
  6698. info->netdev->last_rx = jiffies;
  6699. }
  6700. /**
  6701. * called by device driver when adding device instance
  6702. * do generic HDLC initialization
  6703. *
  6704. * info pointer to device instance information
  6705. *
  6706. * returns 0 if success, otherwise error code
  6707. */
  6708. static int hdlcdev_init(struct mgsl_struct *info)
  6709. {
  6710. int rc;
  6711. struct net_device *dev;
  6712. hdlc_device *hdlc;
  6713. /* allocate and initialize network and HDLC layer objects */
  6714. if (!(dev = alloc_hdlcdev(info))) {
  6715. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  6716. return -ENOMEM;
  6717. }
  6718. /* for network layer reporting purposes only */
  6719. dev->base_addr = info->io_base;
  6720. dev->irq = info->irq_level;
  6721. dev->dma = info->dma_level;
  6722. /* network layer callbacks and settings */
  6723. dev->do_ioctl = hdlcdev_ioctl;
  6724. dev->open = hdlcdev_open;
  6725. dev->stop = hdlcdev_close;
  6726. dev->tx_timeout = hdlcdev_tx_timeout;
  6727. dev->watchdog_timeo = 10*HZ;
  6728. dev->tx_queue_len = 50;
  6729. /* generic HDLC layer callbacks and settings */
  6730. hdlc = dev_to_hdlc(dev);
  6731. hdlc->attach = hdlcdev_attach;
  6732. hdlc->xmit = hdlcdev_xmit;
  6733. /* register objects with HDLC layer */
  6734. if ((rc = register_hdlc_device(dev))) {
  6735. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  6736. free_netdev(dev);
  6737. return rc;
  6738. }
  6739. info->netdev = dev;
  6740. return 0;
  6741. }
  6742. /**
  6743. * called by device driver when removing device instance
  6744. * do generic HDLC cleanup
  6745. *
  6746. * info pointer to device instance information
  6747. */
  6748. static void hdlcdev_exit(struct mgsl_struct *info)
  6749. {
  6750. unregister_hdlc_device(info->netdev);
  6751. free_netdev(info->netdev);
  6752. info->netdev = NULL;
  6753. }
  6754. #endif /* CONFIG_HDLC */
  6755. static int __devinit synclink_init_one (struct pci_dev *dev,
  6756. const struct pci_device_id *ent)
  6757. {
  6758. struct mgsl_struct *info;
  6759. if (pci_enable_device(dev)) {
  6760. printk("error enabling pci device %p\n", dev);
  6761. return -EIO;
  6762. }
  6763. if (!(info = mgsl_allocate_device())) {
  6764. printk("can't allocate device instance data.\n");
  6765. return -EIO;
  6766. }
  6767. /* Copy user configuration info to device instance data */
  6768. info->io_base = pci_resource_start(dev, 2);
  6769. info->irq_level = dev->irq;
  6770. info->phys_memory_base = pci_resource_start(dev, 3);
  6771. /* Because veremap only works on page boundaries we must map
  6772. * a larger area than is actually implemented for the LCR
  6773. * memory range. We map a full page starting at the page boundary.
  6774. */
  6775. info->phys_lcr_base = pci_resource_start(dev, 0);
  6776. info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
  6777. info->phys_lcr_base &= ~(PAGE_SIZE-1);
  6778. info->bus_type = MGSL_BUS_TYPE_PCI;
  6779. info->io_addr_size = 8;
  6780. info->irq_flags = IRQF_SHARED;
  6781. if (dev->device == 0x0210) {
  6782. /* Version 1 PCI9030 based universal PCI adapter */
  6783. info->misc_ctrl_value = 0x007c4080;
  6784. info->hw_version = 1;
  6785. } else {
  6786. /* Version 0 PCI9050 based 5V PCI adapter
  6787. * A PCI9050 bug prevents reading LCR registers if
  6788. * LCR base address bit 7 is set. Maintain shadow
  6789. * value so we can write to LCR misc control reg.
  6790. */
  6791. info->misc_ctrl_value = 0x087e4546;
  6792. info->hw_version = 0;
  6793. }
  6794. mgsl_add_device(info);
  6795. return 0;
  6796. }
  6797. static void __devexit synclink_remove_one (struct pci_dev *dev)
  6798. {
  6799. }