scc.h 16 KB

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  1. /*
  2. * atari_SCC.h: Definitions for the Am8530 Serial Communications Controller
  3. *
  4. * Copyright 1994 Roman Hodek <Roman.Hodek@informatik.uni-erlangen.de>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive
  8. * for more details.
  9. *
  10. */
  11. #ifndef _SCC_H
  12. #define _SCC_H
  13. #include <linux/delay.h>
  14. /* Special configuration ioctls for the Atari SCC5380 Serial
  15. * Communications Controller
  16. */
  17. /* ioctl command codes */
  18. #define TIOCGATSCC 0x54c0 /* get SCC configuration */
  19. #define TIOCSATSCC 0x54c1 /* set SCC configuration */
  20. #define TIOCDATSCC 0x54c2 /* reset configuration to defaults */
  21. /* Clock sources */
  22. #define CLK_RTxC 0
  23. #define CLK_TRxC 1
  24. #define CLK_PCLK 2
  25. /* baud_bases for the common clocks in the Atari. These are the real
  26. * frequencies divided by 16.
  27. */
  28. #define SCC_BAUD_BASE_TIMC 19200 /* 0.3072 MHz from TT-MFP, Timer C */
  29. #define SCC_BAUD_BASE_BCLK 153600 /* 2.4576 MHz */
  30. #define SCC_BAUD_BASE_PCLK4 229500 /* 3.6720 MHz */
  31. #define SCC_BAUD_BASE_PCLK 503374 /* 8.0539763 MHz */
  32. #define SCC_BAUD_BASE_NONE 0 /* for not connected or unused
  33. * clock sources */
  34. /* The SCC clock configuration structure */
  35. struct scc_clock_config {
  36. unsigned RTxC_base; /* base_baud of RTxC */
  37. unsigned TRxC_base; /* base_baud of TRxC */
  38. unsigned PCLK_base; /* base_baud of PCLK, both channels! */
  39. struct {
  40. unsigned clksrc; /* CLK_RTxC, CLK_TRxC or CLK_PCLK */
  41. unsigned divisor; /* divisor for base baud, valid values:
  42. * see below */
  43. } baud_table[17]; /* For 50, 75, 110, 135, 150, 200, 300,
  44. * 600, 1200, 1800, 2400, 4800, 9600,
  45. * 19200, 38400, 57600 and 115200 bps.
  46. * The last two could be replaced by
  47. * other rates > 38400 if they're not
  48. * possible.
  49. */
  50. };
  51. /* The following divisors are valid:
  52. *
  53. * - CLK_RTxC: 1 or even (1, 2 and 4 are the direct modes, > 4 use
  54. * the BRG)
  55. *
  56. * - CLK_TRxC: 1, 2 or 4 (no BRG, only direct modes possible)
  57. *
  58. * - CLK_PCLK: >= 4 and even (no direct modes, only BRG)
  59. *
  60. */
  61. struct scc_port {
  62. struct gs_port gs;
  63. volatile unsigned char *ctrlp;
  64. volatile unsigned char *datap;
  65. int x_char; /* xon/xoff character */
  66. int c_dcd;
  67. int channel;
  68. struct scc_port *port_a; /* Reference to port A and B */
  69. struct scc_port *port_b; /* structs for reg access */
  70. };
  71. #define SCC_MAGIC 0x52696368
  72. /***********************************************************************/
  73. /* */
  74. /* Register Names */
  75. /* */
  76. /***********************************************************************/
  77. /* The SCC documentation gives no explicit names to the registers,
  78. * they're just called WR0..15 and RR0..15. To make the source code
  79. * better readable and make the transparent write reg read access (see
  80. * below) possible, I christen them here with self-invented names.
  81. * Note that (real) read registers are assigned numbers 16..31. WR7'
  82. * has number 33.
  83. */
  84. #define COMMAND_REG 0 /* wo */
  85. #define INT_AND_DMA_REG 1 /* wo */
  86. #define INT_VECTOR_REG 2 /* rw, common to both channels */
  87. #define RX_CTRL_REG 3 /* rw */
  88. #define AUX1_CTRL_REG 4 /* rw */
  89. #define TX_CTRL_REG 5 /* rw */
  90. #define SYNC_ADR_REG 6 /* wo */
  91. #define SYNC_CHAR_REG 7 /* wo */
  92. #define SDLC_OPTION_REG 33 /* wo */
  93. #define TX_DATA_REG 8 /* wo */
  94. #define MASTER_INT_CTRL 9 /* wo, common to both channels */
  95. #define AUX2_CTRL_REG 10 /* rw */
  96. #define CLK_CTRL_REG 11 /* wo */
  97. #define TIMER_LOW_REG 12 /* rw */
  98. #define TIMER_HIGH_REG 13 /* rw */
  99. #define DPLL_CTRL_REG 14 /* wo */
  100. #define INT_CTRL_REG 15 /* rw */
  101. #define STATUS_REG 16 /* ro */
  102. #define SPCOND_STATUS_REG 17 /* wo */
  103. /* RR2 is WR2 for Channel A, Channel B gives vector + current status: */
  104. #define CURR_VECTOR_REG 18 /* Ch. B only, Ch. A for rw */
  105. #define INT_PENDING_REG 19 /* Channel A only! */
  106. /* RR4 is WR4, if b6(MR7') == 1 */
  107. /* RR5 is WR5, if b6(MR7') == 1 */
  108. #define FS_FIFO_LOW_REG 22 /* ro */
  109. #define FS_FIFO_HIGH_REG 23 /* ro */
  110. #define RX_DATA_REG 24 /* ro */
  111. /* RR9 is WR3, if b6(MR7') == 1 */
  112. #define DPLL_STATUS_REG 26 /* ro */
  113. /* RR11 is WR10, if b6(MR7') == 1 */
  114. /* RR12 is WR12 */
  115. /* RR13 is WR13 */
  116. /* RR14 not present */
  117. /* RR15 is WR15 */
  118. /***********************************************************************/
  119. /* */
  120. /* Register Values */
  121. /* */
  122. /***********************************************************************/
  123. /* WR0: COMMAND_REG "CR" */
  124. #define CR_RX_CRC_RESET 0x40
  125. #define CR_TX_CRC_RESET 0x80
  126. #define CR_TX_UNDERRUN_RESET 0xc0
  127. #define CR_EXTSTAT_RESET 0x10
  128. #define CR_SEND_ABORT 0x18
  129. #define CR_ENAB_INT_NEXT_RX 0x20
  130. #define CR_TX_PENDING_RESET 0x28
  131. #define CR_ERROR_RESET 0x30
  132. #define CR_HIGHEST_IUS_RESET 0x38
  133. /* WR1: INT_AND_DMA_REG "IDR" */
  134. #define IDR_EXTSTAT_INT_ENAB 0x01
  135. #define IDR_TX_INT_ENAB 0x02
  136. #define IDR_PARERR_AS_SPCOND 0x04
  137. #define IDR_RX_INT_DISAB 0x00
  138. #define IDR_RX_INT_FIRST 0x08
  139. #define IDR_RX_INT_ALL 0x10
  140. #define IDR_RX_INT_SPCOND 0x18
  141. #define IDR_RX_INT_MASK 0x18
  142. #define IDR_WAITREQ_RX 0x20
  143. #define IDR_WAITREQ_IS_REQ 0x40
  144. #define IDR_WAITREQ_ENAB 0x80
  145. /* WR3: RX_CTRL_REG "RCR" */
  146. #define RCR_RX_ENAB 0x01
  147. #define RCR_DISCARD_SYNC_CHARS 0x02
  148. #define RCR_ADDR_SEARCH 0x04
  149. #define RCR_CRC_ENAB 0x08
  150. #define RCR_SEARCH_MODE 0x10
  151. #define RCR_AUTO_ENAB_MODE 0x20
  152. #define RCR_CHSIZE_MASK 0xc0
  153. #define RCR_CHSIZE_5 0x00
  154. #define RCR_CHSIZE_6 0x40
  155. #define RCR_CHSIZE_7 0x80
  156. #define RCR_CHSIZE_8 0xc0
  157. /* WR4: AUX1_CTRL_REG "A1CR" */
  158. #define A1CR_PARITY_MASK 0x03
  159. #define A1CR_PARITY_NONE 0x00
  160. #define A1CR_PARITY_ODD 0x01
  161. #define A1CR_PARITY_EVEN 0x03
  162. #define A1CR_MODE_MASK 0x0c
  163. #define A1CR_MODE_SYNCR 0x00
  164. #define A1CR_MODE_ASYNC_1 0x04
  165. #define A1CR_MODE_ASYNC_15 0x08
  166. #define A1CR_MODE_ASYNC_2 0x0c
  167. #define A1CR_SYNCR_MODE_MASK 0x30
  168. #define A1CR_SYNCR_MONOSYNC 0x00
  169. #define A1CR_SYNCR_BISYNC 0x10
  170. #define A1CR_SYNCR_SDLC 0x20
  171. #define A1CR_SYNCR_EXTCSYNC 0x30
  172. #define A1CR_CLKMODE_MASK 0xc0
  173. #define A1CR_CLKMODE_x1 0x00
  174. #define A1CR_CLKMODE_x16 0x40
  175. #define A1CR_CLKMODE_x32 0x80
  176. #define A1CR_CLKMODE_x64 0xc0
  177. /* WR5: TX_CTRL_REG "TCR" */
  178. #define TCR_TX_CRC_ENAB 0x01
  179. #define TCR_RTS 0x02
  180. #define TCR_USE_CRC_CCITT 0x00
  181. #define TCR_USE_CRC_16 0x04
  182. #define TCR_TX_ENAB 0x08
  183. #define TCR_SEND_BREAK 0x10
  184. #define TCR_CHSIZE_MASK 0x60
  185. #define TCR_CHSIZE_5 0x00
  186. #define TCR_CHSIZE_6 0x20
  187. #define TCR_CHSIZE_7 0x40
  188. #define TCR_CHSIZE_8 0x60
  189. #define TCR_DTR 0x80
  190. /* WR7': SLDC_OPTION_REG "SOR" */
  191. #define SOR_AUTO_TX_ENAB 0x01
  192. #define SOR_AUTO_EOM_RESET 0x02
  193. #define SOR_AUTO_RTS_MODE 0x04
  194. #define SOR_NRZI_DISAB_HIGH 0x08
  195. #define SOR_ALT_DTRREQ_TIMING 0x10
  196. #define SOR_READ_CRC_CHARS 0x20
  197. #define SOR_EXTENDED_REG_ACCESS 0x40
  198. /* WR9: MASTER_INT_CTRL "MIC" */
  199. #define MIC_VEC_INCL_STAT 0x01
  200. #define MIC_NO_VECTOR 0x02
  201. #define MIC_DISAB_LOWER_CHAIN 0x04
  202. #define MIC_MASTER_INT_ENAB 0x08
  203. #define MIC_STATUS_HIGH 0x10
  204. #define MIC_IGN_INTACK 0x20
  205. #define MIC_NO_RESET 0x00
  206. #define MIC_CH_A_RESET 0x40
  207. #define MIC_CH_B_RESET 0x80
  208. #define MIC_HARD_RESET 0xc0
  209. /* WR10: AUX2_CTRL_REG "A2CR" */
  210. #define A2CR_SYNC_6 0x01
  211. #define A2CR_LOOP_MODE 0x02
  212. #define A2CR_ABORT_ON_UNDERRUN 0x04
  213. #define A2CR_MARK_IDLE 0x08
  214. #define A2CR_GO_ACTIVE_ON_POLL 0x10
  215. #define A2CR_CODING_MASK 0x60
  216. #define A2CR_CODING_NRZ 0x00
  217. #define A2CR_CODING_NRZI 0x20
  218. #define A2CR_CODING_FM1 0x40
  219. #define A2CR_CODING_FM0 0x60
  220. #define A2CR_PRESET_CRC_1 0x80
  221. /* WR11: CLK_CTRL_REG "CCR" */
  222. #define CCR_TRxCOUT_MASK 0x03
  223. #define CCR_TRxCOUT_XTAL 0x00
  224. #define CCR_TRxCOUT_TXCLK 0x01
  225. #define CCR_TRxCOUT_BRG 0x02
  226. #define CCR_TRxCOUT_DPLL 0x03
  227. #define CCR_TRxC_OUTPUT 0x04
  228. #define CCR_TXCLK_MASK 0x18
  229. #define CCR_TXCLK_RTxC 0x00
  230. #define CCR_TXCLK_TRxC 0x08
  231. #define CCR_TXCLK_BRG 0x10
  232. #define CCR_TXCLK_DPLL 0x18
  233. #define CCR_RXCLK_MASK 0x60
  234. #define CCR_RXCLK_RTxC 0x00
  235. #define CCR_RXCLK_TRxC 0x20
  236. #define CCR_RXCLK_BRG 0x40
  237. #define CCR_RXCLK_DPLL 0x60
  238. #define CCR_RTxC_XTAL 0x80
  239. /* WR14: DPLL_CTRL_REG "DCR" */
  240. #define DCR_BRG_ENAB 0x01
  241. #define DCR_BRG_USE_PCLK 0x02
  242. #define DCR_DTRREQ_IS_REQ 0x04
  243. #define DCR_AUTO_ECHO 0x08
  244. #define DCR_LOCAL_LOOPBACK 0x10
  245. #define DCR_DPLL_EDGE_SEARCH 0x20
  246. #define DCR_DPLL_ERR_RESET 0x40
  247. #define DCR_DPLL_DISAB 0x60
  248. #define DCR_DPLL_CLK_BRG 0x80
  249. #define DCR_DPLL_CLK_RTxC 0xa0
  250. #define DCR_DPLL_FM 0xc0
  251. #define DCR_DPLL_NRZI 0xe0
  252. /* WR15: INT_CTRL_REG "ICR" */
  253. #define ICR_OPTIONREG_SELECT 0x01
  254. #define ICR_ENAB_BRG_ZERO_INT 0x02
  255. #define ICR_USE_FS_FIFO 0x04
  256. #define ICR_ENAB_DCD_INT 0x08
  257. #define ICR_ENAB_SYNC_INT 0x10
  258. #define ICR_ENAB_CTS_INT 0x20
  259. #define ICR_ENAB_UNDERRUN_INT 0x40
  260. #define ICR_ENAB_BREAK_INT 0x80
  261. /* RR0: STATUS_REG "SR" */
  262. #define SR_CHAR_AVAIL 0x01
  263. #define SR_BRG_ZERO 0x02
  264. #define SR_TX_BUF_EMPTY 0x04
  265. #define SR_DCD 0x08
  266. #define SR_SYNC_ABORT 0x10
  267. #define SR_CTS 0x20
  268. #define SR_TX_UNDERRUN 0x40
  269. #define SR_BREAK 0x80
  270. /* RR1: SPCOND_STATUS_REG "SCSR" */
  271. #define SCSR_ALL_SENT 0x01
  272. #define SCSR_RESIDUAL_MASK 0x0e
  273. #define SCSR_PARITY_ERR 0x10
  274. #define SCSR_RX_OVERRUN 0x20
  275. #define SCSR_CRC_FRAME_ERR 0x40
  276. #define SCSR_END_OF_FRAME 0x80
  277. /* RR3: INT_PENDING_REG "IPR" */
  278. #define IPR_B_EXTSTAT 0x01
  279. #define IPR_B_TX 0x02
  280. #define IPR_B_RX 0x04
  281. #define IPR_A_EXTSTAT 0x08
  282. #define IPR_A_TX 0x10
  283. #define IPR_A_RX 0x20
  284. /* RR7: FS_FIFO_HIGH_REG "FFHR" */
  285. #define FFHR_CNT_MASK 0x3f
  286. #define FFHR_IS_FROM_FIFO 0x40
  287. #define FFHR_FIFO_OVERRUN 0x80
  288. /* RR10: DPLL_STATUS_REG "DSR" */
  289. #define DSR_ON_LOOP 0x02
  290. #define DSR_ON_LOOP_SENDING 0x10
  291. #define DSR_TWO_CLK_MISSING 0x40
  292. #define DSR_ONE_CLK_MISSING 0x80
  293. /***********************************************************************/
  294. /* */
  295. /* Register Access */
  296. /* */
  297. /***********************************************************************/
  298. /* The SCC needs 3.5 PCLK cycles recovery time between to register
  299. * accesses. PCLK runs with 8 MHz on an Atari, so this delay is 3.5 *
  300. * 125 ns = 437.5 ns. This is too short for udelay().
  301. * 10/16/95: A tstb mfp.par_dt_reg takes 600ns (sure?) and thus should be
  302. * quite right
  303. */
  304. #define scc_reg_delay() \
  305. do { \
  306. if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147) \
  307. __asm__ __volatile__ ( " nop; nop"); \
  308. else if (MACH_IS_ATARI) \
  309. __asm__ __volatile__ ( "tstb %0" : : "g" (*_scc_del) : "cc" );\
  310. } while (0)
  311. static unsigned char scc_shadow[2][16];
  312. /* The following functions should relax the somehow complicated
  313. * register access of the SCC. _SCCwrite() stores all written values
  314. * (except for WR0 and WR8) in shadow registers for later recall. This
  315. * removes the burden of remembering written values as needed. The
  316. * extra work of storing the value doesn't count, since a delay is
  317. * needed after a SCC access anyway. Additionally, _SCCwrite() manages
  318. * writes to WR0 and WR8 differently, because these can be accessed
  319. * directly with less overhead. Another special case are WR7 and WR7'.
  320. * _SCCwrite automatically checks what of this registers is selected
  321. * and changes b0 of WR15 if needed.
  322. *
  323. * _SCCread() for standard read registers is straightforward, except
  324. * for RR2 (split into two "virtual" registers: one for the value
  325. * written to WR2 (from the shadow) and one for the vector including
  326. * status from RR2, Ch. B) and RR3. The latter must be read from
  327. * Channel A, because it reads as all zeros on Ch. B. RR0 and RR8 can
  328. * be accessed directly as before.
  329. *
  330. * The two inline function contain complicated switch statements. But
  331. * I rely on regno and final_delay being constants, so gcc can reduce
  332. * the whole stuff to just some assembler statements.
  333. *
  334. * _SCCwrite and _SCCread aren't intended to be used directly under
  335. * normal circumstances. The macros SCCread[_ND] and SCCwrite[_ND] are
  336. * for that purpose. They assume that a local variable 'port' is
  337. * declared and pointing to the port's scc_struct entry. The
  338. * variants with "_NB" appended should be used if no other SCC
  339. * accesses follow immediately (within 0.5 usecs). They just skip the
  340. * final delay nops.
  341. *
  342. * Please note that accesses to SCC registers should only take place
  343. * when interrupts are turned off (at least if SCC interrupts are
  344. * enabled). Otherwise, an interrupt could interfere with the
  345. * two-stage accessing process.
  346. *
  347. */
  348. static __inline__ void _SCCwrite(
  349. struct scc_port *port,
  350. unsigned char *shadow,
  351. volatile unsigned char *_scc_del,
  352. int regno,
  353. unsigned char val, int final_delay )
  354. {
  355. switch( regno ) {
  356. case COMMAND_REG:
  357. /* WR0 can be written directly without pointing */
  358. *port->ctrlp = val;
  359. break;
  360. case SYNC_CHAR_REG:
  361. /* For WR7, first set b0 of WR15 to 0, if needed */
  362. if (shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT) {
  363. *port->ctrlp = 15;
  364. shadow[INT_CTRL_REG] &= ~ICR_OPTIONREG_SELECT;
  365. scc_reg_delay();
  366. *port->ctrlp = shadow[INT_CTRL_REG];
  367. scc_reg_delay();
  368. }
  369. goto normal_case;
  370. case SDLC_OPTION_REG:
  371. /* For WR7', first set b0 of WR15 to 1, if needed */
  372. if (!(shadow[INT_CTRL_REG] & ICR_OPTIONREG_SELECT)) {
  373. *port->ctrlp = 15;
  374. shadow[INT_CTRL_REG] |= ICR_OPTIONREG_SELECT;
  375. scc_reg_delay();
  376. *port->ctrlp = shadow[INT_CTRL_REG];
  377. scc_reg_delay();
  378. }
  379. *port->ctrlp = 7;
  380. shadow[8] = val; /* WR7' shadowed at WR8 */
  381. scc_reg_delay();
  382. *port->ctrlp = val;
  383. break;
  384. case TX_DATA_REG: /* WR8 */
  385. /* TX_DATA_REG can be accessed directly on some h/w */
  386. if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
  387. {
  388. *port->ctrlp = regno;
  389. scc_reg_delay();
  390. *port->ctrlp = val;
  391. }
  392. else
  393. *port->datap = val;
  394. break;
  395. case MASTER_INT_CTRL:
  396. *port->ctrlp = regno;
  397. val &= 0x3f; /* bits 6..7 are the reset commands */
  398. scc_shadow[0][regno] = val;
  399. scc_reg_delay();
  400. *port->ctrlp = val;
  401. break;
  402. case DPLL_CTRL_REG:
  403. *port->ctrlp = regno;
  404. val &= 0x1f; /* bits 5..7 are the DPLL commands */
  405. shadow[regno] = val;
  406. scc_reg_delay();
  407. *port->ctrlp = val;
  408. break;
  409. case 1 ... 6:
  410. case 10 ... 13:
  411. case 15:
  412. normal_case:
  413. *port->ctrlp = regno;
  414. shadow[regno] = val;
  415. scc_reg_delay();
  416. *port->ctrlp = val;
  417. break;
  418. default:
  419. printk( "Bad SCC write access to WR%d\n", regno );
  420. break;
  421. }
  422. if (final_delay)
  423. scc_reg_delay();
  424. }
  425. static __inline__ unsigned char _SCCread(
  426. struct scc_port *port,
  427. unsigned char *shadow,
  428. volatile unsigned char *_scc_del,
  429. int regno, int final_delay )
  430. {
  431. unsigned char rv;
  432. switch( regno ) {
  433. /* --- real read registers --- */
  434. case STATUS_REG:
  435. rv = *port->ctrlp;
  436. break;
  437. case INT_PENDING_REG:
  438. /* RR3: read only from Channel A! */
  439. port = port->port_a;
  440. goto normal_case;
  441. case RX_DATA_REG:
  442. /* RR8 can be accessed directly on some h/w */
  443. if (MACH_IS_MVME16x || MACH_IS_BVME6000 || MACH_IS_MVME147)
  444. {
  445. *port->ctrlp = 8;
  446. scc_reg_delay();
  447. rv = *port->ctrlp;
  448. }
  449. else
  450. rv = *port->datap;
  451. break;
  452. case CURR_VECTOR_REG:
  453. /* RR2 (vector including status) from Ch. B */
  454. port = port->port_b;
  455. goto normal_case;
  456. /* --- reading write registers: access the shadow --- */
  457. case 1 ... 7:
  458. case 10 ... 15:
  459. return shadow[regno]; /* no final delay! */
  460. /* WR7' is special, because it is shadowed at the place of WR8 */
  461. case SDLC_OPTION_REG:
  462. return shadow[8]; /* no final delay! */
  463. /* WR9 is special too, because it is common for both channels */
  464. case MASTER_INT_CTRL:
  465. return scc_shadow[0][9]; /* no final delay! */
  466. default:
  467. printk( "Bad SCC read access to %cR%d\n", (regno & 16) ? 'R' : 'W',
  468. regno & ~16 );
  469. break;
  470. case SPCOND_STATUS_REG:
  471. case FS_FIFO_LOW_REG:
  472. case FS_FIFO_HIGH_REG:
  473. case DPLL_STATUS_REG:
  474. normal_case:
  475. *port->ctrlp = regno & 0x0f;
  476. scc_reg_delay();
  477. rv = *port->ctrlp;
  478. break;
  479. }
  480. if (final_delay)
  481. scc_reg_delay();
  482. return rv;
  483. }
  484. #define SCC_ACCESS_INIT(port) \
  485. unsigned char *_scc_shadow = &scc_shadow[port->channel][0]
  486. #define SCCwrite(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),1)
  487. #define SCCwrite_NB(reg,val) _SCCwrite(port,_scc_shadow,scc_del,(reg),(val),0)
  488. #define SCCread(reg) _SCCread(port,_scc_shadow,scc_del,(reg),1)
  489. #define SCCread_NB(reg) _SCCread(port,_scc_shadow,scc_del,(reg),0)
  490. #define SCCmod(reg,and,or) SCCwrite((reg),(SCCread(reg)&(and))|(or))
  491. #endif /* _SCC_H */