rocket_int.h 43 KB

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  1. /*
  2. * rocket_int.h --- internal header file for rocket.c
  3. *
  4. * Written by Theodore Ts'o, Copyright 1997.
  5. * Copyright 1997 Comtrol Corporation.
  6. *
  7. */
  8. /*
  9. * Definition of the types in rcktpt_type
  10. */
  11. #define ROCKET_TYPE_NORMAL 0
  12. #define ROCKET_TYPE_MODEM 1
  13. #define ROCKET_TYPE_MODEMII 2
  14. #define ROCKET_TYPE_MODEMIII 3
  15. #define ROCKET_TYPE_PC104 4
  16. #include <asm/io.h>
  17. #include <asm/byteorder.h>
  18. typedef unsigned char Byte_t;
  19. typedef unsigned int ByteIO_t;
  20. typedef unsigned int Word_t;
  21. typedef unsigned int WordIO_t;
  22. typedef unsigned long DWord_t;
  23. typedef unsigned int DWordIO_t;
  24. /*
  25. * Note! Normally the Linux I/O macros already take care of
  26. * byte-swapping the I/O instructions. However, all accesses using
  27. * sOutDW aren't really 32-bit accesses, but should be handled in byte
  28. * order. Hence the use of the cpu_to_le32() macro to byte-swap
  29. * things to no-op the byte swapping done by the big-endian outl()
  30. * instruction.
  31. */
  32. #ifdef ROCKET_DEBUG_IO
  33. static inline void sOutB(unsigned short port, unsigned char value)
  34. {
  35. #ifdef ROCKET_DEBUG_IO
  36. printk("sOutB(%x, %x)...", port, value);
  37. #endif
  38. outb_p(value, port);
  39. }
  40. static inline void sOutW(unsigned short port, unsigned short value)
  41. {
  42. #ifdef ROCKET_DEBUG_IO
  43. printk("sOutW(%x, %x)...", port, value);
  44. #endif
  45. outw_p(value, port);
  46. }
  47. static inline void sOutDW(unsigned short port, unsigned long value)
  48. {
  49. #ifdef ROCKET_DEBUG_IO
  50. printk("sOutDW(%x, %lx)...", port, value);
  51. #endif
  52. outl_p(cpu_to_le32(value), port);
  53. }
  54. static inline unsigned char sInB(unsigned short port)
  55. {
  56. return inb_p(port);
  57. }
  58. static inline unsigned short sInW(unsigned short port)
  59. {
  60. return inw_p(port);
  61. }
  62. #else /* !ROCKET_DEBUG_IO */
  63. #define sOutB(a, b) outb_p(b, a)
  64. #define sOutW(a, b) outw_p(b, a)
  65. #define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
  66. #define sInB(a) (inb_p(a))
  67. #define sInW(a) (inw_p(a))
  68. #endif /* ROCKET_DEBUG_IO */
  69. /* This is used to move arrays of bytes so byte swapping isn't appropriate. */
  70. #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
  71. #define sInStrW(port, addr, count) if (count) insw(port, addr, count)
  72. #define CTL_SIZE 8
  73. #define AIOP_CTL_SIZE 4
  74. #define CHAN_AIOP_SIZE 8
  75. #define MAX_PORTS_PER_AIOP 8
  76. #define MAX_AIOPS_PER_BOARD 4
  77. #define MAX_PORTS_PER_BOARD 32
  78. /* Bus type ID */
  79. #define isISA 0
  80. #define isPCI 1
  81. #define isMC 2
  82. /* Controller ID numbers */
  83. #define CTLID_NULL -1 /* no controller exists */
  84. #define CTLID_0001 0x0001 /* controller release 1 */
  85. /* AIOP ID numbers, identifies AIOP type implementing channel */
  86. #define AIOPID_NULL -1 /* no AIOP or channel exists */
  87. #define AIOPID_0001 0x0001 /* AIOP release 1 */
  88. #define NULLDEV -1 /* identifies non-existant device */
  89. #define NULLCTL -1 /* identifies non-existant controller */
  90. #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
  91. #define NULLAIOP -1 /* identifies non-existant AIOP */
  92. #define NULLCHAN -1 /* identifies non-existant channel */
  93. /************************************************************************
  94. Global Register Offsets - Direct Access - Fixed values
  95. ************************************************************************/
  96. #define _CMD_REG 0x38 /* Command Register 8 Write */
  97. #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
  98. #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
  99. #define _UNUSED 0x3B /* Unused 8 */
  100. #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
  101. #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
  102. /************************************************************************
  103. Channel Register Offsets for 1st channel in AIOP - Direct Access
  104. ************************************************************************/
  105. #define _TD0 0x00 /* Transmit Data 16 Write */
  106. #define _RD0 0x00 /* Receive Data 16 Read */
  107. #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
  108. #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
  109. #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
  110. /************************************************************************
  111. Tx Control Register Offsets - Indexed - External - Fixed
  112. ************************************************************************/
  113. #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
  114. #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
  115. #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
  116. #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
  117. #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
  118. #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
  119. /************************************************************************
  120. Memory Controller Register Offsets - Indexed - External - Fixed
  121. ************************************************************************/
  122. #define _RX_FIFO 0x000 /* Rx FIFO */
  123. #define _TX_FIFO 0x800 /* Tx FIFO */
  124. #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
  125. #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
  126. #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
  127. #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
  128. #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
  129. #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
  130. #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
  131. #define TXFIFO_SIZE 255 /* size of Tx FIFO */
  132. #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
  133. /************************************************************************
  134. Tx Priority Buffer - Indexed - External - Fixed
  135. ************************************************************************/
  136. #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
  137. #define TXP_SIZE 0x20 /* 32 bytes */
  138. /************************************************************************
  139. Channel Register Offsets - Indexed - Internal - Fixed
  140. ************************************************************************/
  141. #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
  142. #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
  143. #define _BAUD 0xFF4 /* Baud Rate 16 Write */
  144. #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
  145. #define STMBREAK 0x08 /* BREAK */
  146. #define STMFRAME 0x04 /* framing error */
  147. #define STMRCVROVR 0x02 /* receiver over run error */
  148. #define STMPARITY 0x01 /* parity error */
  149. #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
  150. #define STMBREAKH 0x800 /* BREAK */
  151. #define STMFRAMEH 0x400 /* framing error */
  152. #define STMRCVROVRH 0x200 /* receiver over run error */
  153. #define STMPARITYH 0x100 /* parity error */
  154. #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
  155. #define CTS_ACT 0x20 /* CTS input asserted */
  156. #define DSR_ACT 0x10 /* DSR input asserted */
  157. #define CD_ACT 0x08 /* CD input asserted */
  158. #define TXFIFOMT 0x04 /* Tx FIFO is empty */
  159. #define TXSHRMT 0x02 /* Tx shift register is empty */
  160. #define RDA 0x01 /* Rx data available */
  161. #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
  162. #define STATMODE 0x8000 /* status mode enable bit */
  163. #define RXFOVERFL 0x2000 /* receive FIFO overflow */
  164. #define RX2MATCH 0x1000 /* receive compare byte 2 match */
  165. #define RX1MATCH 0x0800 /* receive compare byte 1 match */
  166. #define RXBREAK 0x0400 /* received BREAK */
  167. #define RXFRAME 0x0200 /* received framing error */
  168. #define RXPARITY 0x0100 /* received parity error */
  169. #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
  170. #define CTSFC_EN 0x80 /* CTS flow control enable bit */
  171. #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
  172. #define TXINT_EN 0x10 /* transmit interrupt enable */
  173. #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
  174. #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
  175. #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
  176. #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
  177. #define SETBREAK 0x10 /* send break condition (must clear) */
  178. #define LOCALLOOP 0x08 /* local loopback set for test */
  179. #define SET_DTR 0x04 /* assert DTR */
  180. #define SET_RTS 0x02 /* assert RTS */
  181. #define TX_ENABLE 0x01 /* enable transmitter */
  182. #define RTSFC_EN 0x40 /* RTS flow control enable */
  183. #define RXPROC_EN 0x20 /* receive processor enable */
  184. #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
  185. #define TRIG_1 0x08 /* trigger level 1 char */
  186. #define TRIG_1_2 0x10 /* trigger level 1/2 */
  187. #define TRIG_7_8 0x18 /* trigger level 7/8 */
  188. #define TRIG_MASK 0x18 /* trigger level mask */
  189. #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
  190. #define RXINT_EN 0x02 /* Rx interrupt enable */
  191. #define MCINT_EN 0x01 /* modem change interrupt enable */
  192. #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
  193. #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
  194. #define SRC_INT 0x08 /* special receive condition interrupt */
  195. #define DELTA_CD 0x04 /* CD change interrupt */
  196. #define DELTA_CTS 0x02 /* CTS change interrupt */
  197. #define DELTA_DSR 0x01 /* DSR change interrupt */
  198. #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
  199. #define IGN2_EN 0x08 /* ignore byte 2 enable */
  200. #define IGN1_EN 0x04 /* ignore byte 1 enable */
  201. #define COMP2_EN 0x02 /* compare byte 2 enable */
  202. #define COMP1_EN 0x01 /* compare byte 1 enable */
  203. #define RESET_ALL 0x80 /* reset AIOP (all channels) */
  204. #define TXOVERIDE 0x40 /* Transmit software off override */
  205. #define RESETUART 0x20 /* reset channel's UART */
  206. #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
  207. #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
  208. #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
  209. #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
  210. #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
  211. #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
  212. #define INTR_EN 0x08 /* allow interrupts to host */
  213. #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
  214. /**************************************************************************
  215. MUDBAC remapped for PCI
  216. **************************************************************************/
  217. #define _CFG_INT_PCI 0x40
  218. #define _PCI_INT_FUNC 0x3A
  219. #define PCI_STROB 0x2000 /* bit 13 of int aiop register */
  220. #define INTR_EN_PCI 0x0010 /* allow interrupts to host */
  221. /*
  222. * Definitions for Universal PCI board registers
  223. */
  224. #define _PCI_9030_INT_CTRL 0x4c /* Offsets from BAR1 */
  225. #define _PCI_9030_GPIO_CTRL 0x54
  226. #define PCI_INT_CTRL_AIOP 0x0001
  227. #define PCI_GPIO_CTRL_8PORT 0x4000
  228. #define _PCI_9030_RING_IND 0xc0 /* Offsets from BAR1 */
  229. #define CHAN3_EN 0x08 /* enable AIOP 3 */
  230. #define CHAN2_EN 0x04 /* enable AIOP 2 */
  231. #define CHAN1_EN 0x02 /* enable AIOP 1 */
  232. #define CHAN0_EN 0x01 /* enable AIOP 0 */
  233. #define FREQ_DIS 0x00
  234. #define FREQ_274HZ 0x60
  235. #define FREQ_137HZ 0x50
  236. #define FREQ_69HZ 0x40
  237. #define FREQ_34HZ 0x30
  238. #define FREQ_17HZ 0x20
  239. #define FREQ_9HZ 0x10
  240. #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
  241. #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
  242. #define RDATASIZE 72
  243. #define RREGDATASIZE 52
  244. /*
  245. * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
  246. */
  247. #define AIOP_INTR_BIT_0 0x0001
  248. #define AIOP_INTR_BIT_1 0x0002
  249. #define AIOP_INTR_BIT_2 0x0004
  250. #define AIOP_INTR_BIT_3 0x0008
  251. #define AIOP_INTR_BITS ( \
  252. AIOP_INTR_BIT_0 \
  253. | AIOP_INTR_BIT_1 \
  254. | AIOP_INTR_BIT_2 \
  255. | AIOP_INTR_BIT_3)
  256. #define UPCI_AIOP_INTR_BIT_0 0x0004
  257. #define UPCI_AIOP_INTR_BIT_1 0x0020
  258. #define UPCI_AIOP_INTR_BIT_2 0x0100
  259. #define UPCI_AIOP_INTR_BIT_3 0x0800
  260. #define UPCI_AIOP_INTR_BITS ( \
  261. UPCI_AIOP_INTR_BIT_0 \
  262. | UPCI_AIOP_INTR_BIT_1 \
  263. | UPCI_AIOP_INTR_BIT_2 \
  264. | UPCI_AIOP_INTR_BIT_3)
  265. /* Controller level information structure */
  266. typedef struct {
  267. int CtlID;
  268. int CtlNum;
  269. int BusType;
  270. int boardType;
  271. int isUPCI;
  272. WordIO_t PCIIO;
  273. WordIO_t PCIIO2;
  274. ByteIO_t MBaseIO;
  275. ByteIO_t MReg1IO;
  276. ByteIO_t MReg2IO;
  277. ByteIO_t MReg3IO;
  278. Byte_t MReg2;
  279. Byte_t MReg3;
  280. int NumAiop;
  281. int AltChanRingIndicator;
  282. ByteIO_t UPCIRingInd;
  283. WordIO_t AiopIO[AIOP_CTL_SIZE];
  284. ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
  285. int AiopID[AIOP_CTL_SIZE];
  286. int AiopNumChan[AIOP_CTL_SIZE];
  287. Word_t *AiopIntrBits;
  288. } CONTROLLER_T;
  289. typedef CONTROLLER_T CONTROLLER_t;
  290. /* Channel level information structure */
  291. typedef struct {
  292. CONTROLLER_T *CtlP;
  293. int AiopNum;
  294. int ChanID;
  295. int ChanNum;
  296. int rtsToggle;
  297. ByteIO_t Cmd;
  298. ByteIO_t IntChan;
  299. ByteIO_t IntMask;
  300. DWordIO_t IndexAddr;
  301. WordIO_t IndexData;
  302. WordIO_t TxRxData;
  303. WordIO_t ChanStat;
  304. WordIO_t TxRxCount;
  305. ByteIO_t IntID;
  306. Word_t TxFIFO;
  307. Word_t TxFIFOPtrs;
  308. Word_t RxFIFO;
  309. Word_t RxFIFOPtrs;
  310. Word_t TxPrioCnt;
  311. Word_t TxPrioPtr;
  312. Word_t TxPrioBuf;
  313. Byte_t R[RREGDATASIZE];
  314. Byte_t BaudDiv[4];
  315. Byte_t TxControl[4];
  316. Byte_t RxControl[4];
  317. Byte_t TxEnables[4];
  318. Byte_t TxCompare[4];
  319. Byte_t TxReplace1[4];
  320. Byte_t TxReplace2[4];
  321. } CHANNEL_T;
  322. typedef CHANNEL_T CHANNEL_t;
  323. typedef CHANNEL_T *CHANPTR_T;
  324. #define InterfaceModeRS232 0x00
  325. #define InterfaceModeRS422 0x08
  326. #define InterfaceModeRS485 0x10
  327. #define InterfaceModeRS232T 0x18
  328. /***************************************************************************
  329. Function: sClrBreak
  330. Purpose: Stop sending a transmit BREAK signal
  331. Call: sClrBreak(ChP)
  332. CHANNEL_T *ChP; Ptr to channel structure
  333. */
  334. #define sClrBreak(ChP) \
  335. do { \
  336. (ChP)->TxControl[3] &= ~SETBREAK; \
  337. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  338. } while (0)
  339. /***************************************************************************
  340. Function: sClrDTR
  341. Purpose: Clr the DTR output
  342. Call: sClrDTR(ChP)
  343. CHANNEL_T *ChP; Ptr to channel structure
  344. */
  345. #define sClrDTR(ChP) \
  346. do { \
  347. (ChP)->TxControl[3] &= ~SET_DTR; \
  348. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  349. } while (0)
  350. /***************************************************************************
  351. Function: sClrRTS
  352. Purpose: Clr the RTS output
  353. Call: sClrRTS(ChP)
  354. CHANNEL_T *ChP; Ptr to channel structure
  355. */
  356. #define sClrRTS(ChP) \
  357. do { \
  358. if ((ChP)->rtsToggle) break; \
  359. (ChP)->TxControl[3] &= ~SET_RTS; \
  360. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  361. } while (0)
  362. /***************************************************************************
  363. Function: sClrTxXOFF
  364. Purpose: Clear any existing transmit software flow control off condition
  365. Call: sClrTxXOFF(ChP)
  366. CHANNEL_T *ChP; Ptr to channel structure
  367. */
  368. #define sClrTxXOFF(ChP) \
  369. do { \
  370. sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
  371. sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
  372. } while (0)
  373. /***************************************************************************
  374. Function: sCtlNumToCtlPtr
  375. Purpose: Convert a controller number to controller structure pointer
  376. Call: sCtlNumToCtlPtr(CtlNum)
  377. int CtlNum; Controller number
  378. Return: CONTROLLER_T *: Ptr to controller structure
  379. */
  380. #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
  381. /***************************************************************************
  382. Function: sControllerEOI
  383. Purpose: Strobe the MUDBAC's End Of Interrupt bit.
  384. Call: sControllerEOI(CtlP)
  385. CONTROLLER_T *CtlP; Ptr to controller structure
  386. */
  387. #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
  388. /***************************************************************************
  389. Function: sPCIControllerEOI
  390. Purpose: Strobe the PCI End Of Interrupt bit.
  391. For the UPCI boards, toggle the AIOP interrupt enable bit
  392. (this was taken from the Windows driver).
  393. Call: sPCIControllerEOI(CtlP)
  394. CONTROLLER_T *CtlP; Ptr to controller structure
  395. */
  396. #define sPCIControllerEOI(CTLP) \
  397. do { \
  398. if ((CTLP)->isUPCI) { \
  399. Word_t w = sInW((CTLP)->PCIIO); \
  400. sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
  401. sOutW((CTLP)->PCIIO, w); \
  402. } \
  403. else { \
  404. sOutW((CTLP)->PCIIO, PCI_STROB); \
  405. } \
  406. } while (0)
  407. /***************************************************************************
  408. Function: sDisAiop
  409. Purpose: Disable I/O access to an AIOP
  410. Call: sDisAiop(CltP)
  411. CONTROLLER_T *CtlP; Ptr to controller structure
  412. int AiopNum; Number of AIOP on controller
  413. */
  414. #define sDisAiop(CTLP,AIOPNUM) \
  415. do { \
  416. (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
  417. sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
  418. } while (0)
  419. /***************************************************************************
  420. Function: sDisCTSFlowCtl
  421. Purpose: Disable output flow control using CTS
  422. Call: sDisCTSFlowCtl(ChP)
  423. CHANNEL_T *ChP; Ptr to channel structure
  424. */
  425. #define sDisCTSFlowCtl(ChP) \
  426. do { \
  427. (ChP)->TxControl[2] &= ~CTSFC_EN; \
  428. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  429. } while (0)
  430. /***************************************************************************
  431. Function: sDisIXANY
  432. Purpose: Disable IXANY Software Flow Control
  433. Call: sDisIXANY(ChP)
  434. CHANNEL_T *ChP; Ptr to channel structure
  435. */
  436. #define sDisIXANY(ChP) \
  437. do { \
  438. (ChP)->R[0x0e] = 0x86; \
  439. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
  440. } while (0)
  441. /***************************************************************************
  442. Function: DisParity
  443. Purpose: Disable parity
  444. Call: sDisParity(ChP)
  445. CHANNEL_T *ChP; Ptr to channel structure
  446. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  447. sDisParity(), sSetOddParity(), and sSetEvenParity().
  448. */
  449. #define sDisParity(ChP) \
  450. do { \
  451. (ChP)->TxControl[2] &= ~PARITY_EN; \
  452. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  453. } while (0)
  454. /***************************************************************************
  455. Function: sDisRTSToggle
  456. Purpose: Disable RTS toggle
  457. Call: sDisRTSToggle(ChP)
  458. CHANNEL_T *ChP; Ptr to channel structure
  459. */
  460. #define sDisRTSToggle(ChP) \
  461. do { \
  462. (ChP)->TxControl[2] &= ~RTSTOG_EN; \
  463. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  464. (ChP)->rtsToggle = 0; \
  465. } while (0)
  466. /***************************************************************************
  467. Function: sDisRxFIFO
  468. Purpose: Disable Rx FIFO
  469. Call: sDisRxFIFO(ChP)
  470. CHANNEL_T *ChP; Ptr to channel structure
  471. */
  472. #define sDisRxFIFO(ChP) \
  473. do { \
  474. (ChP)->R[0x32] = 0x0a; \
  475. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
  476. } while (0)
  477. /***************************************************************************
  478. Function: sDisRxStatusMode
  479. Purpose: Disable the Rx status mode
  480. Call: sDisRxStatusMode(ChP)
  481. CHANNEL_T *ChP; Ptr to channel structure
  482. Comments: This takes the channel out of the receive status mode. All
  483. subsequent reads of receive data using sReadRxWord() will return
  484. two data bytes.
  485. */
  486. #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
  487. /***************************************************************************
  488. Function: sDisTransmit
  489. Purpose: Disable transmit
  490. Call: sDisTransmit(ChP)
  491. CHANNEL_T *ChP; Ptr to channel structure
  492. This disables movement of Tx data from the Tx FIFO into the 1 byte
  493. Tx buffer. Therefore there could be up to a 2 byte latency
  494. between the time sDisTransmit() is called and the transmit buffer
  495. and transmit shift register going completely empty.
  496. */
  497. #define sDisTransmit(ChP) \
  498. do { \
  499. (ChP)->TxControl[3] &= ~TX_ENABLE; \
  500. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  501. } while (0)
  502. /***************************************************************************
  503. Function: sDisTxSoftFlowCtl
  504. Purpose: Disable Tx Software Flow Control
  505. Call: sDisTxSoftFlowCtl(ChP)
  506. CHANNEL_T *ChP; Ptr to channel structure
  507. */
  508. #define sDisTxSoftFlowCtl(ChP) \
  509. do { \
  510. (ChP)->R[0x06] = 0x8a; \
  511. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
  512. } while (0)
  513. /***************************************************************************
  514. Function: sEnAiop
  515. Purpose: Enable I/O access to an AIOP
  516. Call: sEnAiop(CltP)
  517. CONTROLLER_T *CtlP; Ptr to controller structure
  518. int AiopNum; Number of AIOP on controller
  519. */
  520. #define sEnAiop(CTLP,AIOPNUM) \
  521. do { \
  522. (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
  523. sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
  524. } while (0)
  525. /***************************************************************************
  526. Function: sEnCTSFlowCtl
  527. Purpose: Enable output flow control using CTS
  528. Call: sEnCTSFlowCtl(ChP)
  529. CHANNEL_T *ChP; Ptr to channel structure
  530. */
  531. #define sEnCTSFlowCtl(ChP) \
  532. do { \
  533. (ChP)->TxControl[2] |= CTSFC_EN; \
  534. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  535. } while (0)
  536. /***************************************************************************
  537. Function: sEnIXANY
  538. Purpose: Enable IXANY Software Flow Control
  539. Call: sEnIXANY(ChP)
  540. CHANNEL_T *ChP; Ptr to channel structure
  541. */
  542. #define sEnIXANY(ChP) \
  543. do { \
  544. (ChP)->R[0x0e] = 0x21; \
  545. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
  546. } while (0)
  547. /***************************************************************************
  548. Function: EnParity
  549. Purpose: Enable parity
  550. Call: sEnParity(ChP)
  551. CHANNEL_T *ChP; Ptr to channel structure
  552. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  553. sDisParity(), sSetOddParity(), and sSetEvenParity().
  554. Warnings: Before enabling parity odd or even parity should be chosen using
  555. functions sSetOddParity() or sSetEvenParity().
  556. */
  557. #define sEnParity(ChP) \
  558. do { \
  559. (ChP)->TxControl[2] |= PARITY_EN; \
  560. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  561. } while (0)
  562. /***************************************************************************
  563. Function: sEnRTSToggle
  564. Purpose: Enable RTS toggle
  565. Call: sEnRTSToggle(ChP)
  566. CHANNEL_T *ChP; Ptr to channel structure
  567. Comments: This function will disable RTS flow control and clear the RTS
  568. line to allow operation of RTS toggle.
  569. */
  570. #define sEnRTSToggle(ChP) \
  571. do { \
  572. (ChP)->RxControl[2] &= ~RTSFC_EN; \
  573. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
  574. (ChP)->TxControl[2] |= RTSTOG_EN; \
  575. (ChP)->TxControl[3] &= ~SET_RTS; \
  576. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  577. (ChP)->rtsToggle = 1; \
  578. } while (0)
  579. /***************************************************************************
  580. Function: sEnRxFIFO
  581. Purpose: Enable Rx FIFO
  582. Call: sEnRxFIFO(ChP)
  583. CHANNEL_T *ChP; Ptr to channel structure
  584. */
  585. #define sEnRxFIFO(ChP) \
  586. do { \
  587. (ChP)->R[0x32] = 0x08; \
  588. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
  589. } while (0)
  590. /***************************************************************************
  591. Function: sEnRxProcessor
  592. Purpose: Enable the receive processor
  593. Call: sEnRxProcessor(ChP)
  594. CHANNEL_T *ChP; Ptr to channel structure
  595. Comments: This function is used to start the receive processor. When
  596. the channel is in the reset state the receive processor is not
  597. running. This is done to prevent the receive processor from
  598. executing invalid microcode instructions prior to the
  599. downloading of the microcode.
  600. Warnings: This function must be called after valid microcode has been
  601. downloaded to the AIOP, and it must not be called before the
  602. microcode has been downloaded.
  603. */
  604. #define sEnRxProcessor(ChP) \
  605. do { \
  606. (ChP)->RxControl[2] |= RXPROC_EN; \
  607. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
  608. } while (0)
  609. /***************************************************************************
  610. Function: sEnRxStatusMode
  611. Purpose: Enable the Rx status mode
  612. Call: sEnRxStatusMode(ChP)
  613. CHANNEL_T *ChP; Ptr to channel structure
  614. Comments: This places the channel in the receive status mode. All subsequent
  615. reads of receive data using sReadRxWord() will return a data byte
  616. in the low word and a status byte in the high word.
  617. */
  618. #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
  619. /***************************************************************************
  620. Function: sEnTransmit
  621. Purpose: Enable transmit
  622. Call: sEnTransmit(ChP)
  623. CHANNEL_T *ChP; Ptr to channel structure
  624. */
  625. #define sEnTransmit(ChP) \
  626. do { \
  627. (ChP)->TxControl[3] |= TX_ENABLE; \
  628. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  629. } while (0)
  630. /***************************************************************************
  631. Function: sEnTxSoftFlowCtl
  632. Purpose: Enable Tx Software Flow Control
  633. Call: sEnTxSoftFlowCtl(ChP)
  634. CHANNEL_T *ChP; Ptr to channel structure
  635. */
  636. #define sEnTxSoftFlowCtl(ChP) \
  637. do { \
  638. (ChP)->R[0x06] = 0xc5; \
  639. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
  640. } while (0)
  641. /***************************************************************************
  642. Function: sGetAiopIntStatus
  643. Purpose: Get the AIOP interrupt status
  644. Call: sGetAiopIntStatus(CtlP,AiopNum)
  645. CONTROLLER_T *CtlP; Ptr to controller structure
  646. int AiopNum; AIOP number
  647. Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
  648. represent channels 0 through 7 respectively. If a
  649. bit is set that channel is interrupting.
  650. */
  651. #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
  652. /***************************************************************************
  653. Function: sGetAiopNumChan
  654. Purpose: Get the number of channels supported by an AIOP
  655. Call: sGetAiopNumChan(CtlP,AiopNum)
  656. CONTROLLER_T *CtlP; Ptr to controller structure
  657. int AiopNum; AIOP number
  658. Return: int: The number of channels supported by the AIOP
  659. */
  660. #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
  661. /***************************************************************************
  662. Function: sGetChanIntID
  663. Purpose: Get a channel's interrupt identification byte
  664. Call: sGetChanIntID(ChP)
  665. CHANNEL_T *ChP; Ptr to channel structure
  666. Return: Byte_t: The channel interrupt ID. Can be any
  667. combination of the following flags:
  668. RXF_TRIG: Rx FIFO trigger level interrupt
  669. TXFIFO_MT: Tx FIFO empty interrupt
  670. SRC_INT: Special receive condition interrupt
  671. DELTA_CD: CD change interrupt
  672. DELTA_CTS: CTS change interrupt
  673. DELTA_DSR: DSR change interrupt
  674. */
  675. #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
  676. /***************************************************************************
  677. Function: sGetChanNum
  678. Purpose: Get the number of a channel within an AIOP
  679. Call: sGetChanNum(ChP)
  680. CHANNEL_T *ChP; Ptr to channel structure
  681. Return: int: Channel number within AIOP, or NULLCHAN if channel does
  682. not exist.
  683. */
  684. #define sGetChanNum(ChP) (ChP)->ChanNum
  685. /***************************************************************************
  686. Function: sGetChanStatus
  687. Purpose: Get the channel status
  688. Call: sGetChanStatus(ChP)
  689. CHANNEL_T *ChP; Ptr to channel structure
  690. Return: Word_t: The channel status. Can be any combination of
  691. the following flags:
  692. LOW BYTE FLAGS
  693. CTS_ACT: CTS input asserted
  694. DSR_ACT: DSR input asserted
  695. CD_ACT: CD input asserted
  696. TXFIFOMT: Tx FIFO is empty
  697. TXSHRMT: Tx shift register is empty
  698. RDA: Rx data available
  699. HIGH BYTE FLAGS
  700. STATMODE: status mode enable bit
  701. RXFOVERFL: receive FIFO overflow
  702. RX2MATCH: receive compare byte 2 match
  703. RX1MATCH: receive compare byte 1 match
  704. RXBREAK: received BREAK
  705. RXFRAME: received framing error
  706. RXPARITY: received parity error
  707. Warnings: This function will clear the high byte flags in the Channel
  708. Status Register.
  709. */
  710. #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
  711. /***************************************************************************
  712. Function: sGetChanStatusLo
  713. Purpose: Get the low byte only of the channel status
  714. Call: sGetChanStatusLo(ChP)
  715. CHANNEL_T *ChP; Ptr to channel structure
  716. Return: Byte_t: The channel status low byte. Can be any combination
  717. of the following flags:
  718. CTS_ACT: CTS input asserted
  719. DSR_ACT: DSR input asserted
  720. CD_ACT: CD input asserted
  721. TXFIFOMT: Tx FIFO is empty
  722. TXSHRMT: Tx shift register is empty
  723. RDA: Rx data available
  724. */
  725. #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
  726. /**********************************************************************
  727. * Get RI status of channel
  728. * Defined as a function in rocket.c -aes
  729. */
  730. #if 0
  731. #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
  732. (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
  733. (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
  734. (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
  735. 0))
  736. #endif
  737. /***************************************************************************
  738. Function: sGetControllerIntStatus
  739. Purpose: Get the controller interrupt status
  740. Call: sGetControllerIntStatus(CtlP)
  741. CONTROLLER_T *CtlP; Ptr to controller structure
  742. Return: Byte_t: The controller interrupt status in the lower 4
  743. bits. Bits 0 through 3 represent AIOP's 0
  744. through 3 respectively. If a bit is set that
  745. AIOP is interrupting. Bits 4 through 7 will
  746. always be cleared.
  747. */
  748. #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
  749. /***************************************************************************
  750. Function: sPCIGetControllerIntStatus
  751. Purpose: Get the controller interrupt status
  752. Call: sPCIGetControllerIntStatus(CtlP)
  753. CONTROLLER_T *CtlP; Ptr to controller structure
  754. Return: unsigned char: The controller interrupt status in the lower 4
  755. bits and bit 4. Bits 0 through 3 represent AIOP's 0
  756. through 3 respectively. Bit 4 is set if the int
  757. was generated from periodic. If a bit is set the
  758. AIOP is interrupting.
  759. */
  760. #define sPCIGetControllerIntStatus(CTLP) \
  761. ((CTLP)->isUPCI ? \
  762. (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
  763. ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
  764. /***************************************************************************
  765. Function: sGetRxCnt
  766. Purpose: Get the number of data bytes in the Rx FIFO
  767. Call: sGetRxCnt(ChP)
  768. CHANNEL_T *ChP; Ptr to channel structure
  769. Return: int: The number of data bytes in the Rx FIFO.
  770. Comments: Byte read of count register is required to obtain Rx count.
  771. */
  772. #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
  773. /***************************************************************************
  774. Function: sGetTxCnt
  775. Purpose: Get the number of data bytes in the Tx FIFO
  776. Call: sGetTxCnt(ChP)
  777. CHANNEL_T *ChP; Ptr to channel structure
  778. Return: Byte_t: The number of data bytes in the Tx FIFO.
  779. Comments: Byte read of count register is required to obtain Tx count.
  780. */
  781. #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
  782. /*****************************************************************************
  783. Function: sGetTxRxDataIO
  784. Purpose: Get the I/O address of a channel's TxRx Data register
  785. Call: sGetTxRxDataIO(ChP)
  786. CHANNEL_T *ChP; Ptr to channel structure
  787. Return: WordIO_t: I/O address of a channel's TxRx Data register
  788. */
  789. #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
  790. /***************************************************************************
  791. Function: sInitChanDefaults
  792. Purpose: Initialize a channel structure to it's default state.
  793. Call: sInitChanDefaults(ChP)
  794. CHANNEL_T *ChP; Ptr to the channel structure
  795. Comments: This function must be called once for every channel structure
  796. that exists before any other SSCI calls can be made.
  797. */
  798. #define sInitChanDefaults(ChP) \
  799. do { \
  800. (ChP)->CtlP = NULLCTLPTR; \
  801. (ChP)->AiopNum = NULLAIOP; \
  802. (ChP)->ChanID = AIOPID_NULL; \
  803. (ChP)->ChanNum = NULLCHAN; \
  804. } while (0)
  805. /***************************************************************************
  806. Function: sResetAiopByNum
  807. Purpose: Reset the AIOP by number
  808. Call: sResetAiopByNum(CTLP,AIOPNUM)
  809. CONTROLLER_T CTLP; Ptr to controller structure
  810. AIOPNUM; AIOP index
  811. */
  812. #define sResetAiopByNum(CTLP,AIOPNUM) \
  813. do { \
  814. sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
  815. sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
  816. } while (0)
  817. /***************************************************************************
  818. Function: sSendBreak
  819. Purpose: Send a transmit BREAK signal
  820. Call: sSendBreak(ChP)
  821. CHANNEL_T *ChP; Ptr to channel structure
  822. */
  823. #define sSendBreak(ChP) \
  824. do { \
  825. (ChP)->TxControl[3] |= SETBREAK; \
  826. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  827. } while (0)
  828. /***************************************************************************
  829. Function: sSetBaud
  830. Purpose: Set baud rate
  831. Call: sSetBaud(ChP,Divisor)
  832. CHANNEL_T *ChP; Ptr to channel structure
  833. Word_t Divisor; 16 bit baud rate divisor for channel
  834. */
  835. #define sSetBaud(ChP,DIVISOR) \
  836. do { \
  837. (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
  838. (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
  839. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
  840. } while (0)
  841. /***************************************************************************
  842. Function: sSetData7
  843. Purpose: Set data bits to 7
  844. Call: sSetData7(ChP)
  845. CHANNEL_T *ChP; Ptr to channel structure
  846. */
  847. #define sSetData7(ChP) \
  848. do { \
  849. (ChP)->TxControl[2] &= ~DATA8BIT; \
  850. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  851. } while (0)
  852. /***************************************************************************
  853. Function: sSetData8
  854. Purpose: Set data bits to 8
  855. Call: sSetData8(ChP)
  856. CHANNEL_T *ChP; Ptr to channel structure
  857. */
  858. #define sSetData8(ChP) \
  859. do { \
  860. (ChP)->TxControl[2] |= DATA8BIT; \
  861. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  862. } while (0)
  863. /***************************************************************************
  864. Function: sSetDTR
  865. Purpose: Set the DTR output
  866. Call: sSetDTR(ChP)
  867. CHANNEL_T *ChP; Ptr to channel structure
  868. */
  869. #define sSetDTR(ChP) \
  870. do { \
  871. (ChP)->TxControl[3] |= SET_DTR; \
  872. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  873. } while (0)
  874. /***************************************************************************
  875. Function: sSetEvenParity
  876. Purpose: Set even parity
  877. Call: sSetEvenParity(ChP)
  878. CHANNEL_T *ChP; Ptr to channel structure
  879. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  880. sDisParity(), sSetOddParity(), and sSetEvenParity().
  881. Warnings: This function has no effect unless parity is enabled with function
  882. sEnParity().
  883. */
  884. #define sSetEvenParity(ChP) \
  885. do { \
  886. (ChP)->TxControl[2] |= EVEN_PAR; \
  887. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  888. } while (0)
  889. /***************************************************************************
  890. Function: sSetOddParity
  891. Purpose: Set odd parity
  892. Call: sSetOddParity(ChP)
  893. CHANNEL_T *ChP; Ptr to channel structure
  894. Comments: Function sSetParity() can be used in place of functions sEnParity(),
  895. sDisParity(), sSetOddParity(), and sSetEvenParity().
  896. Warnings: This function has no effect unless parity is enabled with function
  897. sEnParity().
  898. */
  899. #define sSetOddParity(ChP) \
  900. do { \
  901. (ChP)->TxControl[2] &= ~EVEN_PAR; \
  902. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  903. } while (0)
  904. /***************************************************************************
  905. Function: sSetRTS
  906. Purpose: Set the RTS output
  907. Call: sSetRTS(ChP)
  908. CHANNEL_T *ChP; Ptr to channel structure
  909. */
  910. #define sSetRTS(ChP) \
  911. do { \
  912. if ((ChP)->rtsToggle) break; \
  913. (ChP)->TxControl[3] |= SET_RTS; \
  914. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  915. } while (0)
  916. /***************************************************************************
  917. Function: sSetRxTrigger
  918. Purpose: Set the Rx FIFO trigger level
  919. Call: sSetRxProcessor(ChP,Level)
  920. CHANNEL_T *ChP; Ptr to channel structure
  921. Byte_t Level; Number of characters in Rx FIFO at which the
  922. interrupt will be generated. Can be any of the following flags:
  923. TRIG_NO: no trigger
  924. TRIG_1: 1 character in FIFO
  925. TRIG_1_2: FIFO 1/2 full
  926. TRIG_7_8: FIFO 7/8 full
  927. Comments: An interrupt will be generated when the trigger level is reached
  928. only if function sEnInterrupt() has been called with flag
  929. RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
  930. register will be set whenever the trigger level is reached
  931. regardless of the setting of RXINT_EN.
  932. */
  933. #define sSetRxTrigger(ChP,LEVEL) \
  934. do { \
  935. (ChP)->RxControl[2] &= ~TRIG_MASK; \
  936. (ChP)->RxControl[2] |= LEVEL; \
  937. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
  938. } while (0)
  939. /***************************************************************************
  940. Function: sSetStop1
  941. Purpose: Set stop bits to 1
  942. Call: sSetStop1(ChP)
  943. CHANNEL_T *ChP; Ptr to channel structure
  944. */
  945. #define sSetStop1(ChP) \
  946. do { \
  947. (ChP)->TxControl[2] &= ~STOP2; \
  948. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  949. } while (0)
  950. /***************************************************************************
  951. Function: sSetStop2
  952. Purpose: Set stop bits to 2
  953. Call: sSetStop2(ChP)
  954. CHANNEL_T *ChP; Ptr to channel structure
  955. */
  956. #define sSetStop2(ChP) \
  957. do { \
  958. (ChP)->TxControl[2] |= STOP2; \
  959. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
  960. } while (0)
  961. /***************************************************************************
  962. Function: sSetTxXOFFChar
  963. Purpose: Set the Tx XOFF flow control character
  964. Call: sSetTxXOFFChar(ChP,Ch)
  965. CHANNEL_T *ChP; Ptr to channel structure
  966. Byte_t Ch; The value to set the Tx XOFF character to
  967. */
  968. #define sSetTxXOFFChar(ChP,CH) \
  969. do { \
  970. (ChP)->R[0x07] = (CH); \
  971. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
  972. } while (0)
  973. /***************************************************************************
  974. Function: sSetTxXONChar
  975. Purpose: Set the Tx XON flow control character
  976. Call: sSetTxXONChar(ChP,Ch)
  977. CHANNEL_T *ChP; Ptr to channel structure
  978. Byte_t Ch; The value to set the Tx XON character to
  979. */
  980. #define sSetTxXONChar(ChP,CH) \
  981. do { \
  982. (ChP)->R[0x0b] = (CH); \
  983. sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
  984. } while (0)
  985. /***************************************************************************
  986. Function: sStartRxProcessor
  987. Purpose: Start a channel's receive processor
  988. Call: sStartRxProcessor(ChP)
  989. CHANNEL_T *ChP; Ptr to channel structure
  990. Comments: This function is used to start a Rx processor after it was
  991. stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
  992. will restart both the Rx processor and software input flow control.
  993. */
  994. #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
  995. /***************************************************************************
  996. Function: sWriteTxByte
  997. Purpose: Write a transmit data byte to a channel.
  998. ByteIO_t io: Channel transmit register I/O address. This can
  999. be obtained with sGetTxRxDataIO().
  1000. Byte_t Data; The transmit data byte.
  1001. Warnings: This function writes the data byte without checking to see if
  1002. sMaxTxSize is exceeded in the Tx FIFO.
  1003. */
  1004. #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
  1005. /*
  1006. * Begin Linux specific definitions for the Rocketport driver
  1007. *
  1008. * This code is Copyright Theodore Ts'o, 1995-1997
  1009. */
  1010. struct r_port {
  1011. int magic;
  1012. int line;
  1013. int flags;
  1014. int count;
  1015. int blocked_open;
  1016. struct tty_struct *tty;
  1017. unsigned int board:3;
  1018. unsigned int aiop:2;
  1019. unsigned int chan:3;
  1020. CONTROLLER_t *ctlp;
  1021. CHANNEL_t channel;
  1022. int closing_wait;
  1023. int close_delay;
  1024. int intmask;
  1025. int xmit_fifo_room; /* room in xmit fifo */
  1026. unsigned char *xmit_buf;
  1027. int xmit_head;
  1028. int xmit_tail;
  1029. int xmit_cnt;
  1030. int session;
  1031. int pgrp;
  1032. int cd_status;
  1033. int ignore_status_mask;
  1034. int read_status_mask;
  1035. int cps;
  1036. #ifdef DECLARE_WAITQUEUE
  1037. wait_queue_head_t open_wait;
  1038. wait_queue_head_t close_wait;
  1039. #else
  1040. struct wait_queue *open_wait;
  1041. struct wait_queue *close_wait;
  1042. #endif
  1043. spinlock_t slock;
  1044. struct semaphore write_sem;
  1045. };
  1046. #define RPORT_MAGIC 0x525001
  1047. #define NUM_BOARDS 8
  1048. #define MAX_RP_PORTS (32*NUM_BOARDS)
  1049. /*
  1050. * The size of the xmit buffer is 1 page, or 4096 bytes
  1051. */
  1052. #define XMIT_BUF_SIZE 4096
  1053. /* number of characters left in xmit buffer before we ask for more */
  1054. #define WAKEUP_CHARS 256
  1055. /* Internal flags used only by the rocketport driver */
  1056. #define ROCKET_INITIALIZED 0x80000000 /* Port is active */
  1057. #define ROCKET_CLOSING 0x40000000 /* Serial port is closing */
  1058. #define ROCKET_NORMAL_ACTIVE 0x20000000 /* Normal port is active */
  1059. /* tty subtypes */
  1060. #define SERIAL_TYPE_NORMAL 1
  1061. /*
  1062. * Assigned major numbers for the Comtrol Rocketport
  1063. */
  1064. #define TTY_ROCKET_MAJOR 46
  1065. #define CUA_ROCKET_MAJOR 47
  1066. #ifdef PCI_VENDOR_ID_RP
  1067. #undef PCI_VENDOR_ID_RP
  1068. #undef PCI_DEVICE_ID_RP8OCTA
  1069. #undef PCI_DEVICE_ID_RP8INTF
  1070. #undef PCI_DEVICE_ID_RP16INTF
  1071. #undef PCI_DEVICE_ID_RP32INTF
  1072. #undef PCI_DEVICE_ID_URP8OCTA
  1073. #undef PCI_DEVICE_ID_URP8INTF
  1074. #undef PCI_DEVICE_ID_URP16INTF
  1075. #undef PCI_DEVICE_ID_CRP16INTF
  1076. #undef PCI_DEVICE_ID_URP32INTF
  1077. #endif
  1078. /* Comtrol PCI Vendor ID */
  1079. #define PCI_VENDOR_ID_RP 0x11fe
  1080. /* Comtrol Device ID's */
  1081. #define PCI_DEVICE_ID_RP32INTF 0x0001 /* Rocketport 32 port w/external I/F */
  1082. #define PCI_DEVICE_ID_RP8INTF 0x0002 /* Rocketport 8 port w/external I/F */
  1083. #define PCI_DEVICE_ID_RP16INTF 0x0003 /* Rocketport 16 port w/external I/F */
  1084. #define PCI_DEVICE_ID_RP4QUAD 0x0004 /* Rocketport 4 port w/quad cable */
  1085. #define PCI_DEVICE_ID_RP8OCTA 0x0005 /* Rocketport 8 port w/octa cable */
  1086. #define PCI_DEVICE_ID_RP8J 0x0006 /* Rocketport 8 port w/RJ11 connectors */
  1087. #define PCI_DEVICE_ID_RP4J 0x0007 /* Rocketport 4 port w/RJ11 connectors */
  1088. #define PCI_DEVICE_ID_RP8SNI 0x0008 /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
  1089. #define PCI_DEVICE_ID_RP16SNI 0x0009 /* Rocketport 16 port w/ DB78 SNI (Siemens) connector */
  1090. #define PCI_DEVICE_ID_RPP4 0x000A /* Rocketport Plus 4 port */
  1091. #define PCI_DEVICE_ID_RPP8 0x000B /* Rocketport Plus 8 port */
  1092. #define PCI_DEVICE_ID_RP6M 0x000C /* RocketModem 6 port */
  1093. #define PCI_DEVICE_ID_RP4M 0x000D /* RocketModem 4 port */
  1094. #define PCI_DEVICE_ID_RP2_232 0x000E /* Rocketport Plus 2 port RS232 */
  1095. #define PCI_DEVICE_ID_RP2_422 0x000F /* Rocketport Plus 2 port RS422 */
  1096. /* Universal PCI boards */
  1097. #define PCI_DEVICE_ID_URP32INTF 0x0801 /* Rocketport UPCI 32 port w/external I/F */
  1098. #define PCI_DEVICE_ID_URP8INTF 0x0802 /* Rocketport UPCI 8 port w/external I/F */
  1099. #define PCI_DEVICE_ID_URP16INTF 0x0803 /* Rocketport UPCI 16 port w/external I/F */
  1100. #define PCI_DEVICE_ID_URP8OCTA 0x0805 /* Rocketport UPCI 8 port w/octa cable */
  1101. #define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C /* Rocketmodem III 8 port */
  1102. #define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D /* Rocketmodem III 4 port */
  1103. /* Compact PCI device */
  1104. #define PCI_DEVICE_ID_CRP16INTF 0x0903 /* Rocketport Compact PCI 16 port w/external I/F */
  1105. #define TTY_GET_LINE(t) t->index
  1106. #define TTY_DRIVER_MINOR_START(t) t->driver->minor_start
  1107. #define TTY_DRIVER_SUBTYPE(t) t->driver->subtype
  1108. #define TTY_DRIVER_NAME(t) t->driver->name
  1109. #define TTY_DRIVER_NAME_BASE(t) t->driver->name_base
  1110. #define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer
  1111. #define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t)