rocket.c 97 KB

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  1. /*
  2. * RocketPort device driver for Linux
  3. *
  4. * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
  5. *
  6. * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of the
  11. * License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. /*
  23. * Kernel Synchronization:
  24. *
  25. * This driver has 2 kernel control paths - exception handlers (calls into the driver
  26. * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
  27. * are not used.
  28. *
  29. * Critical data:
  30. * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
  31. * serial port state information and the xmit_buf circular buffer. Protected by
  32. * a per port spinlock.
  33. * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  34. * is data to be transmitted. Protected by atomic bit operations.
  35. * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
  36. *
  37. * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  38. * simultaneous access to the same port by more than one process.
  39. */
  40. /****** Defines ******/
  41. #ifdef PCI_NUM_RESOURCES
  42. #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
  43. #else
  44. #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
  45. #endif
  46. #define ROCKET_PARANOIA_CHECK
  47. #define ROCKET_DISABLE_SIMUSAGE
  48. #undef ROCKET_SOFT_FLOW
  49. #undef ROCKET_DEBUG_OPEN
  50. #undef ROCKET_DEBUG_INTR
  51. #undef ROCKET_DEBUG_WRITE
  52. #undef ROCKET_DEBUG_FLOW
  53. #undef ROCKET_DEBUG_THROTTLE
  54. #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  55. #undef ROCKET_DEBUG_RECEIVE
  56. #undef ROCKET_DEBUG_HANGUP
  57. #undef REV_PCI_ORDER
  58. #undef ROCKET_DEBUG_IO
  59. #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
  60. /****** Kernel includes ******/
  61. #ifdef MODVERSIONS
  62. #include <config/modversions.h>
  63. #endif
  64. #include <linux/module.h>
  65. #include <linux/errno.h>
  66. #include <linux/major.h>
  67. #include <linux/kernel.h>
  68. #include <linux/signal.h>
  69. #include <linux/slab.h>
  70. #include <linux/mm.h>
  71. #include <linux/sched.h>
  72. #include <linux/timer.h>
  73. #include <linux/interrupt.h>
  74. #include <linux/tty.h>
  75. #include <linux/tty_driver.h>
  76. #include <linux/tty_flip.h>
  77. #include <linux/string.h>
  78. #include <linux/fcntl.h>
  79. #include <linux/ptrace.h>
  80. #include <linux/ioport.h>
  81. #include <linux/delay.h>
  82. #include <linux/wait.h>
  83. #include <linux/pci.h>
  84. #include <asm/uaccess.h>
  85. #include <asm/atomic.h>
  86. #include <linux/bitops.h>
  87. #include <linux/spinlock.h>
  88. #include <asm/semaphore.h>
  89. #include <linux/init.h>
  90. /****** RocketPort includes ******/
  91. #include "rocket_int.h"
  92. #include "rocket.h"
  93. #define ROCKET_VERSION "2.09"
  94. #define ROCKET_DATE "12-June-2003"
  95. /****** RocketPort Local Variables ******/
  96. static void rp_do_poll(unsigned long dummy);
  97. static struct tty_driver *rocket_driver;
  98. static struct rocket_version driver_version = {
  99. ROCKET_VERSION, ROCKET_DATE
  100. };
  101. static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
  102. static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
  103. /* eg. Bit 0 indicates port 0 has xmit data, ... */
  104. static atomic_t rp_num_ports_open; /* Number of serial ports open */
  105. static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
  106. static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
  107. static unsigned long board2;
  108. static unsigned long board3;
  109. static unsigned long board4;
  110. static unsigned long controller;
  111. static int support_low_speed;
  112. static unsigned long modem1;
  113. static unsigned long modem2;
  114. static unsigned long modem3;
  115. static unsigned long modem4;
  116. static unsigned long pc104_1[8];
  117. static unsigned long pc104_2[8];
  118. static unsigned long pc104_3[8];
  119. static unsigned long pc104_4[8];
  120. static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
  121. static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
  122. static unsigned long rcktpt_io_addr[NUM_BOARDS];
  123. static int rcktpt_type[NUM_BOARDS];
  124. static int is_PCI[NUM_BOARDS];
  125. static rocketModel_t rocketModel[NUM_BOARDS];
  126. static int max_board;
  127. /*
  128. * The following arrays define the interrupt bits corresponding to each AIOP.
  129. * These bits are different between the ISA and regular PCI boards and the
  130. * Universal PCI boards.
  131. */
  132. static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
  133. AIOP_INTR_BIT_0,
  134. AIOP_INTR_BIT_1,
  135. AIOP_INTR_BIT_2,
  136. AIOP_INTR_BIT_3
  137. };
  138. static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
  139. UPCI_AIOP_INTR_BIT_0,
  140. UPCI_AIOP_INTR_BIT_1,
  141. UPCI_AIOP_INTR_BIT_2,
  142. UPCI_AIOP_INTR_BIT_3
  143. };
  144. static Byte_t RData[RDATASIZE] = {
  145. 0x00, 0x09, 0xf6, 0x82,
  146. 0x02, 0x09, 0x86, 0xfb,
  147. 0x04, 0x09, 0x00, 0x0a,
  148. 0x06, 0x09, 0x01, 0x0a,
  149. 0x08, 0x09, 0x8a, 0x13,
  150. 0x0a, 0x09, 0xc5, 0x11,
  151. 0x0c, 0x09, 0x86, 0x85,
  152. 0x0e, 0x09, 0x20, 0x0a,
  153. 0x10, 0x09, 0x21, 0x0a,
  154. 0x12, 0x09, 0x41, 0xff,
  155. 0x14, 0x09, 0x82, 0x00,
  156. 0x16, 0x09, 0x82, 0x7b,
  157. 0x18, 0x09, 0x8a, 0x7d,
  158. 0x1a, 0x09, 0x88, 0x81,
  159. 0x1c, 0x09, 0x86, 0x7a,
  160. 0x1e, 0x09, 0x84, 0x81,
  161. 0x20, 0x09, 0x82, 0x7c,
  162. 0x22, 0x09, 0x0a, 0x0a
  163. };
  164. static Byte_t RRegData[RREGDATASIZE] = {
  165. 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
  166. 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
  167. 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
  168. 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
  169. 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
  170. 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
  171. 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
  172. 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
  173. 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
  174. 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
  175. 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
  176. 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
  177. 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
  178. };
  179. static CONTROLLER_T sController[CTL_SIZE] = {
  180. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  181. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  182. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  183. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  184. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  185. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
  186. {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
  187. {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
  188. };
  189. static Byte_t sBitMapClrTbl[8] = {
  190. 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
  191. };
  192. static Byte_t sBitMapSetTbl[8] = {
  193. 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
  194. };
  195. static int sClockPrescale = 0x14;
  196. /*
  197. * Line number is the ttySIx number (x), the Minor number. We
  198. * assign them sequentially, starting at zero. The following
  199. * array keeps track of the line number assigned to a given board/aiop/channel.
  200. */
  201. static unsigned char lineNumbers[MAX_RP_PORTS];
  202. static unsigned long nextLineNumber;
  203. /***** RocketPort Static Prototypes *********/
  204. static int __init init_ISA(int i);
  205. static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
  206. static void rp_flush_buffer(struct tty_struct *tty);
  207. static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
  208. static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
  209. static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
  210. static void rp_start(struct tty_struct *tty);
  211. static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
  212. int ChanNum);
  213. static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
  214. static void sFlushRxFIFO(CHANNEL_T * ChP);
  215. static void sFlushTxFIFO(CHANNEL_T * ChP);
  216. static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
  217. static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
  218. static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
  219. static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
  220. static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
  221. static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
  222. ByteIO_t * AiopIOList, int AiopIOListSize,
  223. WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
  224. int PeriodicOnly, int altChanRingIndicator,
  225. int UPCIRingInd);
  226. static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
  227. ByteIO_t * AiopIOList, int AiopIOListSize,
  228. int IRQNum, Byte_t Frequency, int PeriodicOnly);
  229. static int sReadAiopID(ByteIO_t io);
  230. static int sReadAiopNumChan(WordIO_t io);
  231. MODULE_AUTHOR("Theodore Ts'o");
  232. MODULE_DESCRIPTION("Comtrol RocketPort driver");
  233. module_param(board1, ulong, 0);
  234. MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
  235. module_param(board2, ulong, 0);
  236. MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
  237. module_param(board3, ulong, 0);
  238. MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
  239. module_param(board4, ulong, 0);
  240. MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
  241. module_param(controller, ulong, 0);
  242. MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
  243. module_param(support_low_speed, bool, 0);
  244. MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
  245. module_param(modem1, ulong, 0);
  246. MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
  247. module_param(modem2, ulong, 0);
  248. MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
  249. module_param(modem3, ulong, 0);
  250. MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
  251. module_param(modem4, ulong, 0);
  252. MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
  253. module_param_array(pc104_1, ulong, NULL, 0);
  254. MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
  255. module_param_array(pc104_2, ulong, NULL, 0);
  256. MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
  257. module_param_array(pc104_3, ulong, NULL, 0);
  258. MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
  259. module_param_array(pc104_4, ulong, NULL, 0);
  260. MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
  261. static int rp_init(void);
  262. static void rp_cleanup_module(void);
  263. module_init(rp_init);
  264. module_exit(rp_cleanup_module);
  265. MODULE_LICENSE("Dual BSD/GPL");
  266. /*************************************************************************/
  267. /* Module code starts here */
  268. static inline int rocket_paranoia_check(struct r_port *info,
  269. const char *routine)
  270. {
  271. #ifdef ROCKET_PARANOIA_CHECK
  272. if (!info)
  273. return 1;
  274. if (info->magic != RPORT_MAGIC) {
  275. printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
  276. routine);
  277. return 1;
  278. }
  279. #endif
  280. return 0;
  281. }
  282. /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
  283. * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
  284. * tty layer.
  285. */
  286. static void rp_do_receive(struct r_port *info,
  287. struct tty_struct *tty,
  288. CHANNEL_t * cp, unsigned int ChanStatus)
  289. {
  290. unsigned int CharNStat;
  291. int ToRecv, wRecv, space;
  292. unsigned char *cbuf;
  293. ToRecv = sGetRxCnt(cp);
  294. #ifdef ROCKET_DEBUG_INTR
  295. printk(KERN_INFO "rp_do_receive(%d)...", ToRecv);
  296. #endif
  297. if (ToRecv == 0)
  298. return;
  299. /*
  300. * if status indicates there are errored characters in the
  301. * FIFO, then enter status mode (a word in FIFO holds
  302. * character and status).
  303. */
  304. if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
  305. if (!(ChanStatus & STATMODE)) {
  306. #ifdef ROCKET_DEBUG_RECEIVE
  307. printk(KERN_INFO "Entering STATMODE...");
  308. #endif
  309. ChanStatus |= STATMODE;
  310. sEnRxStatusMode(cp);
  311. }
  312. }
  313. /*
  314. * if we previously entered status mode, then read down the
  315. * FIFO one word at a time, pulling apart the character and
  316. * the status. Update error counters depending on status
  317. */
  318. if (ChanStatus & STATMODE) {
  319. #ifdef ROCKET_DEBUG_RECEIVE
  320. printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
  321. info->read_status_mask);
  322. #endif
  323. while (ToRecv) {
  324. char flag;
  325. CharNStat = sInW(sGetTxRxDataIO(cp));
  326. #ifdef ROCKET_DEBUG_RECEIVE
  327. printk(KERN_INFO "%x...", CharNStat);
  328. #endif
  329. if (CharNStat & STMBREAKH)
  330. CharNStat &= ~(STMFRAMEH | STMPARITYH);
  331. if (CharNStat & info->ignore_status_mask) {
  332. ToRecv--;
  333. continue;
  334. }
  335. CharNStat &= info->read_status_mask;
  336. if (CharNStat & STMBREAKH)
  337. flag = TTY_BREAK;
  338. else if (CharNStat & STMPARITYH)
  339. flag = TTY_PARITY;
  340. else if (CharNStat & STMFRAMEH)
  341. flag = TTY_FRAME;
  342. else if (CharNStat & STMRCVROVRH)
  343. flag = TTY_OVERRUN;
  344. else
  345. flag = TTY_NORMAL;
  346. tty_insert_flip_char(tty, CharNStat & 0xff, flag);
  347. ToRecv--;
  348. }
  349. /*
  350. * after we've emptied the FIFO in status mode, turn
  351. * status mode back off
  352. */
  353. if (sGetRxCnt(cp) == 0) {
  354. #ifdef ROCKET_DEBUG_RECEIVE
  355. printk(KERN_INFO "Status mode off.\n");
  356. #endif
  357. sDisRxStatusMode(cp);
  358. }
  359. } else {
  360. /*
  361. * we aren't in status mode, so read down the FIFO two
  362. * characters at time by doing repeated word IO
  363. * transfer.
  364. */
  365. space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
  366. if (space < ToRecv) {
  367. #ifdef ROCKET_DEBUG_RECEIVE
  368. printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
  369. #endif
  370. if (space <= 0)
  371. return;
  372. ToRecv = space;
  373. }
  374. wRecv = ToRecv >> 1;
  375. if (wRecv)
  376. sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
  377. if (ToRecv & 1)
  378. cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
  379. }
  380. /* Push the data up to the tty layer */
  381. tty_flip_buffer_push(tty);
  382. }
  383. /*
  384. * Serial port transmit data function. Called from the timer polling loop as a
  385. * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
  386. * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
  387. * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
  388. */
  389. static void rp_do_transmit(struct r_port *info)
  390. {
  391. int c;
  392. CHANNEL_t *cp = &info->channel;
  393. struct tty_struct *tty;
  394. unsigned long flags;
  395. #ifdef ROCKET_DEBUG_INTR
  396. printk(KERN_INFO "rp_do_transmit ");
  397. #endif
  398. if (!info)
  399. return;
  400. if (!info->tty) {
  401. printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
  402. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  403. return;
  404. }
  405. spin_lock_irqsave(&info->slock, flags);
  406. tty = info->tty;
  407. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  408. /* Loop sending data to FIFO until done or FIFO full */
  409. while (1) {
  410. if (tty->stopped || tty->hw_stopped)
  411. break;
  412. c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
  413. if (c <= 0 || info->xmit_fifo_room <= 0)
  414. break;
  415. sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
  416. if (c & 1)
  417. sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
  418. info->xmit_tail += c;
  419. info->xmit_tail &= XMIT_BUF_SIZE - 1;
  420. info->xmit_cnt -= c;
  421. info->xmit_fifo_room -= c;
  422. #ifdef ROCKET_DEBUG_INTR
  423. printk(KERN_INFO "tx %d chars...", c);
  424. #endif
  425. }
  426. if (info->xmit_cnt == 0)
  427. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  428. if (info->xmit_cnt < WAKEUP_CHARS) {
  429. tty_wakeup(tty);
  430. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  431. wake_up_interruptible(&tty->poll_wait);
  432. #endif
  433. }
  434. spin_unlock_irqrestore(&info->slock, flags);
  435. #ifdef ROCKET_DEBUG_INTR
  436. printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
  437. info->xmit_tail, info->xmit_fifo_room);
  438. #endif
  439. }
  440. /*
  441. * Called when a serial port signals it has read data in it's RX FIFO.
  442. * It checks what interrupts are pending and services them, including
  443. * receiving serial data.
  444. */
  445. static void rp_handle_port(struct r_port *info)
  446. {
  447. CHANNEL_t *cp;
  448. struct tty_struct *tty;
  449. unsigned int IntMask, ChanStatus;
  450. if (!info)
  451. return;
  452. if ((info->flags & ROCKET_INITIALIZED) == 0) {
  453. printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
  454. return;
  455. }
  456. if (!info->tty) {
  457. printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
  458. return;
  459. }
  460. cp = &info->channel;
  461. tty = info->tty;
  462. IntMask = sGetChanIntID(cp) & info->intmask;
  463. #ifdef ROCKET_DEBUG_INTR
  464. printk(KERN_INFO "rp_interrupt %02x...", IntMask);
  465. #endif
  466. ChanStatus = sGetChanStatus(cp);
  467. if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
  468. rp_do_receive(info, tty, cp, ChanStatus);
  469. }
  470. if (IntMask & DELTA_CD) { /* CD change */
  471. #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
  472. printk(KERN_INFO "ttyR%d CD now %s...", info->line,
  473. (ChanStatus & CD_ACT) ? "on" : "off");
  474. #endif
  475. if (!(ChanStatus & CD_ACT) && info->cd_status) {
  476. #ifdef ROCKET_DEBUG_HANGUP
  477. printk(KERN_INFO "CD drop, calling hangup.\n");
  478. #endif
  479. tty_hangup(tty);
  480. }
  481. info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
  482. wake_up_interruptible(&info->open_wait);
  483. }
  484. #ifdef ROCKET_DEBUG_INTR
  485. if (IntMask & DELTA_CTS) { /* CTS change */
  486. printk(KERN_INFO "CTS change...\n");
  487. }
  488. if (IntMask & DELTA_DSR) { /* DSR change */
  489. printk(KERN_INFO "DSR change...\n");
  490. }
  491. #endif
  492. }
  493. /*
  494. * The top level polling routine. Repeats every 1/100 HZ (10ms).
  495. */
  496. static void rp_do_poll(unsigned long dummy)
  497. {
  498. CONTROLLER_t *ctlp;
  499. int ctrl, aiop, ch, line, i;
  500. unsigned int xmitmask;
  501. unsigned int CtlMask;
  502. unsigned char AiopMask;
  503. Word_t bit;
  504. /* Walk through all the boards (ctrl's) */
  505. for (ctrl = 0; ctrl < max_board; ctrl++) {
  506. if (rcktpt_io_addr[ctrl] <= 0)
  507. continue;
  508. /* Get a ptr to the board's control struct */
  509. ctlp = sCtlNumToCtlPtr(ctrl);
  510. /* Get the interupt status from the board */
  511. #ifdef CONFIG_PCI
  512. if (ctlp->BusType == isPCI)
  513. CtlMask = sPCIGetControllerIntStatus(ctlp);
  514. else
  515. #endif
  516. CtlMask = sGetControllerIntStatus(ctlp);
  517. /* Check if any AIOP read bits are set */
  518. for (aiop = 0; CtlMask; aiop++) {
  519. bit = ctlp->AiopIntrBits[aiop];
  520. if (CtlMask & bit) {
  521. CtlMask &= ~bit;
  522. AiopMask = sGetAiopIntStatus(ctlp, aiop);
  523. /* Check if any port read bits are set */
  524. for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
  525. if (AiopMask & 1) {
  526. /* Get the line number (/dev/ttyRx number). */
  527. /* Read the data from the port. */
  528. line = GetLineNumber(ctrl, aiop, ch);
  529. rp_handle_port(rp_table[line]);
  530. }
  531. }
  532. }
  533. }
  534. xmitmask = xmit_flags[ctrl];
  535. /*
  536. * xmit_flags contains bit-significant flags, indicating there is data
  537. * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
  538. * 1, ... (32 total possible). The variable i has the aiop and ch
  539. * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
  540. */
  541. if (xmitmask) {
  542. for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
  543. if (xmitmask & (1 << i)) {
  544. aiop = (i & 0x18) >> 3;
  545. ch = i & 0x07;
  546. line = GetLineNumber(ctrl, aiop, ch);
  547. rp_do_transmit(rp_table[line]);
  548. }
  549. }
  550. }
  551. }
  552. /*
  553. * Reset the timer so we get called at the next clock tick (10ms).
  554. */
  555. if (atomic_read(&rp_num_ports_open))
  556. mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
  557. }
  558. /*
  559. * Initializes the r_port structure for a port, as well as enabling the port on
  560. * the board.
  561. * Inputs: board, aiop, chan numbers
  562. */
  563. static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
  564. {
  565. unsigned rocketMode;
  566. struct r_port *info;
  567. int line;
  568. CONTROLLER_T *ctlp;
  569. /* Get the next available line number */
  570. line = SetLineNumber(board, aiop, chan);
  571. ctlp = sCtlNumToCtlPtr(board);
  572. /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
  573. info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
  574. if (!info) {
  575. printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
  576. return;
  577. }
  578. memset(info, 0, sizeof (struct r_port));
  579. info->magic = RPORT_MAGIC;
  580. info->line = line;
  581. info->ctlp = ctlp;
  582. info->board = board;
  583. info->aiop = aiop;
  584. info->chan = chan;
  585. info->closing_wait = 3000;
  586. info->close_delay = 50;
  587. init_waitqueue_head(&info->open_wait);
  588. init_waitqueue_head(&info->close_wait);
  589. info->flags &= ~ROCKET_MODE_MASK;
  590. switch (pc104[board][line]) {
  591. case 422:
  592. info->flags |= ROCKET_MODE_RS422;
  593. break;
  594. case 485:
  595. info->flags |= ROCKET_MODE_RS485;
  596. break;
  597. case 232:
  598. default:
  599. info->flags |= ROCKET_MODE_RS232;
  600. break;
  601. }
  602. info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
  603. if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
  604. printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
  605. kfree(info);
  606. return;
  607. }
  608. rocketMode = info->flags & ROCKET_MODE_MASK;
  609. if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
  610. sEnRTSToggle(&info->channel);
  611. else
  612. sDisRTSToggle(&info->channel);
  613. if (ctlp->boardType == ROCKET_TYPE_PC104) {
  614. switch (rocketMode) {
  615. case ROCKET_MODE_RS485:
  616. sSetInterfaceMode(&info->channel, InterfaceModeRS485);
  617. break;
  618. case ROCKET_MODE_RS422:
  619. sSetInterfaceMode(&info->channel, InterfaceModeRS422);
  620. break;
  621. case ROCKET_MODE_RS232:
  622. default:
  623. if (info->flags & ROCKET_RTS_TOGGLE)
  624. sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
  625. else
  626. sSetInterfaceMode(&info->channel, InterfaceModeRS232);
  627. break;
  628. }
  629. }
  630. spin_lock_init(&info->slock);
  631. sema_init(&info->write_sem, 1);
  632. rp_table[line] = info;
  633. if (pci_dev)
  634. tty_register_device(rocket_driver, line, &pci_dev->dev);
  635. }
  636. /*
  637. * Configures a rocketport port according to its termio settings. Called from
  638. * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
  639. */
  640. static void configure_r_port(struct r_port *info,
  641. struct ktermios *old_termios)
  642. {
  643. unsigned cflag;
  644. unsigned long flags;
  645. unsigned rocketMode;
  646. int bits, baud, divisor;
  647. CHANNEL_t *cp;
  648. if (!info->tty || !info->tty->termios)
  649. return;
  650. cp = &info->channel;
  651. cflag = info->tty->termios->c_cflag;
  652. /* Byte size and parity */
  653. if ((cflag & CSIZE) == CS8) {
  654. sSetData8(cp);
  655. bits = 10;
  656. } else {
  657. sSetData7(cp);
  658. bits = 9;
  659. }
  660. if (cflag & CSTOPB) {
  661. sSetStop2(cp);
  662. bits++;
  663. } else {
  664. sSetStop1(cp);
  665. }
  666. if (cflag & PARENB) {
  667. sEnParity(cp);
  668. bits++;
  669. if (cflag & PARODD) {
  670. sSetOddParity(cp);
  671. } else {
  672. sSetEvenParity(cp);
  673. }
  674. } else {
  675. sDisParity(cp);
  676. }
  677. /* baud rate */
  678. baud = tty_get_baud_rate(info->tty);
  679. if (!baud)
  680. baud = 9600;
  681. divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
  682. if ((divisor >= 8192 || divisor < 0) && old_termios) {
  683. info->tty->termios->c_cflag &= ~CBAUD;
  684. info->tty->termios->c_cflag |=
  685. (old_termios->c_cflag & CBAUD);
  686. baud = tty_get_baud_rate(info->tty);
  687. if (!baud)
  688. baud = 9600;
  689. divisor = (rp_baud_base[info->board] / baud) - 1;
  690. }
  691. if (divisor >= 8192 || divisor < 0) {
  692. baud = 9600;
  693. divisor = (rp_baud_base[info->board] / baud) - 1;
  694. }
  695. info->cps = baud / bits;
  696. sSetBaud(cp, divisor);
  697. if (cflag & CRTSCTS) {
  698. info->intmask |= DELTA_CTS;
  699. sEnCTSFlowCtl(cp);
  700. } else {
  701. info->intmask &= ~DELTA_CTS;
  702. sDisCTSFlowCtl(cp);
  703. }
  704. if (cflag & CLOCAL) {
  705. info->intmask &= ~DELTA_CD;
  706. } else {
  707. spin_lock_irqsave(&info->slock, flags);
  708. if (sGetChanStatus(cp) & CD_ACT)
  709. info->cd_status = 1;
  710. else
  711. info->cd_status = 0;
  712. info->intmask |= DELTA_CD;
  713. spin_unlock_irqrestore(&info->slock, flags);
  714. }
  715. /*
  716. * Handle software flow control in the board
  717. */
  718. #ifdef ROCKET_SOFT_FLOW
  719. if (I_IXON(info->tty)) {
  720. sEnTxSoftFlowCtl(cp);
  721. if (I_IXANY(info->tty)) {
  722. sEnIXANY(cp);
  723. } else {
  724. sDisIXANY(cp);
  725. }
  726. sSetTxXONChar(cp, START_CHAR(info->tty));
  727. sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
  728. } else {
  729. sDisTxSoftFlowCtl(cp);
  730. sDisIXANY(cp);
  731. sClrTxXOFF(cp);
  732. }
  733. #endif
  734. /*
  735. * Set up ignore/read mask words
  736. */
  737. info->read_status_mask = STMRCVROVRH | 0xFF;
  738. if (I_INPCK(info->tty))
  739. info->read_status_mask |= STMFRAMEH | STMPARITYH;
  740. if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
  741. info->read_status_mask |= STMBREAKH;
  742. /*
  743. * Characters to ignore
  744. */
  745. info->ignore_status_mask = 0;
  746. if (I_IGNPAR(info->tty))
  747. info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
  748. if (I_IGNBRK(info->tty)) {
  749. info->ignore_status_mask |= STMBREAKH;
  750. /*
  751. * If we're ignoring parity and break indicators,
  752. * ignore overruns too. (For real raw support).
  753. */
  754. if (I_IGNPAR(info->tty))
  755. info->ignore_status_mask |= STMRCVROVRH;
  756. }
  757. rocketMode = info->flags & ROCKET_MODE_MASK;
  758. if ((info->flags & ROCKET_RTS_TOGGLE)
  759. || (rocketMode == ROCKET_MODE_RS485))
  760. sEnRTSToggle(cp);
  761. else
  762. sDisRTSToggle(cp);
  763. sSetRTS(&info->channel);
  764. if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
  765. switch (rocketMode) {
  766. case ROCKET_MODE_RS485:
  767. sSetInterfaceMode(cp, InterfaceModeRS485);
  768. break;
  769. case ROCKET_MODE_RS422:
  770. sSetInterfaceMode(cp, InterfaceModeRS422);
  771. break;
  772. case ROCKET_MODE_RS232:
  773. default:
  774. if (info->flags & ROCKET_RTS_TOGGLE)
  775. sSetInterfaceMode(cp, InterfaceModeRS232T);
  776. else
  777. sSetInterfaceMode(cp, InterfaceModeRS232);
  778. break;
  779. }
  780. }
  781. }
  782. /* info->count is considered critical, protected by spinlocks. */
  783. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  784. struct r_port *info)
  785. {
  786. DECLARE_WAITQUEUE(wait, current);
  787. int retval;
  788. int do_clocal = 0, extra_count = 0;
  789. unsigned long flags;
  790. /*
  791. * If the device is in the middle of being closed, then block
  792. * until it's done, and then try again.
  793. */
  794. if (tty_hung_up_p(filp))
  795. return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
  796. if (info->flags & ROCKET_CLOSING) {
  797. interruptible_sleep_on(&info->close_wait);
  798. return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
  799. }
  800. /*
  801. * If non-blocking mode is set, or the port is not enabled,
  802. * then make the check up front and then exit.
  803. */
  804. if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
  805. info->flags |= ROCKET_NORMAL_ACTIVE;
  806. return 0;
  807. }
  808. if (tty->termios->c_cflag & CLOCAL)
  809. do_clocal = 1;
  810. /*
  811. * Block waiting for the carrier detect and the line to become free. While we are in
  812. * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
  813. * We restore it upon exit, either normal or abnormal.
  814. */
  815. retval = 0;
  816. add_wait_queue(&info->open_wait, &wait);
  817. #ifdef ROCKET_DEBUG_OPEN
  818. printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
  819. #endif
  820. spin_lock_irqsave(&info->slock, flags);
  821. #ifdef ROCKET_DISABLE_SIMUSAGE
  822. info->flags |= ROCKET_NORMAL_ACTIVE;
  823. #else
  824. if (!tty_hung_up_p(filp)) {
  825. extra_count = 1;
  826. info->count--;
  827. }
  828. #endif
  829. info->blocked_open++;
  830. spin_unlock_irqrestore(&info->slock, flags);
  831. while (1) {
  832. if (tty->termios->c_cflag & CBAUD) {
  833. sSetDTR(&info->channel);
  834. sSetRTS(&info->channel);
  835. }
  836. set_current_state(TASK_INTERRUPTIBLE);
  837. if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
  838. if (info->flags & ROCKET_HUP_NOTIFY)
  839. retval = -EAGAIN;
  840. else
  841. retval = -ERESTARTSYS;
  842. break;
  843. }
  844. if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
  845. break;
  846. if (signal_pending(current)) {
  847. retval = -ERESTARTSYS;
  848. break;
  849. }
  850. #ifdef ROCKET_DEBUG_OPEN
  851. printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
  852. info->line, info->count, info->flags);
  853. #endif
  854. schedule(); /* Don't hold spinlock here, will hang PC */
  855. }
  856. current->state = TASK_RUNNING;
  857. remove_wait_queue(&info->open_wait, &wait);
  858. spin_lock_irqsave(&info->slock, flags);
  859. if (extra_count)
  860. info->count++;
  861. info->blocked_open--;
  862. spin_unlock_irqrestore(&info->slock, flags);
  863. #ifdef ROCKET_DEBUG_OPEN
  864. printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
  865. info->line, info->count);
  866. #endif
  867. if (retval)
  868. return retval;
  869. info->flags |= ROCKET_NORMAL_ACTIVE;
  870. return 0;
  871. }
  872. /*
  873. * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
  874. * port's r_port struct. Initializes the port hardware.
  875. */
  876. static int rp_open(struct tty_struct *tty, struct file *filp)
  877. {
  878. struct r_port *info;
  879. int line = 0, retval;
  880. CHANNEL_t *cp;
  881. unsigned long page;
  882. line = TTY_GET_LINE(tty);
  883. if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
  884. return -ENXIO;
  885. page = __get_free_page(GFP_KERNEL);
  886. if (!page)
  887. return -ENOMEM;
  888. if (info->flags & ROCKET_CLOSING) {
  889. interruptible_sleep_on(&info->close_wait);
  890. free_page(page);
  891. return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
  892. }
  893. /*
  894. * We must not sleep from here until the port is marked fully in use.
  895. */
  896. if (info->xmit_buf)
  897. free_page(page);
  898. else
  899. info->xmit_buf = (unsigned char *) page;
  900. tty->driver_data = info;
  901. info->tty = tty;
  902. if (info->count++ == 0) {
  903. atomic_inc(&rp_num_ports_open);
  904. #ifdef ROCKET_DEBUG_OPEN
  905. printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
  906. #endif
  907. }
  908. #ifdef ROCKET_DEBUG_OPEN
  909. printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
  910. #endif
  911. /*
  912. * Info->count is now 1; so it's safe to sleep now.
  913. */
  914. info->session = process_session(current);
  915. info->pgrp = process_group(current);
  916. if ((info->flags & ROCKET_INITIALIZED) == 0) {
  917. cp = &info->channel;
  918. sSetRxTrigger(cp, TRIG_1);
  919. if (sGetChanStatus(cp) & CD_ACT)
  920. info->cd_status = 1;
  921. else
  922. info->cd_status = 0;
  923. sDisRxStatusMode(cp);
  924. sFlushRxFIFO(cp);
  925. sFlushTxFIFO(cp);
  926. sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  927. sSetRxTrigger(cp, TRIG_1);
  928. sGetChanStatus(cp);
  929. sDisRxStatusMode(cp);
  930. sClrTxXOFF(cp);
  931. sDisCTSFlowCtl(cp);
  932. sDisTxSoftFlowCtl(cp);
  933. sEnRxFIFO(cp);
  934. sEnTransmit(cp);
  935. info->flags |= ROCKET_INITIALIZED;
  936. /*
  937. * Set up the tty->alt_speed kludge
  938. */
  939. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
  940. info->tty->alt_speed = 57600;
  941. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
  942. info->tty->alt_speed = 115200;
  943. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
  944. info->tty->alt_speed = 230400;
  945. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
  946. info->tty->alt_speed = 460800;
  947. configure_r_port(info, NULL);
  948. if (tty->termios->c_cflag & CBAUD) {
  949. sSetDTR(cp);
  950. sSetRTS(cp);
  951. }
  952. }
  953. /* Starts (or resets) the maint polling loop */
  954. mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
  955. retval = block_til_ready(tty, filp, info);
  956. if (retval) {
  957. #ifdef ROCKET_DEBUG_OPEN
  958. printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
  959. #endif
  960. return retval;
  961. }
  962. return 0;
  963. }
  964. /*
  965. * Exception handler that closes a serial port. info->count is considered critical.
  966. */
  967. static void rp_close(struct tty_struct *tty, struct file *filp)
  968. {
  969. struct r_port *info = (struct r_port *) tty->driver_data;
  970. unsigned long flags;
  971. int timeout;
  972. CHANNEL_t *cp;
  973. if (rocket_paranoia_check(info, "rp_close"))
  974. return;
  975. #ifdef ROCKET_DEBUG_OPEN
  976. printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
  977. #endif
  978. if (tty_hung_up_p(filp))
  979. return;
  980. spin_lock_irqsave(&info->slock, flags);
  981. if ((tty->count == 1) && (info->count != 1)) {
  982. /*
  983. * Uh, oh. tty->count is 1, which means that the tty
  984. * structure will be freed. Info->count should always
  985. * be one in these conditions. If it's greater than
  986. * one, we've got real problems, since it means the
  987. * serial port won't be shutdown.
  988. */
  989. printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
  990. "info->count is %d\n", info->count);
  991. info->count = 1;
  992. }
  993. if (--info->count < 0) {
  994. printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
  995. info->line, info->count);
  996. info->count = 0;
  997. }
  998. if (info->count) {
  999. spin_unlock_irqrestore(&info->slock, flags);
  1000. return;
  1001. }
  1002. info->flags |= ROCKET_CLOSING;
  1003. spin_unlock_irqrestore(&info->slock, flags);
  1004. cp = &info->channel;
  1005. /*
  1006. * Notify the line discpline to only process XON/XOFF characters
  1007. */
  1008. tty->closing = 1;
  1009. /*
  1010. * If transmission was throttled by the application request,
  1011. * just flush the xmit buffer.
  1012. */
  1013. if (tty->flow_stopped)
  1014. rp_flush_buffer(tty);
  1015. /*
  1016. * Wait for the transmit buffer to clear
  1017. */
  1018. if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
  1019. tty_wait_until_sent(tty, info->closing_wait);
  1020. /*
  1021. * Before we drop DTR, make sure the UART transmitter
  1022. * has completely drained; this is especially
  1023. * important if there is a transmit FIFO!
  1024. */
  1025. timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
  1026. if (timeout == 0)
  1027. timeout = 1;
  1028. rp_wait_until_sent(tty, timeout);
  1029. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1030. sDisTransmit(cp);
  1031. sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  1032. sDisCTSFlowCtl(cp);
  1033. sDisTxSoftFlowCtl(cp);
  1034. sClrTxXOFF(cp);
  1035. sFlushRxFIFO(cp);
  1036. sFlushTxFIFO(cp);
  1037. sClrRTS(cp);
  1038. if (C_HUPCL(tty))
  1039. sClrDTR(cp);
  1040. if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
  1041. TTY_DRIVER_FLUSH_BUFFER(tty);
  1042. tty_ldisc_flush(tty);
  1043. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1044. if (info->blocked_open) {
  1045. if (info->close_delay) {
  1046. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  1047. }
  1048. wake_up_interruptible(&info->open_wait);
  1049. } else {
  1050. if (info->xmit_buf) {
  1051. free_page((unsigned long) info->xmit_buf);
  1052. info->xmit_buf = NULL;
  1053. }
  1054. }
  1055. info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
  1056. tty->closing = 0;
  1057. wake_up_interruptible(&info->close_wait);
  1058. atomic_dec(&rp_num_ports_open);
  1059. #ifdef ROCKET_DEBUG_OPEN
  1060. printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
  1061. printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
  1062. #endif
  1063. }
  1064. static void rp_set_termios(struct tty_struct *tty,
  1065. struct ktermios *old_termios)
  1066. {
  1067. struct r_port *info = (struct r_port *) tty->driver_data;
  1068. CHANNEL_t *cp;
  1069. unsigned cflag;
  1070. if (rocket_paranoia_check(info, "rp_set_termios"))
  1071. return;
  1072. cflag = tty->termios->c_cflag;
  1073. if (cflag == old_termios->c_cflag)
  1074. return;
  1075. /*
  1076. * This driver doesn't support CS5 or CS6
  1077. */
  1078. if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
  1079. tty->termios->c_cflag =
  1080. ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
  1081. configure_r_port(info, old_termios);
  1082. cp = &info->channel;
  1083. /* Handle transition to B0 status */
  1084. if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
  1085. sClrDTR(cp);
  1086. sClrRTS(cp);
  1087. }
  1088. /* Handle transition away from B0 status */
  1089. if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
  1090. if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
  1091. sSetRTS(cp);
  1092. sSetDTR(cp);
  1093. }
  1094. if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
  1095. tty->hw_stopped = 0;
  1096. rp_start(tty);
  1097. }
  1098. }
  1099. static void rp_break(struct tty_struct *tty, int break_state)
  1100. {
  1101. struct r_port *info = (struct r_port *) tty->driver_data;
  1102. unsigned long flags;
  1103. if (rocket_paranoia_check(info, "rp_break"))
  1104. return;
  1105. spin_lock_irqsave(&info->slock, flags);
  1106. if (break_state == -1)
  1107. sSendBreak(&info->channel);
  1108. else
  1109. sClrBreak(&info->channel);
  1110. spin_unlock_irqrestore(&info->slock, flags);
  1111. }
  1112. /*
  1113. * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
  1114. * the UPCI boards was added, it was decided to make this a function because
  1115. * the macro was getting too complicated. All cases except the first one
  1116. * (UPCIRingInd) are taken directly from the original macro.
  1117. */
  1118. static int sGetChanRI(CHANNEL_T * ChP)
  1119. {
  1120. CONTROLLER_t *CtlP = ChP->CtlP;
  1121. int ChanNum = ChP->ChanNum;
  1122. int RingInd = 0;
  1123. if (CtlP->UPCIRingInd)
  1124. RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
  1125. else if (CtlP->AltChanRingIndicator)
  1126. RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
  1127. else if (CtlP->boardType == ROCKET_TYPE_PC104)
  1128. RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
  1129. return RingInd;
  1130. }
  1131. /********************************************************************************************/
  1132. /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
  1133. /*
  1134. * Returns the state of the serial modem control lines. These next 2 functions
  1135. * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
  1136. */
  1137. static int rp_tiocmget(struct tty_struct *tty, struct file *file)
  1138. {
  1139. struct r_port *info = (struct r_port *)tty->driver_data;
  1140. unsigned int control, result, ChanStatus;
  1141. ChanStatus = sGetChanStatusLo(&info->channel);
  1142. control = info->channel.TxControl[3];
  1143. result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
  1144. ((control & SET_DTR) ? TIOCM_DTR : 0) |
  1145. ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
  1146. (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
  1147. ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
  1148. ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
  1149. return result;
  1150. }
  1151. /*
  1152. * Sets the modem control lines
  1153. */
  1154. static int rp_tiocmset(struct tty_struct *tty, struct file *file,
  1155. unsigned int set, unsigned int clear)
  1156. {
  1157. struct r_port *info = (struct r_port *)tty->driver_data;
  1158. if (set & TIOCM_RTS)
  1159. info->channel.TxControl[3] |= SET_RTS;
  1160. if (set & TIOCM_DTR)
  1161. info->channel.TxControl[3] |= SET_DTR;
  1162. if (clear & TIOCM_RTS)
  1163. info->channel.TxControl[3] &= ~SET_RTS;
  1164. if (clear & TIOCM_DTR)
  1165. info->channel.TxControl[3] &= ~SET_DTR;
  1166. sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
  1167. return 0;
  1168. }
  1169. static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
  1170. {
  1171. struct rocket_config tmp;
  1172. if (!retinfo)
  1173. return -EFAULT;
  1174. memset(&tmp, 0, sizeof (tmp));
  1175. tmp.line = info->line;
  1176. tmp.flags = info->flags;
  1177. tmp.close_delay = info->close_delay;
  1178. tmp.closing_wait = info->closing_wait;
  1179. tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
  1180. if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
  1181. return -EFAULT;
  1182. return 0;
  1183. }
  1184. static int set_config(struct r_port *info, struct rocket_config __user *new_info)
  1185. {
  1186. struct rocket_config new_serial;
  1187. if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
  1188. return -EFAULT;
  1189. if (!capable(CAP_SYS_ADMIN))
  1190. {
  1191. if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
  1192. return -EPERM;
  1193. info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
  1194. configure_r_port(info, NULL);
  1195. return 0;
  1196. }
  1197. info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
  1198. info->close_delay = new_serial.close_delay;
  1199. info->closing_wait = new_serial.closing_wait;
  1200. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
  1201. info->tty->alt_speed = 57600;
  1202. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
  1203. info->tty->alt_speed = 115200;
  1204. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
  1205. info->tty->alt_speed = 230400;
  1206. if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
  1207. info->tty->alt_speed = 460800;
  1208. configure_r_port(info, NULL);
  1209. return 0;
  1210. }
  1211. /*
  1212. * This function fills in a rocket_ports struct with information
  1213. * about what boards/ports are in the system. This info is passed
  1214. * to user space. See setrocket.c where the info is used to create
  1215. * the /dev/ttyRx ports.
  1216. */
  1217. static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
  1218. {
  1219. struct rocket_ports tmp;
  1220. int board;
  1221. if (!retports)
  1222. return -EFAULT;
  1223. memset(&tmp, 0, sizeof (tmp));
  1224. tmp.tty_major = rocket_driver->major;
  1225. for (board = 0; board < 4; board++) {
  1226. tmp.rocketModel[board].model = rocketModel[board].model;
  1227. strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
  1228. tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
  1229. tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
  1230. tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
  1231. }
  1232. if (copy_to_user(retports, &tmp, sizeof (*retports)))
  1233. return -EFAULT;
  1234. return 0;
  1235. }
  1236. static int reset_rm2(struct r_port *info, void __user *arg)
  1237. {
  1238. int reset;
  1239. if (copy_from_user(&reset, arg, sizeof (int)))
  1240. return -EFAULT;
  1241. if (reset)
  1242. reset = 1;
  1243. if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
  1244. rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
  1245. return -EINVAL;
  1246. if (info->ctlp->BusType == isISA)
  1247. sModemReset(info->ctlp, info->chan, reset);
  1248. else
  1249. sPCIModemReset(info->ctlp, info->chan, reset);
  1250. return 0;
  1251. }
  1252. static int get_version(struct r_port *info, struct rocket_version __user *retvers)
  1253. {
  1254. if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
  1255. return -EFAULT;
  1256. return 0;
  1257. }
  1258. /* IOCTL call handler into the driver */
  1259. static int rp_ioctl(struct tty_struct *tty, struct file *file,
  1260. unsigned int cmd, unsigned long arg)
  1261. {
  1262. struct r_port *info = (struct r_port *) tty->driver_data;
  1263. void __user *argp = (void __user *)arg;
  1264. if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
  1265. return -ENXIO;
  1266. switch (cmd) {
  1267. case RCKP_GET_STRUCT:
  1268. if (copy_to_user(argp, info, sizeof (struct r_port)))
  1269. return -EFAULT;
  1270. return 0;
  1271. case RCKP_GET_CONFIG:
  1272. return get_config(info, argp);
  1273. case RCKP_SET_CONFIG:
  1274. return set_config(info, argp);
  1275. case RCKP_GET_PORTS:
  1276. return get_ports(info, argp);
  1277. case RCKP_RESET_RM2:
  1278. return reset_rm2(info, argp);
  1279. case RCKP_GET_VERSION:
  1280. return get_version(info, argp);
  1281. default:
  1282. return -ENOIOCTLCMD;
  1283. }
  1284. return 0;
  1285. }
  1286. static void rp_send_xchar(struct tty_struct *tty, char ch)
  1287. {
  1288. struct r_port *info = (struct r_port *) tty->driver_data;
  1289. CHANNEL_t *cp;
  1290. if (rocket_paranoia_check(info, "rp_send_xchar"))
  1291. return;
  1292. cp = &info->channel;
  1293. if (sGetTxCnt(cp))
  1294. sWriteTxPrioByte(cp, ch);
  1295. else
  1296. sWriteTxByte(sGetTxRxDataIO(cp), ch);
  1297. }
  1298. static void rp_throttle(struct tty_struct *tty)
  1299. {
  1300. struct r_port *info = (struct r_port *) tty->driver_data;
  1301. CHANNEL_t *cp;
  1302. #ifdef ROCKET_DEBUG_THROTTLE
  1303. printk(KERN_INFO "throttle %s: %d....\n", tty->name,
  1304. tty->ldisc.chars_in_buffer(tty));
  1305. #endif
  1306. if (rocket_paranoia_check(info, "rp_throttle"))
  1307. return;
  1308. cp = &info->channel;
  1309. if (I_IXOFF(tty))
  1310. rp_send_xchar(tty, STOP_CHAR(tty));
  1311. sClrRTS(&info->channel);
  1312. }
  1313. static void rp_unthrottle(struct tty_struct *tty)
  1314. {
  1315. struct r_port *info = (struct r_port *) tty->driver_data;
  1316. CHANNEL_t *cp;
  1317. #ifdef ROCKET_DEBUG_THROTTLE
  1318. printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
  1319. tty->ldisc.chars_in_buffer(tty));
  1320. #endif
  1321. if (rocket_paranoia_check(info, "rp_throttle"))
  1322. return;
  1323. cp = &info->channel;
  1324. if (I_IXOFF(tty))
  1325. rp_send_xchar(tty, START_CHAR(tty));
  1326. sSetRTS(&info->channel);
  1327. }
  1328. /*
  1329. * ------------------------------------------------------------
  1330. * rp_stop() and rp_start()
  1331. *
  1332. * This routines are called before setting or resetting tty->stopped.
  1333. * They enable or disable transmitter interrupts, as necessary.
  1334. * ------------------------------------------------------------
  1335. */
  1336. static void rp_stop(struct tty_struct *tty)
  1337. {
  1338. struct r_port *info = (struct r_port *) tty->driver_data;
  1339. #ifdef ROCKET_DEBUG_FLOW
  1340. printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
  1341. info->xmit_cnt, info->xmit_fifo_room);
  1342. #endif
  1343. if (rocket_paranoia_check(info, "rp_stop"))
  1344. return;
  1345. if (sGetTxCnt(&info->channel))
  1346. sDisTransmit(&info->channel);
  1347. }
  1348. static void rp_start(struct tty_struct *tty)
  1349. {
  1350. struct r_port *info = (struct r_port *) tty->driver_data;
  1351. #ifdef ROCKET_DEBUG_FLOW
  1352. printk(KERN_INFO "start %s: %d %d....\n", tty->name,
  1353. info->xmit_cnt, info->xmit_fifo_room);
  1354. #endif
  1355. if (rocket_paranoia_check(info, "rp_stop"))
  1356. return;
  1357. sEnTransmit(&info->channel);
  1358. set_bit((info->aiop * 8) + info->chan,
  1359. (void *) &xmit_flags[info->board]);
  1360. }
  1361. /*
  1362. * rp_wait_until_sent() --- wait until the transmitter is empty
  1363. */
  1364. static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
  1365. {
  1366. struct r_port *info = (struct r_port *) tty->driver_data;
  1367. CHANNEL_t *cp;
  1368. unsigned long orig_jiffies;
  1369. int check_time, exit_time;
  1370. int txcnt;
  1371. if (rocket_paranoia_check(info, "rp_wait_until_sent"))
  1372. return;
  1373. cp = &info->channel;
  1374. orig_jiffies = jiffies;
  1375. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1376. printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
  1377. jiffies);
  1378. printk(KERN_INFO "cps=%d...", info->cps);
  1379. #endif
  1380. while (1) {
  1381. txcnt = sGetTxCnt(cp);
  1382. if (!txcnt) {
  1383. if (sGetChanStatusLo(cp) & TXSHRMT)
  1384. break;
  1385. check_time = (HZ / info->cps) / 5;
  1386. } else {
  1387. check_time = HZ * txcnt / info->cps;
  1388. }
  1389. if (timeout) {
  1390. exit_time = orig_jiffies + timeout - jiffies;
  1391. if (exit_time <= 0)
  1392. break;
  1393. if (exit_time < check_time)
  1394. check_time = exit_time;
  1395. }
  1396. if (check_time == 0)
  1397. check_time = 1;
  1398. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1399. printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
  1400. #endif
  1401. msleep_interruptible(jiffies_to_msecs(check_time));
  1402. if (signal_pending(current))
  1403. break;
  1404. }
  1405. current->state = TASK_RUNNING;
  1406. #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
  1407. printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
  1408. #endif
  1409. }
  1410. /*
  1411. * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
  1412. */
  1413. static void rp_hangup(struct tty_struct *tty)
  1414. {
  1415. CHANNEL_t *cp;
  1416. struct r_port *info = (struct r_port *) tty->driver_data;
  1417. if (rocket_paranoia_check(info, "rp_hangup"))
  1418. return;
  1419. #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
  1420. printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
  1421. #endif
  1422. rp_flush_buffer(tty);
  1423. if (info->flags & ROCKET_CLOSING)
  1424. return;
  1425. if (info->count)
  1426. atomic_dec(&rp_num_ports_open);
  1427. clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1428. info->count = 0;
  1429. info->flags &= ~ROCKET_NORMAL_ACTIVE;
  1430. info->tty = NULL;
  1431. cp = &info->channel;
  1432. sDisRxFIFO(cp);
  1433. sDisTransmit(cp);
  1434. sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
  1435. sDisCTSFlowCtl(cp);
  1436. sDisTxSoftFlowCtl(cp);
  1437. sClrTxXOFF(cp);
  1438. info->flags &= ~ROCKET_INITIALIZED;
  1439. wake_up_interruptible(&info->open_wait);
  1440. }
  1441. /*
  1442. * Exception handler - write char routine. The RocketPort driver uses a
  1443. * double-buffering strategy, with the twist that if the in-memory CPU
  1444. * buffer is empty, and there's space in the transmit FIFO, the
  1445. * writing routines will write directly to transmit FIFO.
  1446. * Write buffer and counters protected by spinlocks
  1447. */
  1448. static void rp_put_char(struct tty_struct *tty, unsigned char ch)
  1449. {
  1450. struct r_port *info = (struct r_port *) tty->driver_data;
  1451. CHANNEL_t *cp;
  1452. unsigned long flags;
  1453. if (rocket_paranoia_check(info, "rp_put_char"))
  1454. return;
  1455. /* Grab the port write semaphore, locking out other processes that try to write to this port */
  1456. down(&info->write_sem);
  1457. #ifdef ROCKET_DEBUG_WRITE
  1458. printk(KERN_INFO "rp_put_char %c...", ch);
  1459. #endif
  1460. spin_lock_irqsave(&info->slock, flags);
  1461. cp = &info->channel;
  1462. if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
  1463. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  1464. if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
  1465. info->xmit_buf[info->xmit_head++] = ch;
  1466. info->xmit_head &= XMIT_BUF_SIZE - 1;
  1467. info->xmit_cnt++;
  1468. set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1469. } else {
  1470. sOutB(sGetTxRxDataIO(cp), ch);
  1471. info->xmit_fifo_room--;
  1472. }
  1473. spin_unlock_irqrestore(&info->slock, flags);
  1474. up(&info->write_sem);
  1475. }
  1476. /*
  1477. * Exception handler - write routine, called when user app writes to the device.
  1478. * A per port write semaphore is used to protect from another process writing to
  1479. * this port at the same time. This other process could be running on the other CPU
  1480. * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
  1481. * Spinlocks protect the info xmit members.
  1482. */
  1483. static int rp_write(struct tty_struct *tty,
  1484. const unsigned char *buf, int count)
  1485. {
  1486. struct r_port *info = (struct r_port *) tty->driver_data;
  1487. CHANNEL_t *cp;
  1488. const unsigned char *b;
  1489. int c, retval = 0;
  1490. unsigned long flags;
  1491. if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
  1492. return 0;
  1493. down_interruptible(&info->write_sem);
  1494. #ifdef ROCKET_DEBUG_WRITE
  1495. printk(KERN_INFO "rp_write %d chars...", count);
  1496. #endif
  1497. cp = &info->channel;
  1498. if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
  1499. info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
  1500. /*
  1501. * If the write queue for the port is empty, and there is FIFO space, stuff bytes
  1502. * into FIFO. Use the write queue for temp storage.
  1503. */
  1504. if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
  1505. c = min(count, info->xmit_fifo_room);
  1506. b = buf;
  1507. /* Push data into FIFO, 2 bytes at a time */
  1508. sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
  1509. /* If there is a byte remaining, write it */
  1510. if (c & 1)
  1511. sOutB(sGetTxRxDataIO(cp), b[c - 1]);
  1512. retval += c;
  1513. buf += c;
  1514. count -= c;
  1515. spin_lock_irqsave(&info->slock, flags);
  1516. info->xmit_fifo_room -= c;
  1517. spin_unlock_irqrestore(&info->slock, flags);
  1518. }
  1519. /* If count is zero, we wrote it all and are done */
  1520. if (!count)
  1521. goto end;
  1522. /* Write remaining data into the port's xmit_buf */
  1523. while (1) {
  1524. if (info->tty == 0) /* Seemingly obligatory check... */
  1525. goto end;
  1526. c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
  1527. if (c <= 0)
  1528. break;
  1529. b = buf;
  1530. memcpy(info->xmit_buf + info->xmit_head, b, c);
  1531. spin_lock_irqsave(&info->slock, flags);
  1532. info->xmit_head =
  1533. (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
  1534. info->xmit_cnt += c;
  1535. spin_unlock_irqrestore(&info->slock, flags);
  1536. buf += c;
  1537. count -= c;
  1538. retval += c;
  1539. }
  1540. if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
  1541. set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
  1542. end:
  1543. if (info->xmit_cnt < WAKEUP_CHARS) {
  1544. tty_wakeup(tty);
  1545. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  1546. wake_up_interruptible(&tty->poll_wait);
  1547. #endif
  1548. }
  1549. up(&info->write_sem);
  1550. return retval;
  1551. }
  1552. /*
  1553. * Return the number of characters that can be sent. We estimate
  1554. * only using the in-memory transmit buffer only, and ignore the
  1555. * potential space in the transmit FIFO.
  1556. */
  1557. static int rp_write_room(struct tty_struct *tty)
  1558. {
  1559. struct r_port *info = (struct r_port *) tty->driver_data;
  1560. int ret;
  1561. if (rocket_paranoia_check(info, "rp_write_room"))
  1562. return 0;
  1563. ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
  1564. if (ret < 0)
  1565. ret = 0;
  1566. #ifdef ROCKET_DEBUG_WRITE
  1567. printk(KERN_INFO "rp_write_room returns %d...", ret);
  1568. #endif
  1569. return ret;
  1570. }
  1571. /*
  1572. * Return the number of characters in the buffer. Again, this only
  1573. * counts those characters in the in-memory transmit buffer.
  1574. */
  1575. static int rp_chars_in_buffer(struct tty_struct *tty)
  1576. {
  1577. struct r_port *info = (struct r_port *) tty->driver_data;
  1578. CHANNEL_t *cp;
  1579. if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
  1580. return 0;
  1581. cp = &info->channel;
  1582. #ifdef ROCKET_DEBUG_WRITE
  1583. printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
  1584. #endif
  1585. return info->xmit_cnt;
  1586. }
  1587. /*
  1588. * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
  1589. * r_port struct for the port. Note that spinlock are used to protect info members,
  1590. * do not call this function if the spinlock is already held.
  1591. */
  1592. static void rp_flush_buffer(struct tty_struct *tty)
  1593. {
  1594. struct r_port *info = (struct r_port *) tty->driver_data;
  1595. CHANNEL_t *cp;
  1596. unsigned long flags;
  1597. if (rocket_paranoia_check(info, "rp_flush_buffer"))
  1598. return;
  1599. spin_lock_irqsave(&info->slock, flags);
  1600. info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
  1601. spin_unlock_irqrestore(&info->slock, flags);
  1602. #ifdef ROCKETPORT_HAVE_POLL_WAIT
  1603. wake_up_interruptible(&tty->poll_wait);
  1604. #endif
  1605. tty_wakeup(tty);
  1606. cp = &info->channel;
  1607. sFlushTxFIFO(cp);
  1608. }
  1609. #ifdef CONFIG_PCI
  1610. /*
  1611. * Called when a PCI card is found. Retrieves and stores model information,
  1612. * init's aiopic and serial port hardware.
  1613. * Inputs: i is the board number (0-n)
  1614. */
  1615. static __init int register_PCI(int i, struct pci_dev *dev)
  1616. {
  1617. int num_aiops, aiop, max_num_aiops, num_chan, chan;
  1618. unsigned int aiopio[MAX_AIOPS_PER_BOARD];
  1619. char *str, *board_type;
  1620. CONTROLLER_t *ctlp;
  1621. int fast_clock = 0;
  1622. int altChanRingIndicator = 0;
  1623. int ports_per_aiop = 8;
  1624. int ret;
  1625. unsigned int class_rev;
  1626. WordIO_t ConfigIO = 0;
  1627. ByteIO_t UPCIRingInd = 0;
  1628. if (!dev || pci_enable_device(dev))
  1629. return 0;
  1630. rcktpt_io_addr[i] = pci_resource_start(dev, 0);
  1631. ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
  1632. if (ret) {
  1633. printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
  1634. return 0;
  1635. }
  1636. rcktpt_type[i] = ROCKET_TYPE_NORMAL;
  1637. rocketModel[i].loadrm2 = 0;
  1638. rocketModel[i].startingPortNumber = nextLineNumber;
  1639. /* Depending on the model, set up some config variables */
  1640. switch (dev->device) {
  1641. case PCI_DEVICE_ID_RP4QUAD:
  1642. str = "Quadcable";
  1643. max_num_aiops = 1;
  1644. ports_per_aiop = 4;
  1645. rocketModel[i].model = MODEL_RP4QUAD;
  1646. strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
  1647. rocketModel[i].numPorts = 4;
  1648. break;
  1649. case PCI_DEVICE_ID_RP8OCTA:
  1650. str = "Octacable";
  1651. max_num_aiops = 1;
  1652. rocketModel[i].model = MODEL_RP8OCTA;
  1653. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
  1654. rocketModel[i].numPorts = 8;
  1655. break;
  1656. case PCI_DEVICE_ID_URP8OCTA:
  1657. str = "Octacable";
  1658. max_num_aiops = 1;
  1659. rocketModel[i].model = MODEL_UPCI_RP8OCTA;
  1660. strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
  1661. rocketModel[i].numPorts = 8;
  1662. break;
  1663. case PCI_DEVICE_ID_RP8INTF:
  1664. str = "8";
  1665. max_num_aiops = 1;
  1666. rocketModel[i].model = MODEL_RP8INTF;
  1667. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
  1668. rocketModel[i].numPorts = 8;
  1669. break;
  1670. case PCI_DEVICE_ID_URP8INTF:
  1671. str = "8";
  1672. max_num_aiops = 1;
  1673. rocketModel[i].model = MODEL_UPCI_RP8INTF;
  1674. strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
  1675. rocketModel[i].numPorts = 8;
  1676. break;
  1677. case PCI_DEVICE_ID_RP8J:
  1678. str = "8J";
  1679. max_num_aiops = 1;
  1680. rocketModel[i].model = MODEL_RP8J;
  1681. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
  1682. rocketModel[i].numPorts = 8;
  1683. break;
  1684. case PCI_DEVICE_ID_RP4J:
  1685. str = "4J";
  1686. max_num_aiops = 1;
  1687. ports_per_aiop = 4;
  1688. rocketModel[i].model = MODEL_RP4J;
  1689. strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
  1690. rocketModel[i].numPorts = 4;
  1691. break;
  1692. case PCI_DEVICE_ID_RP8SNI:
  1693. str = "8 (DB78 Custom)";
  1694. max_num_aiops = 1;
  1695. rocketModel[i].model = MODEL_RP8SNI;
  1696. strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
  1697. rocketModel[i].numPorts = 8;
  1698. break;
  1699. case PCI_DEVICE_ID_RP16SNI:
  1700. str = "16 (DB78 Custom)";
  1701. max_num_aiops = 2;
  1702. rocketModel[i].model = MODEL_RP16SNI;
  1703. strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
  1704. rocketModel[i].numPorts = 16;
  1705. break;
  1706. case PCI_DEVICE_ID_RP16INTF:
  1707. str = "16";
  1708. max_num_aiops = 2;
  1709. rocketModel[i].model = MODEL_RP16INTF;
  1710. strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
  1711. rocketModel[i].numPorts = 16;
  1712. break;
  1713. case PCI_DEVICE_ID_URP16INTF:
  1714. str = "16";
  1715. max_num_aiops = 2;
  1716. rocketModel[i].model = MODEL_UPCI_RP16INTF;
  1717. strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
  1718. rocketModel[i].numPorts = 16;
  1719. break;
  1720. case PCI_DEVICE_ID_CRP16INTF:
  1721. str = "16";
  1722. max_num_aiops = 2;
  1723. rocketModel[i].model = MODEL_CPCI_RP16INTF;
  1724. strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
  1725. rocketModel[i].numPorts = 16;
  1726. break;
  1727. case PCI_DEVICE_ID_RP32INTF:
  1728. str = "32";
  1729. max_num_aiops = 4;
  1730. rocketModel[i].model = MODEL_RP32INTF;
  1731. strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
  1732. rocketModel[i].numPorts = 32;
  1733. break;
  1734. case PCI_DEVICE_ID_URP32INTF:
  1735. str = "32";
  1736. max_num_aiops = 4;
  1737. rocketModel[i].model = MODEL_UPCI_RP32INTF;
  1738. strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
  1739. rocketModel[i].numPorts = 32;
  1740. break;
  1741. case PCI_DEVICE_ID_RPP4:
  1742. str = "Plus Quadcable";
  1743. max_num_aiops = 1;
  1744. ports_per_aiop = 4;
  1745. altChanRingIndicator++;
  1746. fast_clock++;
  1747. rocketModel[i].model = MODEL_RPP4;
  1748. strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
  1749. rocketModel[i].numPorts = 4;
  1750. break;
  1751. case PCI_DEVICE_ID_RPP8:
  1752. str = "Plus Octacable";
  1753. max_num_aiops = 2;
  1754. ports_per_aiop = 4;
  1755. altChanRingIndicator++;
  1756. fast_clock++;
  1757. rocketModel[i].model = MODEL_RPP8;
  1758. strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
  1759. rocketModel[i].numPorts = 8;
  1760. break;
  1761. case PCI_DEVICE_ID_RP2_232:
  1762. str = "Plus 2 (RS-232)";
  1763. max_num_aiops = 1;
  1764. ports_per_aiop = 2;
  1765. altChanRingIndicator++;
  1766. fast_clock++;
  1767. rocketModel[i].model = MODEL_RP2_232;
  1768. strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
  1769. rocketModel[i].numPorts = 2;
  1770. break;
  1771. case PCI_DEVICE_ID_RP2_422:
  1772. str = "Plus 2 (RS-422)";
  1773. max_num_aiops = 1;
  1774. ports_per_aiop = 2;
  1775. altChanRingIndicator++;
  1776. fast_clock++;
  1777. rocketModel[i].model = MODEL_RP2_422;
  1778. strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
  1779. rocketModel[i].numPorts = 2;
  1780. break;
  1781. case PCI_DEVICE_ID_RP6M:
  1782. max_num_aiops = 1;
  1783. ports_per_aiop = 6;
  1784. str = "6-port";
  1785. /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
  1786. if ((class_rev & 0xFF) == 1) {
  1787. rcktpt_type[i] = ROCKET_TYPE_MODEMII;
  1788. rocketModel[i].loadrm2 = 1;
  1789. } else {
  1790. rcktpt_type[i] = ROCKET_TYPE_MODEM;
  1791. }
  1792. rocketModel[i].model = MODEL_RP6M;
  1793. strcpy(rocketModel[i].modelString, "RocketModem 6 port");
  1794. rocketModel[i].numPorts = 6;
  1795. break;
  1796. case PCI_DEVICE_ID_RP4M:
  1797. max_num_aiops = 1;
  1798. ports_per_aiop = 4;
  1799. str = "4-port";
  1800. if ((class_rev & 0xFF) == 1) {
  1801. rcktpt_type[i] = ROCKET_TYPE_MODEMII;
  1802. rocketModel[i].loadrm2 = 1;
  1803. } else {
  1804. rcktpt_type[i] = ROCKET_TYPE_MODEM;
  1805. }
  1806. rocketModel[i].model = MODEL_RP4M;
  1807. strcpy(rocketModel[i].modelString, "RocketModem 4 port");
  1808. rocketModel[i].numPorts = 4;
  1809. break;
  1810. default:
  1811. str = "(unknown/unsupported)";
  1812. max_num_aiops = 0;
  1813. break;
  1814. }
  1815. /*
  1816. * Check for UPCI boards.
  1817. */
  1818. switch (dev->device) {
  1819. case PCI_DEVICE_ID_URP32INTF:
  1820. case PCI_DEVICE_ID_URP8INTF:
  1821. case PCI_DEVICE_ID_URP16INTF:
  1822. case PCI_DEVICE_ID_CRP16INTF:
  1823. case PCI_DEVICE_ID_URP8OCTA:
  1824. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1825. ConfigIO = pci_resource_start(dev, 1);
  1826. if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
  1827. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1828. /*
  1829. * Check for octa or quad cable.
  1830. */
  1831. if (!
  1832. (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
  1833. PCI_GPIO_CTRL_8PORT)) {
  1834. str = "Quadcable";
  1835. ports_per_aiop = 4;
  1836. rocketModel[i].numPorts = 4;
  1837. }
  1838. }
  1839. break;
  1840. case PCI_DEVICE_ID_UPCI_RM3_8PORT:
  1841. str = "8 ports";
  1842. max_num_aiops = 1;
  1843. rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
  1844. strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
  1845. rocketModel[i].numPorts = 8;
  1846. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1847. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1848. ConfigIO = pci_resource_start(dev, 1);
  1849. rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
  1850. break;
  1851. case PCI_DEVICE_ID_UPCI_RM3_4PORT:
  1852. str = "4 ports";
  1853. max_num_aiops = 1;
  1854. rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
  1855. strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
  1856. rocketModel[i].numPorts = 4;
  1857. rcktpt_io_addr[i] = pci_resource_start(dev, 2);
  1858. UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
  1859. ConfigIO = pci_resource_start(dev, 1);
  1860. rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
  1861. break;
  1862. default:
  1863. break;
  1864. }
  1865. switch (rcktpt_type[i]) {
  1866. case ROCKET_TYPE_MODEM:
  1867. board_type = "RocketModem";
  1868. break;
  1869. case ROCKET_TYPE_MODEMII:
  1870. board_type = "RocketModem II";
  1871. break;
  1872. case ROCKET_TYPE_MODEMIII:
  1873. board_type = "RocketModem III";
  1874. break;
  1875. default:
  1876. board_type = "RocketPort";
  1877. break;
  1878. }
  1879. if (fast_clock) {
  1880. sClockPrescale = 0x12; /* mod 2 (divide by 3) */
  1881. rp_baud_base[i] = 921600;
  1882. } else {
  1883. /*
  1884. * If support_low_speed is set, use the slow clock
  1885. * prescale, which supports 50 bps
  1886. */
  1887. if (support_low_speed) {
  1888. /* mod 9 (divide by 10) prescale */
  1889. sClockPrescale = 0x19;
  1890. rp_baud_base[i] = 230400;
  1891. } else {
  1892. /* mod 4 (devide by 5) prescale */
  1893. sClockPrescale = 0x14;
  1894. rp_baud_base[i] = 460800;
  1895. }
  1896. }
  1897. for (aiop = 0; aiop < max_num_aiops; aiop++)
  1898. aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
  1899. ctlp = sCtlNumToCtlPtr(i);
  1900. num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
  1901. for (aiop = 0; aiop < max_num_aiops; aiop++)
  1902. ctlp->AiopNumChan[aiop] = ports_per_aiop;
  1903. printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
  1904. "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
  1905. rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
  1906. printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
  1907. rocketModel[i].modelString,
  1908. rocketModel[i].startingPortNumber,
  1909. rocketModel[i].startingPortNumber +
  1910. rocketModel[i].numPorts - 1);
  1911. if (num_aiops <= 0) {
  1912. rcktpt_io_addr[i] = 0;
  1913. return (0);
  1914. }
  1915. is_PCI[i] = 1;
  1916. /* Reset the AIOPIC, init the serial ports */
  1917. for (aiop = 0; aiop < num_aiops; aiop++) {
  1918. sResetAiopByNum(ctlp, aiop);
  1919. num_chan = ports_per_aiop;
  1920. for (chan = 0; chan < num_chan; chan++)
  1921. init_r_port(i, aiop, chan, dev);
  1922. }
  1923. /* Rocket modems must be reset */
  1924. if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
  1925. (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
  1926. (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
  1927. num_chan = ports_per_aiop;
  1928. for (chan = 0; chan < num_chan; chan++)
  1929. sPCIModemReset(ctlp, chan, 1);
  1930. mdelay(500);
  1931. for (chan = 0; chan < num_chan; chan++)
  1932. sPCIModemReset(ctlp, chan, 0);
  1933. mdelay(500);
  1934. rmSpeakerReset(ctlp, rocketModel[i].model);
  1935. }
  1936. return (1);
  1937. }
  1938. /*
  1939. * Probes for PCI cards, inits them if found
  1940. * Input: board_found = number of ISA boards already found, or the
  1941. * starting board number
  1942. * Returns: Number of PCI boards found
  1943. */
  1944. static int __init init_PCI(int boards_found)
  1945. {
  1946. struct pci_dev *dev = NULL;
  1947. int count = 0;
  1948. /* Work through the PCI device list, pulling out ours */
  1949. while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
  1950. if (register_PCI(count + boards_found, dev))
  1951. count++;
  1952. }
  1953. return (count);
  1954. }
  1955. #endif /* CONFIG_PCI */
  1956. /*
  1957. * Probes for ISA cards
  1958. * Input: i = the board number to look for
  1959. * Returns: 1 if board found, 0 else
  1960. */
  1961. static int __init init_ISA(int i)
  1962. {
  1963. int num_aiops, num_chan = 0, total_num_chan = 0;
  1964. int aiop, chan;
  1965. unsigned int aiopio[MAX_AIOPS_PER_BOARD];
  1966. CONTROLLER_t *ctlp;
  1967. char *type_string;
  1968. /* If io_addr is zero, no board configured */
  1969. if (rcktpt_io_addr[i] == 0)
  1970. return (0);
  1971. /* Reserve the IO region */
  1972. if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
  1973. printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
  1974. rcktpt_io_addr[i] = 0;
  1975. return (0);
  1976. }
  1977. ctlp = sCtlNumToCtlPtr(i);
  1978. ctlp->boardType = rcktpt_type[i];
  1979. switch (rcktpt_type[i]) {
  1980. case ROCKET_TYPE_PC104:
  1981. type_string = "(PC104)";
  1982. break;
  1983. case ROCKET_TYPE_MODEM:
  1984. type_string = "(RocketModem)";
  1985. break;
  1986. case ROCKET_TYPE_MODEMII:
  1987. type_string = "(RocketModem II)";
  1988. break;
  1989. default:
  1990. type_string = "";
  1991. break;
  1992. }
  1993. /*
  1994. * If support_low_speed is set, use the slow clock prescale,
  1995. * which supports 50 bps
  1996. */
  1997. if (support_low_speed) {
  1998. sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
  1999. rp_baud_base[i] = 230400;
  2000. } else {
  2001. sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
  2002. rp_baud_base[i] = 460800;
  2003. }
  2004. for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
  2005. aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
  2006. num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
  2007. if (ctlp->boardType == ROCKET_TYPE_PC104) {
  2008. sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
  2009. sEnAiop(ctlp, 3); /* CSels used for other stuff */
  2010. }
  2011. /* If something went wrong initing the AIOP's release the ISA IO memory */
  2012. if (num_aiops <= 0) {
  2013. release_region(rcktpt_io_addr[i], 64);
  2014. rcktpt_io_addr[i] = 0;
  2015. return (0);
  2016. }
  2017. rocketModel[i].startingPortNumber = nextLineNumber;
  2018. for (aiop = 0; aiop < num_aiops; aiop++) {
  2019. sResetAiopByNum(ctlp, aiop);
  2020. sEnAiop(ctlp, aiop);
  2021. num_chan = sGetAiopNumChan(ctlp, aiop);
  2022. total_num_chan += num_chan;
  2023. for (chan = 0; chan < num_chan; chan++)
  2024. init_r_port(i, aiop, chan, NULL);
  2025. }
  2026. is_PCI[i] = 0;
  2027. if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
  2028. num_chan = sGetAiopNumChan(ctlp, 0);
  2029. total_num_chan = num_chan;
  2030. for (chan = 0; chan < num_chan; chan++)
  2031. sModemReset(ctlp, chan, 1);
  2032. mdelay(500);
  2033. for (chan = 0; chan < num_chan; chan++)
  2034. sModemReset(ctlp, chan, 0);
  2035. mdelay(500);
  2036. strcpy(rocketModel[i].modelString, "RocketModem ISA");
  2037. } else {
  2038. strcpy(rocketModel[i].modelString, "RocketPort ISA");
  2039. }
  2040. rocketModel[i].numPorts = total_num_chan;
  2041. rocketModel[i].model = MODEL_ISA;
  2042. printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
  2043. i, rcktpt_io_addr[i], num_aiops, type_string);
  2044. printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
  2045. rocketModel[i].modelString,
  2046. rocketModel[i].startingPortNumber,
  2047. rocketModel[i].startingPortNumber +
  2048. rocketModel[i].numPorts - 1);
  2049. return (1);
  2050. }
  2051. static const struct tty_operations rocket_ops = {
  2052. .open = rp_open,
  2053. .close = rp_close,
  2054. .write = rp_write,
  2055. .put_char = rp_put_char,
  2056. .write_room = rp_write_room,
  2057. .chars_in_buffer = rp_chars_in_buffer,
  2058. .flush_buffer = rp_flush_buffer,
  2059. .ioctl = rp_ioctl,
  2060. .throttle = rp_throttle,
  2061. .unthrottle = rp_unthrottle,
  2062. .set_termios = rp_set_termios,
  2063. .stop = rp_stop,
  2064. .start = rp_start,
  2065. .hangup = rp_hangup,
  2066. .break_ctl = rp_break,
  2067. .send_xchar = rp_send_xchar,
  2068. .wait_until_sent = rp_wait_until_sent,
  2069. .tiocmget = rp_tiocmget,
  2070. .tiocmset = rp_tiocmset,
  2071. };
  2072. /*
  2073. * The module "startup" routine; it's run when the module is loaded.
  2074. */
  2075. static int __init rp_init(void)
  2076. {
  2077. int retval, pci_boards_found, isa_boards_found, i;
  2078. printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
  2079. ROCKET_VERSION, ROCKET_DATE);
  2080. rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
  2081. if (!rocket_driver)
  2082. return -ENOMEM;
  2083. /*
  2084. * Initialize the array of pointers to our own internal state
  2085. * structures.
  2086. */
  2087. memset(rp_table, 0, sizeof (rp_table));
  2088. memset(xmit_flags, 0, sizeof (xmit_flags));
  2089. for (i = 0; i < MAX_RP_PORTS; i++)
  2090. lineNumbers[i] = 0;
  2091. nextLineNumber = 0;
  2092. memset(rocketModel, 0, sizeof (rocketModel));
  2093. /*
  2094. * If board 1 is non-zero, there is at least one ISA configured. If controller is
  2095. * zero, use the default controller IO address of board1 + 0x40.
  2096. */
  2097. if (board1) {
  2098. if (controller == 0)
  2099. controller = board1 + 0x40;
  2100. } else {
  2101. controller = 0; /* Used as a flag, meaning no ISA boards */
  2102. }
  2103. /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
  2104. if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
  2105. printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
  2106. return -EBUSY;
  2107. }
  2108. /* Store ISA variable retrieved from command line or .conf file. */
  2109. rcktpt_io_addr[0] = board1;
  2110. rcktpt_io_addr[1] = board2;
  2111. rcktpt_io_addr[2] = board3;
  2112. rcktpt_io_addr[3] = board4;
  2113. rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2114. rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
  2115. rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2116. rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
  2117. rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2118. rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
  2119. rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
  2120. rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
  2121. /*
  2122. * Set up the tty driver structure and then register this
  2123. * driver with the tty layer.
  2124. */
  2125. rocket_driver->owner = THIS_MODULE;
  2126. rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
  2127. rocket_driver->name = "ttyR";
  2128. rocket_driver->driver_name = "Comtrol RocketPort";
  2129. rocket_driver->major = TTY_ROCKET_MAJOR;
  2130. rocket_driver->minor_start = 0;
  2131. rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2132. rocket_driver->subtype = SERIAL_TYPE_NORMAL;
  2133. rocket_driver->init_termios = tty_std_termios;
  2134. rocket_driver->init_termios.c_cflag =
  2135. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2136. rocket_driver->init_termios.c_ispeed = 9600;
  2137. rocket_driver->init_termios.c_ospeed = 9600;
  2138. #ifdef ROCKET_SOFT_FLOW
  2139. rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
  2140. #endif
  2141. tty_set_operations(rocket_driver, &rocket_ops);
  2142. retval = tty_register_driver(rocket_driver);
  2143. if (retval < 0) {
  2144. printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
  2145. put_tty_driver(rocket_driver);
  2146. return -1;
  2147. }
  2148. #ifdef ROCKET_DEBUG_OPEN
  2149. printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
  2150. #endif
  2151. /*
  2152. * OK, let's probe each of the controllers looking for boards. Any boards found
  2153. * will be initialized here.
  2154. */
  2155. isa_boards_found = 0;
  2156. pci_boards_found = 0;
  2157. for (i = 0; i < NUM_BOARDS; i++) {
  2158. if (init_ISA(i))
  2159. isa_boards_found++;
  2160. }
  2161. #ifdef CONFIG_PCI
  2162. if (isa_boards_found < NUM_BOARDS)
  2163. pci_boards_found = init_PCI(isa_boards_found);
  2164. #endif
  2165. max_board = pci_boards_found + isa_boards_found;
  2166. if (max_board == 0) {
  2167. printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
  2168. del_timer_sync(&rocket_timer);
  2169. tty_unregister_driver(rocket_driver);
  2170. put_tty_driver(rocket_driver);
  2171. return -ENXIO;
  2172. }
  2173. return 0;
  2174. }
  2175. static void rp_cleanup_module(void)
  2176. {
  2177. int retval;
  2178. int i;
  2179. del_timer_sync(&rocket_timer);
  2180. retval = tty_unregister_driver(rocket_driver);
  2181. if (retval)
  2182. printk(KERN_INFO "Error %d while trying to unregister "
  2183. "rocketport driver\n", -retval);
  2184. put_tty_driver(rocket_driver);
  2185. for (i = 0; i < MAX_RP_PORTS; i++)
  2186. kfree(rp_table[i]);
  2187. for (i = 0; i < NUM_BOARDS; i++) {
  2188. if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
  2189. continue;
  2190. release_region(rcktpt_io_addr[i], 64);
  2191. }
  2192. if (controller)
  2193. release_region(controller, 4);
  2194. }
  2195. /***************************************************************************
  2196. Function: sInitController
  2197. Purpose: Initialization of controller global registers and controller
  2198. structure.
  2199. Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
  2200. IRQNum,Frequency,PeriodicOnly)
  2201. CONTROLLER_T *CtlP; Ptr to controller structure
  2202. int CtlNum; Controller number
  2203. ByteIO_t MudbacIO; Mudbac base I/O address.
  2204. ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
  2205. This list must be in the order the AIOPs will be found on the
  2206. controller. Once an AIOP in the list is not found, it is
  2207. assumed that there are no more AIOPs on the controller.
  2208. int AiopIOListSize; Number of addresses in AiopIOList
  2209. int IRQNum; Interrupt Request number. Can be any of the following:
  2210. 0: Disable global interrupts
  2211. 3: IRQ 3
  2212. 4: IRQ 4
  2213. 5: IRQ 5
  2214. 9: IRQ 9
  2215. 10: IRQ 10
  2216. 11: IRQ 11
  2217. 12: IRQ 12
  2218. 15: IRQ 15
  2219. Byte_t Frequency: A flag identifying the frequency
  2220. of the periodic interrupt, can be any one of the following:
  2221. FREQ_DIS - periodic interrupt disabled
  2222. FREQ_137HZ - 137 Hertz
  2223. FREQ_69HZ - 69 Hertz
  2224. FREQ_34HZ - 34 Hertz
  2225. FREQ_17HZ - 17 Hertz
  2226. FREQ_9HZ - 9 Hertz
  2227. FREQ_4HZ - 4 Hertz
  2228. If IRQNum is set to 0 the Frequency parameter is
  2229. overidden, it is forced to a value of FREQ_DIS.
  2230. int PeriodicOnly: 1 if all interrupts except the periodic
  2231. interrupt are to be blocked.
  2232. 0 is both the periodic interrupt and
  2233. other channel interrupts are allowed.
  2234. If IRQNum is set to 0 the PeriodicOnly parameter is
  2235. overidden, it is forced to a value of 0.
  2236. Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
  2237. initialization failed.
  2238. Comments:
  2239. If periodic interrupts are to be disabled but AIOP interrupts
  2240. are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
  2241. If interrupts are to be completely disabled set IRQNum to 0.
  2242. Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
  2243. invalid combination.
  2244. This function performs initialization of global interrupt modes,
  2245. but it does not actually enable global interrupts. To enable
  2246. and disable global interrupts use functions sEnGlobalInt() and
  2247. sDisGlobalInt(). Enabling of global interrupts is normally not
  2248. done until all other initializations are complete.
  2249. Even if interrupts are globally enabled, they must also be
  2250. individually enabled for each channel that is to generate
  2251. interrupts.
  2252. Warnings: No range checking on any of the parameters is done.
  2253. No context switches are allowed while executing this function.
  2254. After this function all AIOPs on the controller are disabled,
  2255. they can be enabled with sEnAiop().
  2256. */
  2257. static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
  2258. ByteIO_t * AiopIOList, int AiopIOListSize,
  2259. int IRQNum, Byte_t Frequency, int PeriodicOnly)
  2260. {
  2261. int i;
  2262. ByteIO_t io;
  2263. int done;
  2264. CtlP->AiopIntrBits = aiop_intr_bits;
  2265. CtlP->AltChanRingIndicator = 0;
  2266. CtlP->CtlNum = CtlNum;
  2267. CtlP->CtlID = CTLID_0001; /* controller release 1 */
  2268. CtlP->BusType = isISA;
  2269. CtlP->MBaseIO = MudbacIO;
  2270. CtlP->MReg1IO = MudbacIO + 1;
  2271. CtlP->MReg2IO = MudbacIO + 2;
  2272. CtlP->MReg3IO = MudbacIO + 3;
  2273. #if 1
  2274. CtlP->MReg2 = 0; /* interrupt disable */
  2275. CtlP->MReg3 = 0; /* no periodic interrupts */
  2276. #else
  2277. if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
  2278. CtlP->MReg2 = 0; /* interrupt disable */
  2279. CtlP->MReg3 = 0; /* no periodic interrupts */
  2280. } else {
  2281. CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
  2282. CtlP->MReg3 = Frequency; /* set frequency */
  2283. if (PeriodicOnly) { /* periodic interrupt only */
  2284. CtlP->MReg3 |= PERIODIC_ONLY;
  2285. }
  2286. }
  2287. #endif
  2288. sOutB(CtlP->MReg2IO, CtlP->MReg2);
  2289. sOutB(CtlP->MReg3IO, CtlP->MReg3);
  2290. sControllerEOI(CtlP); /* clear EOI if warm init */
  2291. /* Init AIOPs */
  2292. CtlP->NumAiop = 0;
  2293. for (i = done = 0; i < AiopIOListSize; i++) {
  2294. io = AiopIOList[i];
  2295. CtlP->AiopIO[i] = (WordIO_t) io;
  2296. CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
  2297. sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
  2298. sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
  2299. if (done)
  2300. continue;
  2301. sEnAiop(CtlP, i); /* enable the AIOP */
  2302. CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
  2303. if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
  2304. done = 1; /* done looking for AIOPs */
  2305. else {
  2306. CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
  2307. sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
  2308. sOutB(io + _INDX_DATA, sClockPrescale);
  2309. CtlP->NumAiop++; /* bump count of AIOPs */
  2310. }
  2311. sDisAiop(CtlP, i); /* disable AIOP */
  2312. }
  2313. if (CtlP->NumAiop == 0)
  2314. return (-1);
  2315. else
  2316. return (CtlP->NumAiop);
  2317. }
  2318. /***************************************************************************
  2319. Function: sPCIInitController
  2320. Purpose: Initialization of controller global registers and controller
  2321. structure.
  2322. Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
  2323. IRQNum,Frequency,PeriodicOnly)
  2324. CONTROLLER_T *CtlP; Ptr to controller structure
  2325. int CtlNum; Controller number
  2326. ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
  2327. This list must be in the order the AIOPs will be found on the
  2328. controller. Once an AIOP in the list is not found, it is
  2329. assumed that there are no more AIOPs on the controller.
  2330. int AiopIOListSize; Number of addresses in AiopIOList
  2331. int IRQNum; Interrupt Request number. Can be any of the following:
  2332. 0: Disable global interrupts
  2333. 3: IRQ 3
  2334. 4: IRQ 4
  2335. 5: IRQ 5
  2336. 9: IRQ 9
  2337. 10: IRQ 10
  2338. 11: IRQ 11
  2339. 12: IRQ 12
  2340. 15: IRQ 15
  2341. Byte_t Frequency: A flag identifying the frequency
  2342. of the periodic interrupt, can be any one of the following:
  2343. FREQ_DIS - periodic interrupt disabled
  2344. FREQ_137HZ - 137 Hertz
  2345. FREQ_69HZ - 69 Hertz
  2346. FREQ_34HZ - 34 Hertz
  2347. FREQ_17HZ - 17 Hertz
  2348. FREQ_9HZ - 9 Hertz
  2349. FREQ_4HZ - 4 Hertz
  2350. If IRQNum is set to 0 the Frequency parameter is
  2351. overidden, it is forced to a value of FREQ_DIS.
  2352. int PeriodicOnly: 1 if all interrupts except the periodic
  2353. interrupt are to be blocked.
  2354. 0 is both the periodic interrupt and
  2355. other channel interrupts are allowed.
  2356. If IRQNum is set to 0 the PeriodicOnly parameter is
  2357. overidden, it is forced to a value of 0.
  2358. Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
  2359. initialization failed.
  2360. Comments:
  2361. If periodic interrupts are to be disabled but AIOP interrupts
  2362. are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
  2363. If interrupts are to be completely disabled set IRQNum to 0.
  2364. Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
  2365. invalid combination.
  2366. This function performs initialization of global interrupt modes,
  2367. but it does not actually enable global interrupts. To enable
  2368. and disable global interrupts use functions sEnGlobalInt() and
  2369. sDisGlobalInt(). Enabling of global interrupts is normally not
  2370. done until all other initializations are complete.
  2371. Even if interrupts are globally enabled, they must also be
  2372. individually enabled for each channel that is to generate
  2373. interrupts.
  2374. Warnings: No range checking on any of the parameters is done.
  2375. No context switches are allowed while executing this function.
  2376. After this function all AIOPs on the controller are disabled,
  2377. they can be enabled with sEnAiop().
  2378. */
  2379. static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
  2380. ByteIO_t * AiopIOList, int AiopIOListSize,
  2381. WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
  2382. int PeriodicOnly, int altChanRingIndicator,
  2383. int UPCIRingInd)
  2384. {
  2385. int i;
  2386. ByteIO_t io;
  2387. CtlP->AltChanRingIndicator = altChanRingIndicator;
  2388. CtlP->UPCIRingInd = UPCIRingInd;
  2389. CtlP->CtlNum = CtlNum;
  2390. CtlP->CtlID = CTLID_0001; /* controller release 1 */
  2391. CtlP->BusType = isPCI; /* controller release 1 */
  2392. if (ConfigIO) {
  2393. CtlP->isUPCI = 1;
  2394. CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
  2395. CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
  2396. CtlP->AiopIntrBits = upci_aiop_intr_bits;
  2397. } else {
  2398. CtlP->isUPCI = 0;
  2399. CtlP->PCIIO =
  2400. (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
  2401. CtlP->AiopIntrBits = aiop_intr_bits;
  2402. }
  2403. sPCIControllerEOI(CtlP); /* clear EOI if warm init */
  2404. /* Init AIOPs */
  2405. CtlP->NumAiop = 0;
  2406. for (i = 0; i < AiopIOListSize; i++) {
  2407. io = AiopIOList[i];
  2408. CtlP->AiopIO[i] = (WordIO_t) io;
  2409. CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
  2410. CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
  2411. if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
  2412. break; /* done looking for AIOPs */
  2413. CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
  2414. sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
  2415. sOutB(io + _INDX_DATA, sClockPrescale);
  2416. CtlP->NumAiop++; /* bump count of AIOPs */
  2417. }
  2418. if (CtlP->NumAiop == 0)
  2419. return (-1);
  2420. else
  2421. return (CtlP->NumAiop);
  2422. }
  2423. /***************************************************************************
  2424. Function: sReadAiopID
  2425. Purpose: Read the AIOP idenfication number directly from an AIOP.
  2426. Call: sReadAiopID(io)
  2427. ByteIO_t io: AIOP base I/O address
  2428. Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
  2429. is replace by an identifying number.
  2430. Flag AIOPID_NULL if no valid AIOP is found
  2431. Warnings: No context switches are allowed while executing this function.
  2432. */
  2433. static int sReadAiopID(ByteIO_t io)
  2434. {
  2435. Byte_t AiopID; /* ID byte from AIOP */
  2436. sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
  2437. sOutB(io + _CMD_REG, 0x0);
  2438. AiopID = sInW(io + _CHN_STAT0) & 0x07;
  2439. if (AiopID == 0x06)
  2440. return (1);
  2441. else /* AIOP does not exist */
  2442. return (-1);
  2443. }
  2444. /***************************************************************************
  2445. Function: sReadAiopNumChan
  2446. Purpose: Read the number of channels available in an AIOP directly from
  2447. an AIOP.
  2448. Call: sReadAiopNumChan(io)
  2449. WordIO_t io: AIOP base I/O address
  2450. Return: int: The number of channels available
  2451. Comments: The number of channels is determined by write/reads from identical
  2452. offsets within the SRAM address spaces for channels 0 and 4.
  2453. If the channel 4 space is mirrored to channel 0 it is a 4 channel
  2454. AIOP, otherwise it is an 8 channel.
  2455. Warnings: No context switches are allowed while executing this function.
  2456. */
  2457. static int sReadAiopNumChan(WordIO_t io)
  2458. {
  2459. Word_t x;
  2460. static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
  2461. /* write to chan 0 SRAM */
  2462. sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
  2463. sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
  2464. x = sInW(io + _INDX_DATA);
  2465. sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
  2466. if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
  2467. return (8);
  2468. else
  2469. return (4);
  2470. }
  2471. /***************************************************************************
  2472. Function: sInitChan
  2473. Purpose: Initialization of a channel and channel structure
  2474. Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
  2475. CONTROLLER_T *CtlP; Ptr to controller structure
  2476. CHANNEL_T *ChP; Ptr to channel structure
  2477. int AiopNum; AIOP number within controller
  2478. int ChanNum; Channel number within AIOP
  2479. Return: int: 1 if initialization succeeded, 0 if it fails because channel
  2480. number exceeds number of channels available in AIOP.
  2481. Comments: This function must be called before a channel can be used.
  2482. Warnings: No range checking on any of the parameters is done.
  2483. No context switches are allowed while executing this function.
  2484. */
  2485. static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
  2486. int ChanNum)
  2487. {
  2488. int i;
  2489. WordIO_t AiopIO;
  2490. WordIO_t ChIOOff;
  2491. Byte_t *ChR;
  2492. Word_t ChOff;
  2493. static Byte_t R[4];
  2494. int brd9600;
  2495. if (ChanNum >= CtlP->AiopNumChan[AiopNum])
  2496. return 0; /* exceeds num chans in AIOP */
  2497. /* Channel, AIOP, and controller identifiers */
  2498. ChP->CtlP = CtlP;
  2499. ChP->ChanID = CtlP->AiopID[AiopNum];
  2500. ChP->AiopNum = AiopNum;
  2501. ChP->ChanNum = ChanNum;
  2502. /* Global direct addresses */
  2503. AiopIO = CtlP->AiopIO[AiopNum];
  2504. ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
  2505. ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
  2506. ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
  2507. ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
  2508. ChP->IndexData = AiopIO + _INDX_DATA;
  2509. /* Channel direct addresses */
  2510. ChIOOff = AiopIO + ChP->ChanNum * 2;
  2511. ChP->TxRxData = ChIOOff + _TD0;
  2512. ChP->ChanStat = ChIOOff + _CHN_STAT0;
  2513. ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
  2514. ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
  2515. /* Initialize the channel from the RData array */
  2516. for (i = 0; i < RDATASIZE; i += 4) {
  2517. R[0] = RData[i];
  2518. R[1] = RData[i + 1] + 0x10 * ChanNum;
  2519. R[2] = RData[i + 2];
  2520. R[3] = RData[i + 3];
  2521. sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
  2522. }
  2523. ChR = ChP->R;
  2524. for (i = 0; i < RREGDATASIZE; i += 4) {
  2525. ChR[i] = RRegData[i];
  2526. ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
  2527. ChR[i + 2] = RRegData[i + 2];
  2528. ChR[i + 3] = RRegData[i + 3];
  2529. }
  2530. /* Indexed registers */
  2531. ChOff = (Word_t) ChanNum *0x1000;
  2532. if (sClockPrescale == 0x14)
  2533. brd9600 = 47;
  2534. else
  2535. brd9600 = 23;
  2536. ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
  2537. ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
  2538. ChP->BaudDiv[2] = (Byte_t) brd9600;
  2539. ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
  2540. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
  2541. ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
  2542. ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
  2543. ChP->TxControl[2] = 0;
  2544. ChP->TxControl[3] = 0;
  2545. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
  2546. ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
  2547. ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
  2548. ChP->RxControl[2] = 0;
  2549. ChP->RxControl[3] = 0;
  2550. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
  2551. ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
  2552. ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
  2553. ChP->TxEnables[2] = 0;
  2554. ChP->TxEnables[3] = 0;
  2555. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
  2556. ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
  2557. ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
  2558. ChP->TxCompare[2] = 0;
  2559. ChP->TxCompare[3] = 0;
  2560. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
  2561. ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
  2562. ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
  2563. ChP->TxReplace1[2] = 0;
  2564. ChP->TxReplace1[3] = 0;
  2565. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
  2566. ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
  2567. ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
  2568. ChP->TxReplace2[2] = 0;
  2569. ChP->TxReplace2[3] = 0;
  2570. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
  2571. ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
  2572. ChP->TxFIFO = ChOff + _TX_FIFO;
  2573. sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
  2574. sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
  2575. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  2576. sOutW(ChP->IndexData, 0);
  2577. ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
  2578. ChP->RxFIFO = ChOff + _RX_FIFO;
  2579. sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
  2580. sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
  2581. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
  2582. sOutW(ChP->IndexData, 0);
  2583. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  2584. sOutW(ChP->IndexData, 0);
  2585. ChP->TxPrioCnt = ChOff + _TXP_CNT;
  2586. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
  2587. sOutB(ChP->IndexData, 0);
  2588. ChP->TxPrioPtr = ChOff + _TXP_PNTR;
  2589. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
  2590. sOutB(ChP->IndexData, 0);
  2591. ChP->TxPrioBuf = ChOff + _TXP_BUF;
  2592. sEnRxProcessor(ChP); /* start the Rx processor */
  2593. return 1;
  2594. }
  2595. /***************************************************************************
  2596. Function: sStopRxProcessor
  2597. Purpose: Stop the receive processor from processing a channel.
  2598. Call: sStopRxProcessor(ChP)
  2599. CHANNEL_T *ChP; Ptr to channel structure
  2600. Comments: The receive processor can be started again with sStartRxProcessor().
  2601. This function causes the receive processor to skip over the
  2602. stopped channel. It does not stop it from processing other channels.
  2603. Warnings: No context switches are allowed while executing this function.
  2604. Do not leave the receive processor stopped for more than one
  2605. character time.
  2606. After calling this function a delay of 4 uS is required to ensure
  2607. that the receive processor is no longer processing this channel.
  2608. */
  2609. static void sStopRxProcessor(CHANNEL_T * ChP)
  2610. {
  2611. Byte_t R[4];
  2612. R[0] = ChP->R[0];
  2613. R[1] = ChP->R[1];
  2614. R[2] = 0x0a;
  2615. R[3] = ChP->R[3];
  2616. sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
  2617. }
  2618. /***************************************************************************
  2619. Function: sFlushRxFIFO
  2620. Purpose: Flush the Rx FIFO
  2621. Call: sFlushRxFIFO(ChP)
  2622. CHANNEL_T *ChP; Ptr to channel structure
  2623. Return: void
  2624. Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  2625. while it is being flushed the receive processor is stopped
  2626. and the transmitter is disabled. After these operations a
  2627. 4 uS delay is done before clearing the pointers to allow
  2628. the receive processor to stop. These items are handled inside
  2629. this function.
  2630. Warnings: No context switches are allowed while executing this function.
  2631. */
  2632. static void sFlushRxFIFO(CHANNEL_T * ChP)
  2633. {
  2634. int i;
  2635. Byte_t Ch; /* channel number within AIOP */
  2636. int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
  2637. if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
  2638. return; /* don't need to flush */
  2639. RxFIFOEnabled = 0;
  2640. if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
  2641. RxFIFOEnabled = 1;
  2642. sDisRxFIFO(ChP); /* disable it */
  2643. for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
  2644. sInB(ChP->IntChan); /* depends on bus i/o timing */
  2645. }
  2646. sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
  2647. Ch = (Byte_t) sGetChanNum(ChP);
  2648. sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
  2649. sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
  2650. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
  2651. sOutW(ChP->IndexData, 0);
  2652. sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
  2653. sOutW(ChP->IndexData, 0);
  2654. if (RxFIFOEnabled)
  2655. sEnRxFIFO(ChP); /* enable Rx FIFO */
  2656. }
  2657. /***************************************************************************
  2658. Function: sFlushTxFIFO
  2659. Purpose: Flush the Tx FIFO
  2660. Call: sFlushTxFIFO(ChP)
  2661. CHANNEL_T *ChP; Ptr to channel structure
  2662. Return: void
  2663. Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
  2664. while it is being flushed the receive processor is stopped
  2665. and the transmitter is disabled. After these operations a
  2666. 4 uS delay is done before clearing the pointers to allow
  2667. the receive processor to stop. These items are handled inside
  2668. this function.
  2669. Warnings: No context switches are allowed while executing this function.
  2670. */
  2671. static void sFlushTxFIFO(CHANNEL_T * ChP)
  2672. {
  2673. int i;
  2674. Byte_t Ch; /* channel number within AIOP */
  2675. int TxEnabled; /* 1 if transmitter enabled */
  2676. if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
  2677. return; /* don't need to flush */
  2678. TxEnabled = 0;
  2679. if (ChP->TxControl[3] & TX_ENABLE) {
  2680. TxEnabled = 1;
  2681. sDisTransmit(ChP); /* disable transmitter */
  2682. }
  2683. sStopRxProcessor(ChP); /* stop Rx processor */
  2684. for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
  2685. sInB(ChP->IntChan); /* depends on bus i/o timing */
  2686. Ch = (Byte_t) sGetChanNum(ChP);
  2687. sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
  2688. sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
  2689. sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
  2690. sOutW(ChP->IndexData, 0);
  2691. if (TxEnabled)
  2692. sEnTransmit(ChP); /* enable transmitter */
  2693. sStartRxProcessor(ChP); /* restart Rx processor */
  2694. }
  2695. /***************************************************************************
  2696. Function: sWriteTxPrioByte
  2697. Purpose: Write a byte of priority transmit data to a channel
  2698. Call: sWriteTxPrioByte(ChP,Data)
  2699. CHANNEL_T *ChP; Ptr to channel structure
  2700. Byte_t Data; The transmit data byte
  2701. Return: int: 1 if the bytes is successfully written, otherwise 0.
  2702. Comments: The priority byte is transmitted before any data in the Tx FIFO.
  2703. Warnings: No context switches are allowed while executing this function.
  2704. */
  2705. static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
  2706. {
  2707. Byte_t DWBuf[4]; /* buffer for double word writes */
  2708. Word_t *WordPtr; /* must be far because Win SS != DS */
  2709. register DWordIO_t IndexAddr;
  2710. if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
  2711. IndexAddr = ChP->IndexAddr;
  2712. sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
  2713. if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
  2714. return (0); /* nothing sent */
  2715. WordPtr = (Word_t *) (&DWBuf[0]);
  2716. *WordPtr = ChP->TxPrioBuf; /* data byte address */
  2717. DWBuf[2] = Data; /* data byte value */
  2718. sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
  2719. *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
  2720. DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
  2721. DWBuf[3] = 0; /* priority buffer pointer */
  2722. sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
  2723. } else { /* write it to Tx FIFO */
  2724. sWriteTxByte(sGetTxRxDataIO(ChP), Data);
  2725. }
  2726. return (1); /* 1 byte sent */
  2727. }
  2728. /***************************************************************************
  2729. Function: sEnInterrupts
  2730. Purpose: Enable one or more interrupts for a channel
  2731. Call: sEnInterrupts(ChP,Flags)
  2732. CHANNEL_T *ChP; Ptr to channel structure
  2733. Word_t Flags: Interrupt enable flags, can be any combination
  2734. of the following flags:
  2735. TXINT_EN: Interrupt on Tx FIFO empty
  2736. RXINT_EN: Interrupt on Rx FIFO at trigger level (see
  2737. sSetRxTrigger())
  2738. SRCINT_EN: Interrupt on SRC (Special Rx Condition)
  2739. MCINT_EN: Interrupt on modem input change
  2740. CHANINT_EN: Allow channel interrupt signal to the AIOP's
  2741. Interrupt Channel Register.
  2742. Return: void
  2743. Comments: If an interrupt enable flag is set in Flags, that interrupt will be
  2744. enabled. If an interrupt enable flag is not set in Flags, that
  2745. interrupt will not be changed. Interrupts can be disabled with
  2746. function sDisInterrupts().
  2747. This function sets the appropriate bit for the channel in the AIOP's
  2748. Interrupt Mask Register if the CHANINT_EN flag is set. This allows
  2749. this channel's bit to be set in the AIOP's Interrupt Channel Register.
  2750. Interrupts must also be globally enabled before channel interrupts
  2751. will be passed on to the host. This is done with function
  2752. sEnGlobalInt().
  2753. In some cases it may be desirable to disable interrupts globally but
  2754. enable channel interrupts. This would allow the global interrupt
  2755. status register to be used to determine which AIOPs need service.
  2756. */
  2757. static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
  2758. {
  2759. Byte_t Mask; /* Interrupt Mask Register */
  2760. ChP->RxControl[2] |=
  2761. ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  2762. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
  2763. ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
  2764. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
  2765. if (Flags & CHANINT_EN) {
  2766. Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
  2767. sOutB(ChP->IntMask, Mask);
  2768. }
  2769. }
  2770. /***************************************************************************
  2771. Function: sDisInterrupts
  2772. Purpose: Disable one or more interrupts for a channel
  2773. Call: sDisInterrupts(ChP,Flags)
  2774. CHANNEL_T *ChP; Ptr to channel structure
  2775. Word_t Flags: Interrupt flags, can be any combination
  2776. of the following flags:
  2777. TXINT_EN: Interrupt on Tx FIFO empty
  2778. RXINT_EN: Interrupt on Rx FIFO at trigger level (see
  2779. sSetRxTrigger())
  2780. SRCINT_EN: Interrupt on SRC (Special Rx Condition)
  2781. MCINT_EN: Interrupt on modem input change
  2782. CHANINT_EN: Disable channel interrupt signal to the
  2783. AIOP's Interrupt Channel Register.
  2784. Return: void
  2785. Comments: If an interrupt flag is set in Flags, that interrupt will be
  2786. disabled. If an interrupt flag is not set in Flags, that
  2787. interrupt will not be changed. Interrupts can be enabled with
  2788. function sEnInterrupts().
  2789. This function clears the appropriate bit for the channel in the AIOP's
  2790. Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
  2791. this channel's bit from being set in the AIOP's Interrupt Channel
  2792. Register.
  2793. */
  2794. static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
  2795. {
  2796. Byte_t Mask; /* Interrupt Mask Register */
  2797. ChP->RxControl[2] &=
  2798. ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
  2799. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
  2800. ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
  2801. sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
  2802. if (Flags & CHANINT_EN) {
  2803. Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
  2804. sOutB(ChP->IntMask, Mask);
  2805. }
  2806. }
  2807. static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
  2808. {
  2809. sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
  2810. }
  2811. /*
  2812. * Not an official SSCI function, but how to reset RocketModems.
  2813. * ISA bus version
  2814. */
  2815. static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
  2816. {
  2817. ByteIO_t addr;
  2818. Byte_t val;
  2819. addr = CtlP->AiopIO[0] + 0x400;
  2820. val = sInB(CtlP->MReg3IO);
  2821. /* if AIOP[1] is not enabled, enable it */
  2822. if ((val & 2) == 0) {
  2823. val = sInB(CtlP->MReg2IO);
  2824. sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
  2825. sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
  2826. }
  2827. sEnAiop(CtlP, 1);
  2828. if (!on)
  2829. addr += 8;
  2830. sOutB(addr + chan, 0); /* apply or remove reset */
  2831. sDisAiop(CtlP, 1);
  2832. }
  2833. /*
  2834. * Not an official SSCI function, but how to reset RocketModems.
  2835. * PCI bus version
  2836. */
  2837. static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
  2838. {
  2839. ByteIO_t addr;
  2840. addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
  2841. if (!on)
  2842. addr += 8;
  2843. sOutB(addr + chan, 0); /* apply or remove reset */
  2844. }
  2845. /* Resets the speaker controller on RocketModem II and III devices */
  2846. static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
  2847. {
  2848. ByteIO_t addr;
  2849. /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
  2850. if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
  2851. addr = CtlP->AiopIO[0] + 0x4F;
  2852. sOutB(addr, 0);
  2853. }
  2854. /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
  2855. if ((model == MODEL_UPCI_RM3_8PORT)
  2856. || (model == MODEL_UPCI_RM3_4PORT)) {
  2857. addr = CtlP->AiopIO[0] + 0x88;
  2858. sOutB(addr, 0);
  2859. }
  2860. }
  2861. /* Returns the line number given the controller (board), aiop and channel number */
  2862. static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
  2863. {
  2864. return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
  2865. }
  2866. /*
  2867. * Stores the line number associated with a given controller (board), aiop
  2868. * and channel number.
  2869. * Returns: The line number assigned
  2870. */
  2871. static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
  2872. {
  2873. lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
  2874. return (nextLineNumber - 1);
  2875. }