riscom8_reg.h 12 KB

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  1. /*
  2. * linux/drivers/char/riscom8_reg.h -- RISCom/8 multiport serial driver.
  3. */
  4. /*
  5. * Definitions for RISCom/8 Async Mux card by SDL Communications, Inc.
  6. */
  7. /*
  8. * Address mapping between Cirrus Logic CD180 chip internal registers
  9. * and ISA port addresses:
  10. *
  11. * CL-CD180 A6 A5 A4 A3 A2 A1 A0
  12. * ISA A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
  13. */
  14. #define RC_TO_ISA(r) ((((r)&0x07)<<1) | (((r)&~0x07)<<7))
  15. /* RISCom/8 On-Board Registers (assuming address translation) */
  16. #define RC_RI 0x100 /* Ring Indicator Register (R/O) */
  17. #define RC_DTR 0x100 /* DTR Register (W/O) */
  18. #define RC_BSR 0x101 /* Board Status Register (R/O) */
  19. #define RC_CTOUT 0x101 /* Clear Timeout (W/O) */
  20. /* Board Status Register */
  21. #define RC_BSR_TOUT 0x08 /* Hardware Timeout */
  22. #define RC_BSR_RINT 0x04 /* Receiver Interrupt */
  23. #define RC_BSR_TINT 0x02 /* Transmitter Interrupt */
  24. #define RC_BSR_MINT 0x01 /* Modem Ctl Interrupt */
  25. /* On-board oscillator frequency (in Hz) */
  26. #define RC_OSCFREQ 9830400
  27. /* Values of choice for Interrupt ACKs */
  28. #define RC_ACK_MINT 0x81 /* goes to PILR1 */
  29. #define RC_ACK_RINT 0x82 /* goes to PILR3 */
  30. #define RC_ACK_TINT 0x84 /* goes to PILR2 */
  31. /* Chip ID (sorry, only one chip now) */
  32. #define RC_ID 0x10
  33. /* Definitions for Cirrus Logic CL-CD180 8-port async mux chip */
  34. #define CD180_NCH 8 /* Total number of channels */
  35. #define CD180_TPC 16 /* Ticks per character */
  36. #define CD180_NFIFO 8 /* TX FIFO size */
  37. /* Global registers */
  38. #define CD180_GIVR 0x40 /* Global Interrupt Vector Register */
  39. #define CD180_GICR 0x41 /* Global Interrupting Channel Register */
  40. #define CD180_PILR1 0x61 /* Priority Interrupt Level Register 1 */
  41. #define CD180_PILR2 0x62 /* Priority Interrupt Level Register 2 */
  42. #define CD180_PILR3 0x63 /* Priority Interrupt Level Register 3 */
  43. #define CD180_CAR 0x64 /* Channel Access Register */
  44. #define CD180_GFRCR 0x6b /* Global Firmware Revision Code Register */
  45. #define CD180_PPRH 0x70 /* Prescaler Period Register High */
  46. #define CD180_PPRL 0x71 /* Prescaler Period Register Low */
  47. #define CD180_RDR 0x78 /* Receiver Data Register */
  48. #define CD180_RCSR 0x7a /* Receiver Character Status Register */
  49. #define CD180_TDR 0x7b /* Transmit Data Register */
  50. #define CD180_EOIR 0x7f /* End of Interrupt Register */
  51. /* Channel Registers */
  52. #define CD180_CCR 0x01 /* Channel Command Register */
  53. #define CD180_IER 0x02 /* Interrupt Enable Register */
  54. #define CD180_COR1 0x03 /* Channel Option Register 1 */
  55. #define CD180_COR2 0x04 /* Channel Option Register 2 */
  56. #define CD180_COR3 0x05 /* Channel Option Register 3 */
  57. #define CD180_CCSR 0x06 /* Channel Control Status Register */
  58. #define CD180_RDCR 0x07 /* Receive Data Count Register */
  59. #define CD180_SCHR1 0x09 /* Special Character Register 1 */
  60. #define CD180_SCHR2 0x0a /* Special Character Register 2 */
  61. #define CD180_SCHR3 0x0b /* Special Character Register 3 */
  62. #define CD180_SCHR4 0x0c /* Special Character Register 4 */
  63. #define CD180_MCOR1 0x10 /* Modem Change Option 1 Register */
  64. #define CD180_MCOR2 0x11 /* Modem Change Option 2 Register */
  65. #define CD180_MCR 0x12 /* Modem Change Register */
  66. #define CD180_RTPR 0x18 /* Receive Timeout Period Register */
  67. #define CD180_MSVR 0x28 /* Modem Signal Value Register */
  68. #define CD180_RBPRH 0x31 /* Receive Baud Rate Period Register High */
  69. #define CD180_RBPRL 0x32 /* Receive Baud Rate Period Register Low */
  70. #define CD180_TBPRH 0x39 /* Transmit Baud Rate Period Register High */
  71. #define CD180_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */
  72. /* Global Interrupt Vector Register (R/W) */
  73. #define GIVR_ITMASK 0x07 /* Interrupt type mask */
  74. #define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */
  75. #define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */
  76. #define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */
  77. #define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */
  78. /* Global Interrupt Channel Register (R/W) */
  79. #define GICR_CHAN 0x1c /* Channel Number Mask */
  80. #define GICR_CHAN_OFF 2 /* Channel Number Offset */
  81. /* Channel Address Register (R/W) */
  82. #define CAR_CHAN 0x07 /* Channel Number Mask */
  83. #define CAR_A7 0x08 /* A7 Address Extension (unused) */
  84. /* Receive Character Status Register (R/O) */
  85. #define RCSR_TOUT 0x80 /* Rx Timeout */
  86. #define RCSR_SCDET 0x70 /* Special Character Detected Mask */
  87. #define RCSR_NO_SC 0x00 /* No Special Characters Detected */
  88. #define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
  89. #define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
  90. #define RCSR_SC_3 0x30 /* Special Char 3 Detected */
  91. #define RCSR_SC_4 0x40 /* Special Char 4 Detected */
  92. #define RCSR_BREAK 0x08 /* Break has been detected */
  93. #define RCSR_PE 0x04 /* Parity Error */
  94. #define RCSR_FE 0x02 /* Frame Error */
  95. #define RCSR_OE 0x01 /* Overrun Error */
  96. /* Channel Command Register (R/W) (commands in groups can be OR-ed) */
  97. #define CCR_HARDRESET 0x81 /* Reset the chip */
  98. #define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
  99. #define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
  100. #define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
  101. #define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
  102. #define CCR_SSCH1 0x21 /* Send Special Character 1 */
  103. #define CCR_SSCH2 0x22 /* Send Special Character 2 */
  104. #define CCR_SSCH3 0x23 /* Send Special Character 3 */
  105. #define CCR_SSCH4 0x24 /* Send Special Character 4 */
  106. #define CCR_TXEN 0x18 /* Enable Transmitter */
  107. #define CCR_RXEN 0x12 /* Enable Receiver */
  108. #define CCR_TXDIS 0x14 /* Disable Transmitter */
  109. #define CCR_RXDIS 0x11 /* Disable Receiver */
  110. /* Interrupt Enable Register (R/W) */
  111. #define IER_DSR 0x80 /* Enable interrupt on DSR change */
  112. #define IER_CD 0x40 /* Enable interrupt on CD change */
  113. #define IER_CTS 0x20 /* Enable interrupt on CTS change */
  114. #define IER_RXD 0x10 /* Enable interrupt on Receive Data */
  115. #define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
  116. #define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
  117. #define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
  118. #define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
  119. /* Channel Option Register 1 (R/W) */
  120. #define COR1_ODDP 0x80 /* Odd Parity */
  121. #define COR1_PARMODE 0x60 /* Parity Mode mask */
  122. #define COR1_NOPAR 0x00 /* No Parity */
  123. #define COR1_FORCEPAR 0x20 /* Force Parity */
  124. #define COR1_NORMPAR 0x40 /* Normal Parity */
  125. #define COR1_IGNORE 0x10 /* Ignore Parity on RX */
  126. #define COR1_STOPBITS 0x0c /* Number of Stop Bits */
  127. #define COR1_1SB 0x00 /* 1 Stop Bit */
  128. #define COR1_15SB 0x04 /* 1.5 Stop Bits */
  129. #define COR1_2SB 0x08 /* 2 Stop Bits */
  130. #define COR1_CHARLEN 0x03 /* Character Length */
  131. #define COR1_5BITS 0x00 /* 5 bits */
  132. #define COR1_6BITS 0x01 /* 6 bits */
  133. #define COR1_7BITS 0x02 /* 7 bits */
  134. #define COR1_8BITS 0x03 /* 8 bits */
  135. /* Channel Option Register 2 (R/W) */
  136. #define COR2_IXM 0x80 /* Implied XON mode */
  137. #define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
  138. #define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
  139. #define COR2_LLM 0x10 /* Local Loopback Mode */
  140. #define COR2_RLM 0x08 /* Remote Loopback Mode */
  141. #define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
  142. #define COR2_CTSAE 0x02 /* CTS Automatic Enable */
  143. #define COR2_DSRAE 0x01 /* DSR Automatic Enable */
  144. /* Channel Option Register 3 (R/W) */
  145. #define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
  146. #define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
  147. #define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
  148. #define COR3_SCDE 0x10 /* Special Character Detection Enable */
  149. #define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
  150. /* Channel Control Status Register (R/O) */
  151. #define CCSR_RXEN 0x80 /* Receiver Enabled */
  152. #define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
  153. #define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
  154. #define CCSR_TXEN 0x08 /* Transmitter Enabled */
  155. #define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
  156. #define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
  157. /* Modem Change Option Register 1 (R/W) */
  158. #define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
  159. #define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
  160. #define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
  161. #define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
  162. #define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
  163. /* Modem Change Option Register 2 (R/W) */
  164. #define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
  165. #define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
  166. #define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
  167. /* Modem Change Register (R/W) */
  168. #define MCR_DSRCHG 0x80 /* DSR Changed */
  169. #define MCR_CDCHG 0x40 /* CD Changed */
  170. #define MCR_CTSCHG 0x20 /* CTS Changed */
  171. /* Modem Signal Value Register (R/W) */
  172. #define MSVR_DSR 0x80 /* Current state of DSR input */
  173. #define MSVR_CD 0x40 /* Current state of CD input */
  174. #define MSVR_CTS 0x20 /* Current state of CTS input */
  175. #define MSVR_DTR 0x02 /* Current state of DTR output */
  176. #define MSVR_RTS 0x01 /* Current state of RTS output */
  177. /* Escape characters */
  178. #define CD180_C_ESC 0x00 /* Escape character */
  179. #define CD180_C_SBRK 0x81 /* Start sending BREAK */
  180. #define CD180_C_DELAY 0x82 /* Delay output */
  181. #define CD180_C_EBRK 0x83 /* Stop sending BREAK */