mxser_new.h 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293
  1. #ifndef _MXSER_H
  2. #define _MXSER_H
  3. /*
  4. * Semi-public control interfaces
  5. */
  6. /*
  7. * MOXA ioctls
  8. */
  9. #define MOXA 0x400
  10. #define MOXA_GETDATACOUNT (MOXA + 23)
  11. #define MOXA_GET_CONF (MOXA + 35)
  12. #define MOXA_DIAGNOSE (MOXA + 50)
  13. #define MOXA_CHKPORTENABLE (MOXA + 60)
  14. #define MOXA_HighSpeedOn (MOXA + 61)
  15. #define MOXA_GET_MAJOR (MOXA + 63)
  16. #define MOXA_GET_CUMAJOR (MOXA + 64)
  17. #define MOXA_GETMSTATUS (MOXA + 65)
  18. #define MOXA_SET_OP_MODE (MOXA + 66)
  19. #define MOXA_GET_OP_MODE (MOXA + 67)
  20. #define RS232_MODE 0
  21. #define RS485_2WIRE_MODE 1
  22. #define RS422_MODE 2
  23. #define RS485_4WIRE_MODE 3
  24. #define OP_MODE_MASK 3
  25. #define MOXA_SDS_RSTICOUNTER (MOXA + 69)
  26. #define MOXA_ASPP_OQUEUE (MOXA + 70)
  27. #define MOXA_ASPP_SETBAUD (MOXA + 71)
  28. #define MOXA_ASPP_GETBAUD (MOXA + 72)
  29. #define MOXA_ASPP_MON (MOXA + 73)
  30. #define MOXA_ASPP_LSTATUS (MOXA + 74)
  31. #define MOXA_ASPP_MON_EXT (MOXA + 75)
  32. #define MOXA_SET_BAUD_METHOD (MOXA + 76)
  33. #define MOXA_SET_SPECIAL_BAUD_RATE (MOXA + 77)
  34. #define MOXA_GET_SPECIAL_BAUD_RATE (MOXA + 78)
  35. /* --------------------------------------------------- */
  36. #define NPPI_NOTIFY_PARITY 0x01
  37. #define NPPI_NOTIFY_FRAMING 0x02
  38. #define NPPI_NOTIFY_HW_OVERRUN 0x04
  39. #define NPPI_NOTIFY_SW_OVERRUN 0x08
  40. #define NPPI_NOTIFY_BREAK 0x10
  41. #define NPPI_NOTIFY_CTSHOLD 0x01 /* Tx hold by CTS low */
  42. #define NPPI_NOTIFY_DSRHOLD 0x02 /* Tx hold by DSR low */
  43. #define NPPI_NOTIFY_XOFFHOLD 0x08 /* Tx hold by Xoff received */
  44. #define NPPI_NOTIFY_XOFFXENT 0x10 /* Xoff Sent */
  45. /* follow just for Moxa Must chip define. */
  46. /* */
  47. /* when LCR register (offset 0x03) write following value, */
  48. /* the Must chip will enter enchance mode. And write value */
  49. /* on EFR (offset 0x02) bit 6,7 to change bank. */
  50. #define MOXA_MUST_ENTER_ENCHANCE 0xBF
  51. /* when enhance mode enable, access on general bank register */
  52. #define MOXA_MUST_GDL_REGISTER 0x07
  53. #define MOXA_MUST_GDL_MASK 0x7F
  54. #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
  55. #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
  56. /* enchance register bank select and enchance mode setting register */
  57. /* when LCR register equal to 0xBF */
  58. #define MOXA_MUST_EFR_REGISTER 0x02
  59. /* enchance mode enable */
  60. #define MOXA_MUST_EFR_EFRB_ENABLE 0x10
  61. /* enchance reister bank set 0, 1, 2 */
  62. #define MOXA_MUST_EFR_BANK0 0x00
  63. #define MOXA_MUST_EFR_BANK1 0x40
  64. #define MOXA_MUST_EFR_BANK2 0x80
  65. #define MOXA_MUST_EFR_BANK3 0xC0
  66. #define MOXA_MUST_EFR_BANK_MASK 0xC0
  67. /* set XON1 value register, when LCR=0xBF and change to bank0 */
  68. #define MOXA_MUST_XON1_REGISTER 0x04
  69. /* set XON2 value register, when LCR=0xBF and change to bank0 */
  70. #define MOXA_MUST_XON2_REGISTER 0x05
  71. /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
  72. #define MOXA_MUST_XOFF1_REGISTER 0x06
  73. /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
  74. #define MOXA_MUST_XOFF2_REGISTER 0x07
  75. #define MOXA_MUST_RBRTL_REGISTER 0x04
  76. #define MOXA_MUST_RBRTH_REGISTER 0x05
  77. #define MOXA_MUST_RBRTI_REGISTER 0x06
  78. #define MOXA_MUST_THRTL_REGISTER 0x07
  79. #define MOXA_MUST_ENUM_REGISTER 0x04
  80. #define MOXA_MUST_HWID_REGISTER 0x05
  81. #define MOXA_MUST_ECR_REGISTER 0x06
  82. #define MOXA_MUST_CSR_REGISTER 0x07
  83. /* good data mode enable */
  84. #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20
  85. /* only good data put into RxFIFO */
  86. #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10
  87. /* enable CTS interrupt */
  88. #define MOXA_MUST_IER_ECTSI 0x80
  89. /* enable RTS interrupt */
  90. #define MOXA_MUST_IER_ERTSI 0x40
  91. /* enable Xon/Xoff interrupt */
  92. #define MOXA_MUST_IER_XINT 0x20
  93. /* enable GDA interrupt */
  94. #define MOXA_MUST_IER_EGDAI 0x10
  95. #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
  96. /* GDA interrupt pending */
  97. #define MOXA_MUST_IIR_GDA 0x1C
  98. #define MOXA_MUST_IIR_RDA 0x04
  99. #define MOXA_MUST_IIR_RTO 0x0C
  100. #define MOXA_MUST_IIR_LSR 0x06
  101. /* recieved Xon/Xoff or specical interrupt pending */
  102. #define MOXA_MUST_IIR_XSC 0x10
  103. /* RTS/CTS change state interrupt pending */
  104. #define MOXA_MUST_IIR_RTSCTS 0x20
  105. #define MOXA_MUST_IIR_MASK 0x3E
  106. #define MOXA_MUST_MCR_XON_FLAG 0x40
  107. #define MOXA_MUST_MCR_XON_ANY 0x80
  108. #define MOXA_MUST_MCR_TX_XON 0x08
  109. /* software flow control on chip mask value */
  110. #define MOXA_MUST_EFR_SF_MASK 0x0F
  111. /* send Xon1/Xoff1 */
  112. #define MOXA_MUST_EFR_SF_TX1 0x08
  113. /* send Xon2/Xoff2 */
  114. #define MOXA_MUST_EFR_SF_TX2 0x04
  115. /* send Xon1,Xon2/Xoff1,Xoff2 */
  116. #define MOXA_MUST_EFR_SF_TX12 0x0C
  117. /* don't send Xon/Xoff */
  118. #define MOXA_MUST_EFR_SF_TX_NO 0x00
  119. /* Tx software flow control mask */
  120. #define MOXA_MUST_EFR_SF_TX_MASK 0x0C
  121. /* don't receive Xon/Xoff */
  122. #define MOXA_MUST_EFR_SF_RX_NO 0x00
  123. /* receive Xon1/Xoff1 */
  124. #define MOXA_MUST_EFR_SF_RX1 0x02
  125. /* receive Xon2/Xoff2 */
  126. #define MOXA_MUST_EFR_SF_RX2 0x01
  127. /* receive Xon1,Xon2/Xoff1,Xoff2 */
  128. #define MOXA_MUST_EFR_SF_RX12 0x03
  129. /* Rx software flow control mask */
  130. #define MOXA_MUST_EFR_SF_RX_MASK 0x03
  131. #define ENABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
  132. u8 __oldlcr, __efr; \
  133. __oldlcr = inb((baseio)+UART_LCR); \
  134. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  135. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  136. __efr |= MOXA_MUST_EFR_EFRB_ENABLE; \
  137. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  138. outb(__oldlcr, (baseio)+UART_LCR); \
  139. } while (0)
  140. #define DISABLE_MOXA_MUST_ENCHANCE_MODE(baseio) do { \
  141. u8 __oldlcr, __efr; \
  142. __oldlcr = inb((baseio)+UART_LCR); \
  143. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  144. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  145. __efr &= ~MOXA_MUST_EFR_EFRB_ENABLE; \
  146. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  147. outb(__oldlcr, (baseio)+UART_LCR); \
  148. } while (0)
  149. #define SET_MOXA_MUST_XON1_VALUE(baseio, Value) do { \
  150. u8 __oldlcr, __efr; \
  151. __oldlcr = inb((baseio)+UART_LCR); \
  152. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  153. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  154. __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
  155. __efr |= MOXA_MUST_EFR_BANK0; \
  156. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  157. outb((u8)(Value), (baseio)+MOXA_MUST_XON1_REGISTER); \
  158. outb(__oldlcr, (baseio)+UART_LCR); \
  159. } while (0)
  160. #define SET_MOXA_MUST_XOFF1_VALUE(baseio, Value) do { \
  161. u8 __oldlcr, __efr; \
  162. __oldlcr = inb((baseio)+UART_LCR); \
  163. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  164. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  165. __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
  166. __efr |= MOXA_MUST_EFR_BANK0; \
  167. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  168. outb((u8)(Value), (baseio)+MOXA_MUST_XOFF1_REGISTER); \
  169. outb(__oldlcr, (baseio)+UART_LCR); \
  170. } while (0)
  171. #define SET_MOXA_MUST_FIFO_VALUE(info) do { \
  172. u8 __oldlcr, __efr; \
  173. __oldlcr = inb((info)->ioaddr+UART_LCR); \
  174. outb(MOXA_MUST_ENTER_ENCHANCE, (info)->ioaddr+UART_LCR);\
  175. __efr = inb((info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
  176. __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
  177. __efr |= MOXA_MUST_EFR_BANK1; \
  178. outb(__efr, (info)->ioaddr+MOXA_MUST_EFR_REGISTER); \
  179. outb((u8)((info)->rx_high_water), (info)->ioaddr+ \
  180. MOXA_MUST_RBRTH_REGISTER); \
  181. outb((u8)((info)->rx_trigger), (info)->ioaddr+ \
  182. MOXA_MUST_RBRTI_REGISTER); \
  183. outb((u8)((info)->rx_low_water), (info)->ioaddr+ \
  184. MOXA_MUST_RBRTL_REGISTER); \
  185. outb(__oldlcr, (info)->ioaddr+UART_LCR); \
  186. } while (0)
  187. #define SET_MOXA_MUST_ENUM_VALUE(baseio, Value) do { \
  188. u8 __oldlcr, __efr; \
  189. __oldlcr = inb((baseio)+UART_LCR); \
  190. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  191. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  192. __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
  193. __efr |= MOXA_MUST_EFR_BANK2; \
  194. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  195. outb((u8)(Value), (baseio)+MOXA_MUST_ENUM_REGISTER); \
  196. outb(__oldlcr, (baseio)+UART_LCR); \
  197. } while (0)
  198. #define GET_MOXA_MUST_HARDWARE_ID(baseio, pId) do { \
  199. u8 __oldlcr, __efr; \
  200. __oldlcr = inb((baseio)+UART_LCR); \
  201. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  202. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  203. __efr &= ~MOXA_MUST_EFR_BANK_MASK; \
  204. __efr |= MOXA_MUST_EFR_BANK2; \
  205. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  206. *pId = inb((baseio)+MOXA_MUST_HWID_REGISTER); \
  207. outb(__oldlcr, (baseio)+UART_LCR); \
  208. } while (0)
  209. #define SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(baseio) do { \
  210. u8 __oldlcr, __efr; \
  211. __oldlcr = inb((baseio)+UART_LCR); \
  212. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  213. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  214. __efr &= ~MOXA_MUST_EFR_SF_MASK; \
  215. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  216. outb(__oldlcr, (baseio)+UART_LCR); \
  217. } while (0)
  218. #define ENABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
  219. u8 __oldlcr, __efr; \
  220. __oldlcr = inb((baseio)+UART_LCR); \
  221. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  222. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  223. __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
  224. __efr |= MOXA_MUST_EFR_SF_TX1; \
  225. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  226. outb(__oldlcr, (baseio)+UART_LCR); \
  227. } while (0)
  228. #define DISABLE_MOXA_MUST_TX_SOFTWARE_FLOW_CONTROL(baseio) do { \
  229. u8 __oldlcr, __efr; \
  230. __oldlcr = inb((baseio)+UART_LCR); \
  231. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  232. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  233. __efr &= ~MOXA_MUST_EFR_SF_TX_MASK; \
  234. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  235. outb(__oldlcr, (baseio)+UART_LCR); \
  236. } while (0)
  237. #define ENABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
  238. u8 __oldlcr, __efr; \
  239. __oldlcr = inb((baseio)+UART_LCR); \
  240. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  241. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  242. __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
  243. __efr |= MOXA_MUST_EFR_SF_RX1; \
  244. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  245. outb(__oldlcr, (baseio)+UART_LCR); \
  246. } while (0)
  247. #define DISABLE_MOXA_MUST_RX_SOFTWARE_FLOW_CONTROL(baseio) do { \
  248. u8 __oldlcr, __efr; \
  249. __oldlcr = inb((baseio)+UART_LCR); \
  250. outb(MOXA_MUST_ENTER_ENCHANCE, (baseio)+UART_LCR); \
  251. __efr = inb((baseio)+MOXA_MUST_EFR_REGISTER); \
  252. __efr &= ~MOXA_MUST_EFR_SF_RX_MASK; \
  253. outb(__efr, (baseio)+MOXA_MUST_EFR_REGISTER); \
  254. outb(__oldlcr, (baseio)+UART_LCR); \
  255. } while (0)
  256. #endif