mbcs.h 13 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. #ifndef __MBCS_H__
  9. #define __MBCS_H__
  10. /*
  11. * General macros
  12. */
  13. #define MB (1024*1024)
  14. #define MB2 (2*MB)
  15. #define MB4 (4*MB)
  16. #define MB6 (6*MB)
  17. /*
  18. * Offsets and masks
  19. */
  20. #define MBCS_CM_ID 0x0000 /* Identification */
  21. #define MBCS_CM_STATUS 0x0008 /* Status */
  22. #define MBCS_CM_ERROR_DETAIL1 0x0010 /* Error Detail1 */
  23. #define MBCS_CM_ERROR_DETAIL2 0x0018 /* Error Detail2 */
  24. #define MBCS_CM_CONTROL 0x0020 /* Control */
  25. #define MBCS_CM_REQ_TOUT 0x0028 /* Request Time-out */
  26. #define MBCS_CM_ERR_INT_DEST 0x0038 /* Error Interrupt Destination */
  27. #define MBCS_CM_TARG_FL 0x0050 /* Target Flush */
  28. #define MBCS_CM_ERR_STAT 0x0060 /* Error Status */
  29. #define MBCS_CM_CLR_ERR_STAT 0x0068 /* Clear Error Status */
  30. #define MBCS_CM_ERR_INT_EN 0x0070 /* Error Interrupt Enable */
  31. #define MBCS_RD_DMA_SYS_ADDR 0x0100 /* Read DMA System Address */
  32. #define MBCS_RD_DMA_LOC_ADDR 0x0108 /* Read DMA Local Address */
  33. #define MBCS_RD_DMA_CTRL 0x0110 /* Read DMA Control */
  34. #define MBCS_RD_DMA_AMO_DEST 0x0118 /* Read DMA AMO Destination */
  35. #define MBCS_RD_DMA_INT_DEST 0x0120 /* Read DMA Interrupt Destination */
  36. #define MBCS_RD_DMA_AUX_STAT 0x0130 /* Read DMA Auxillary Status */
  37. #define MBCS_WR_DMA_SYS_ADDR 0x0200 /* Write DMA System Address */
  38. #define MBCS_WR_DMA_LOC_ADDR 0x0208 /* Write DMA Local Address */
  39. #define MBCS_WR_DMA_CTRL 0x0210 /* Write DMA Control */
  40. #define MBCS_WR_DMA_AMO_DEST 0x0218 /* Write DMA AMO Destination */
  41. #define MBCS_WR_DMA_INT_DEST 0x0220 /* Write DMA Interrupt Destination */
  42. #define MBCS_WR_DMA_AUX_STAT 0x0230 /* Write DMA Auxillary Status */
  43. #define MBCS_ALG_AMO_DEST 0x0300 /* Algorithm AMO Destination */
  44. #define MBCS_ALG_INT_DEST 0x0308 /* Algorithm Interrupt Destination */
  45. #define MBCS_ALG_OFFSETS 0x0310
  46. #define MBCS_ALG_STEP 0x0318 /* Algorithm Step */
  47. #define MBCS_GSCR_START 0x0000000
  48. #define MBCS_DEBUG_START 0x0100000
  49. #define MBCS_RAM0_START 0x0200000
  50. #define MBCS_RAM1_START 0x0400000
  51. #define MBCS_RAM2_START 0x0600000
  52. #define MBCS_CM_CONTROL_REQ_TOUT_MASK 0x0000000000ffffffUL
  53. //#define PIO_BASE_ADDR_BASE_OFFSET_MASK 0x00fffffffff00000UL
  54. #define MBCS_SRAM_SIZE (1024*1024)
  55. #define MBCS_CACHELINE_SIZE 128
  56. /*
  57. * MMR get's and put's
  58. */
  59. #define MBCS_MMR_ADDR(mmr_base, offset)((uint64_t *)(mmr_base + offset))
  60. #define MBCS_MMR_SET(mmr_base, offset, value) { \
  61. uint64_t *mbcs_mmr_set_u64p, readback; \
  62. mbcs_mmr_set_u64p = (uint64_t *)(mmr_base + offset); \
  63. *mbcs_mmr_set_u64p = value; \
  64. readback = *mbcs_mmr_set_u64p; \
  65. }
  66. #define MBCS_MMR_GET(mmr_base, offset) *(uint64_t *)(mmr_base + offset)
  67. #define MBCS_MMR_ZERO(mmr_base, offset) MBCS_MMR_SET(mmr_base, offset, 0)
  68. /*
  69. * MBCS mmr structures
  70. */
  71. union cm_id {
  72. uint64_t cm_id_reg;
  73. struct {
  74. uint64_t always_one:1, // 0
  75. mfg_id:11, // 11:1
  76. part_num:16, // 27:12
  77. bitstream_rev:8, // 35:28
  78. :28; // 63:36
  79. };
  80. };
  81. union cm_status {
  82. uint64_t cm_status_reg;
  83. struct {
  84. uint64_t pending_reads:8, // 7:0
  85. pending_writes:8, // 15:8
  86. ice_rsp_credits:8, // 23:16
  87. ice_req_credits:8, // 31:24
  88. cm_req_credits:8, // 39:32
  89. :1, // 40
  90. rd_dma_in_progress:1, // 41
  91. rd_dma_done:1, // 42
  92. :1, // 43
  93. wr_dma_in_progress:1, // 44
  94. wr_dma_done:1, // 45
  95. alg_waiting:1, // 46
  96. alg_pipe_running:1, // 47
  97. alg_done:1, // 48
  98. :3, // 51:49
  99. pending_int_reqs:8, // 59:52
  100. :3, // 62:60
  101. alg_half_speed_sel:1; // 63
  102. };
  103. };
  104. union cm_error_detail1 {
  105. uint64_t cm_error_detail1_reg;
  106. struct {
  107. uint64_t packet_type:4, // 3:0
  108. source_id:2, // 5:4
  109. data_size:2, // 7:6
  110. tnum:8, // 15:8
  111. byte_enable:8, // 23:16
  112. gfx_cred:8, // 31:24
  113. read_type:2, // 33:32
  114. pio_or_memory:1, // 34
  115. head_cw_error:1, // 35
  116. :12, // 47:36
  117. head_error_bit:1, // 48
  118. data_error_bit:1, // 49
  119. :13, // 62:50
  120. valid:1; // 63
  121. };
  122. };
  123. union cm_error_detail2 {
  124. uint64_t cm_error_detail2_reg;
  125. struct {
  126. uint64_t address:56, // 55:0
  127. :8; // 63:56
  128. };
  129. };
  130. union cm_control {
  131. uint64_t cm_control_reg;
  132. struct {
  133. uint64_t cm_id:2, // 1:0
  134. :2, // 3:2
  135. max_trans:5, // 8:4
  136. :3, // 11:9
  137. address_mode:1, // 12
  138. :7, // 19:13
  139. credit_limit:8, // 27:20
  140. :5, // 32:28
  141. rearm_stat_regs:1, // 33
  142. prescalar_byp:1, // 34
  143. force_gap_war:1, // 35
  144. rd_dma_go:1, // 36
  145. wr_dma_go:1, // 37
  146. alg_go:1, // 38
  147. rd_dma_clr:1, // 39
  148. wr_dma_clr:1, // 40
  149. alg_clr:1, // 41
  150. :2, // 43:42
  151. alg_wait_step:1, // 44
  152. alg_done_amo_en:1, // 45
  153. alg_done_int_en:1, // 46
  154. :1, // 47
  155. alg_sram0_locked:1, // 48
  156. alg_sram1_locked:1, // 49
  157. alg_sram2_locked:1, // 50
  158. alg_done_clr:1, // 51
  159. :12; // 63:52
  160. };
  161. };
  162. union cm_req_timeout {
  163. uint64_t cm_req_timeout_reg;
  164. struct {
  165. uint64_t time_out:24, // 23:0
  166. :40; // 63:24
  167. };
  168. };
  169. union intr_dest {
  170. uint64_t intr_dest_reg;
  171. struct {
  172. uint64_t address:56, // 55:0
  173. int_vector:8; // 63:56
  174. };
  175. };
  176. union cm_error_status {
  177. uint64_t cm_error_status_reg;
  178. struct {
  179. uint64_t ecc_sbe:1, // 0
  180. ecc_mbe:1, // 1
  181. unsupported_req:1, // 2
  182. unexpected_rsp:1, // 3
  183. bad_length:1, // 4
  184. bad_datavalid:1, // 5
  185. buffer_overflow:1, // 6
  186. request_timeout:1, // 7
  187. :8, // 15:8
  188. head_inv_data_size:1, // 16
  189. rsp_pactype_inv:1, // 17
  190. head_sb_err:1, // 18
  191. missing_head:1, // 19
  192. head_inv_rd_type:1, // 20
  193. head_cmd_err_bit:1, // 21
  194. req_addr_align_inv:1, // 22
  195. pio_req_addr_inv:1, // 23
  196. req_range_dsize_inv:1, // 24
  197. early_term:1, // 25
  198. early_tail:1, // 26
  199. missing_tail:1, // 27
  200. data_flit_sb_err:1, // 28
  201. cm2hcm_req_cred_of:1, // 29
  202. cm2hcm_rsp_cred_of:1, // 30
  203. rx_bad_didn:1, // 31
  204. rd_dma_err_rsp:1, // 32
  205. rd_dma_tnum_tout:1, // 33
  206. rd_dma_multi_tnum_tou:1, // 34
  207. wr_dma_err_rsp:1, // 35
  208. wr_dma_tnum_tout:1, // 36
  209. wr_dma_multi_tnum_tou:1, // 37
  210. alg_data_overflow:1, // 38
  211. alg_data_underflow:1, // 39
  212. ram0_access_conflict:1, // 40
  213. ram1_access_conflict:1, // 41
  214. ram2_access_conflict:1, // 42
  215. ram0_perr:1, // 43
  216. ram1_perr:1, // 44
  217. ram2_perr:1, // 45
  218. int_gen_rsp_err:1, // 46
  219. int_gen_tnum_tout:1, // 47
  220. rd_dma_prog_err:1, // 48
  221. wr_dma_prog_err:1, // 49
  222. :14; // 63:50
  223. };
  224. };
  225. union cm_clr_error_status {
  226. uint64_t cm_clr_error_status_reg;
  227. struct {
  228. uint64_t clr_ecc_sbe:1, // 0
  229. clr_ecc_mbe:1, // 1
  230. clr_unsupported_req:1, // 2
  231. clr_unexpected_rsp:1, // 3
  232. clr_bad_length:1, // 4
  233. clr_bad_datavalid:1, // 5
  234. clr_buffer_overflow:1, // 6
  235. clr_request_timeout:1, // 7
  236. :8, // 15:8
  237. clr_head_inv_data_siz:1, // 16
  238. clr_rsp_pactype_inv:1, // 17
  239. clr_head_sb_err:1, // 18
  240. clr_missing_head:1, // 19
  241. clr_head_inv_rd_type:1, // 20
  242. clr_head_cmd_err_bit:1, // 21
  243. clr_req_addr_align_in:1, // 22
  244. clr_pio_req_addr_inv:1, // 23
  245. clr_req_range_dsize_i:1, // 24
  246. clr_early_term:1, // 25
  247. clr_early_tail:1, // 26
  248. clr_missing_tail:1, // 27
  249. clr_data_flit_sb_err:1, // 28
  250. clr_cm2hcm_req_cred_o:1, // 29
  251. clr_cm2hcm_rsp_cred_o:1, // 30
  252. clr_rx_bad_didn:1, // 31
  253. clr_rd_dma_err_rsp:1, // 32
  254. clr_rd_dma_tnum_tout:1, // 33
  255. clr_rd_dma_multi_tnum:1, // 34
  256. clr_wr_dma_err_rsp:1, // 35
  257. clr_wr_dma_tnum_tout:1, // 36
  258. clr_wr_dma_multi_tnum:1, // 37
  259. clr_alg_data_overflow:1, // 38
  260. clr_alg_data_underflo:1, // 39
  261. clr_ram0_access_confl:1, // 40
  262. clr_ram1_access_confl:1, // 41
  263. clr_ram2_access_confl:1, // 42
  264. clr_ram0_perr:1, // 43
  265. clr_ram1_perr:1, // 44
  266. clr_ram2_perr:1, // 45
  267. clr_int_gen_rsp_err:1, // 46
  268. clr_int_gen_tnum_tout:1, // 47
  269. clr_rd_dma_prog_err:1, // 48
  270. clr_wr_dma_prog_err:1, // 49
  271. :14; // 63:50
  272. };
  273. };
  274. union cm_error_intr_enable {
  275. uint64_t cm_error_intr_enable_reg;
  276. struct {
  277. uint64_t int_en_ecc_sbe:1, // 0
  278. int_en_ecc_mbe:1, // 1
  279. int_en_unsupported_re:1, // 2
  280. int_en_unexpected_rsp:1, // 3
  281. int_en_bad_length:1, // 4
  282. int_en_bad_datavalid:1, // 5
  283. int_en_buffer_overflo:1, // 6
  284. int_en_request_timeou:1, // 7
  285. :8, // 15:8
  286. int_en_head_inv_data_:1, // 16
  287. int_en_rsp_pactype_in:1, // 17
  288. int_en_head_sb_err:1, // 18
  289. int_en_missing_head:1, // 19
  290. int_en_head_inv_rd_ty:1, // 20
  291. int_en_head_cmd_err_b:1, // 21
  292. int_en_req_addr_align:1, // 22
  293. int_en_pio_req_addr_i:1, // 23
  294. int_en_req_range_dsiz:1, // 24
  295. int_en_early_term:1, // 25
  296. int_en_early_tail:1, // 26
  297. int_en_missing_tail:1, // 27
  298. int_en_data_flit_sb_e:1, // 28
  299. int_en_cm2hcm_req_cre:1, // 29
  300. int_en_cm2hcm_rsp_cre:1, // 30
  301. int_en_rx_bad_didn:1, // 31
  302. int_en_rd_dma_err_rsp:1, // 32
  303. int_en_rd_dma_tnum_to:1, // 33
  304. int_en_rd_dma_multi_t:1, // 34
  305. int_en_wr_dma_err_rsp:1, // 35
  306. int_en_wr_dma_tnum_to:1, // 36
  307. int_en_wr_dma_multi_t:1, // 37
  308. int_en_alg_data_overf:1, // 38
  309. int_en_alg_data_under:1, // 39
  310. int_en_ram0_access_co:1, // 40
  311. int_en_ram1_access_co:1, // 41
  312. int_en_ram2_access_co:1, // 42
  313. int_en_ram0_perr:1, // 43
  314. int_en_ram1_perr:1, // 44
  315. int_en_ram2_perr:1, // 45
  316. int_en_int_gen_rsp_er:1, // 46
  317. int_en_int_gen_tnum_t:1, // 47
  318. int_en_rd_dma_prog_er:1, // 48
  319. int_en_wr_dma_prog_er:1, // 49
  320. :14; // 63:50
  321. };
  322. };
  323. struct cm_mmr {
  324. union cm_id id;
  325. union cm_status status;
  326. union cm_error_detail1 err_detail1;
  327. union cm_error_detail2 err_detail2;
  328. union cm_control control;
  329. union cm_req_timeout req_timeout;
  330. uint64_t reserved1[1];
  331. union intr_dest int_dest;
  332. uint64_t reserved2[2];
  333. uint64_t targ_flush;
  334. uint64_t reserved3[1];
  335. union cm_error_status err_status;
  336. union cm_clr_error_status clr_err_status;
  337. union cm_error_intr_enable int_enable;
  338. };
  339. union dma_hostaddr {
  340. uint64_t dma_hostaddr_reg;
  341. struct {
  342. uint64_t dma_sys_addr:56, // 55:0
  343. :8; // 63:56
  344. };
  345. };
  346. union dma_localaddr {
  347. uint64_t dma_localaddr_reg;
  348. struct {
  349. uint64_t dma_ram_addr:21, // 20:0
  350. dma_ram_sel:2, // 22:21
  351. :41; // 63:23
  352. };
  353. };
  354. union dma_control {
  355. uint64_t dma_control_reg;
  356. struct {
  357. uint64_t dma_op_length:16, // 15:0
  358. :18, // 33:16
  359. done_amo_en:1, // 34
  360. done_int_en:1, // 35
  361. :1, // 36
  362. pio_mem_n:1, // 37
  363. :26; // 63:38
  364. };
  365. };
  366. union dma_amo_dest {
  367. uint64_t dma_amo_dest_reg;
  368. struct {
  369. uint64_t dma_amo_sys_addr:56, // 55:0
  370. dma_amo_mod_type:3, // 58:56
  371. :5; // 63:59
  372. };
  373. };
  374. union rdma_aux_status {
  375. uint64_t rdma_aux_status_reg;
  376. struct {
  377. uint64_t op_num_pacs_left:17, // 16:0
  378. :5, // 21:17
  379. lrsp_buff_empty:1, // 22
  380. :17, // 39:23
  381. pending_reqs_left:6, // 45:40
  382. :18; // 63:46
  383. };
  384. };
  385. struct rdma_mmr {
  386. union dma_hostaddr host_addr;
  387. union dma_localaddr local_addr;
  388. union dma_control control;
  389. union dma_amo_dest amo_dest;
  390. union intr_dest intr_dest;
  391. union rdma_aux_status aux_status;
  392. };
  393. union wdma_aux_status {
  394. uint64_t wdma_aux_status_reg;
  395. struct {
  396. uint64_t op_num_pacs_left:17, // 16:0
  397. :4, // 20:17
  398. lreq_buff_empty:1, // 21
  399. :18, // 39:22
  400. pending_reqs_left:6, // 45:40
  401. :18; // 63:46
  402. };
  403. };
  404. struct wdma_mmr {
  405. union dma_hostaddr host_addr;
  406. union dma_localaddr local_addr;
  407. union dma_control control;
  408. union dma_amo_dest amo_dest;
  409. union intr_dest intr_dest;
  410. union wdma_aux_status aux_status;
  411. };
  412. union algo_step {
  413. uint64_t algo_step_reg;
  414. struct {
  415. uint64_t alg_step_cnt:16, // 15:0
  416. :48; // 63:16
  417. };
  418. };
  419. struct algo_mmr {
  420. union dma_amo_dest amo_dest;
  421. union intr_dest intr_dest;
  422. union {
  423. uint64_t algo_offset_reg;
  424. struct {
  425. uint64_t sram0_offset:7, // 6:0
  426. reserved0:1, // 7
  427. sram1_offset:7, // 14:8
  428. reserved1:1, // 15
  429. sram2_offset:7, // 22:16
  430. reserved2:14; // 63:23
  431. };
  432. } sram_offset;
  433. union algo_step step;
  434. };
  435. struct mbcs_mmr {
  436. struct cm_mmr cm;
  437. uint64_t reserved1[17];
  438. struct rdma_mmr rdDma;
  439. uint64_t reserved2[25];
  440. struct wdma_mmr wrDma;
  441. uint64_t reserved3[25];
  442. struct algo_mmr algo;
  443. uint64_t reserved4[156];
  444. };
  445. /*
  446. * defines
  447. */
  448. #define DEVICE_NAME "mbcs"
  449. #define MBCS_PART_NUM 0xfff0
  450. #define MBCS_PART_NUM_ALG0 0xf001
  451. #define MBCS_MFG_NUM 0x1
  452. struct algoblock {
  453. uint64_t amoHostDest;
  454. uint64_t amoModType;
  455. uint64_t intrHostDest;
  456. uint64_t intrVector;
  457. uint64_t algoStepCount;
  458. };
  459. struct getdma {
  460. uint64_t hostAddr;
  461. uint64_t localAddr;
  462. uint64_t bytes;
  463. uint64_t DoneAmoEnable;
  464. uint64_t DoneIntEnable;
  465. uint64_t peerIO;
  466. uint64_t amoHostDest;
  467. uint64_t amoModType;
  468. uint64_t intrHostDest;
  469. uint64_t intrVector;
  470. };
  471. struct putdma {
  472. uint64_t hostAddr;
  473. uint64_t localAddr;
  474. uint64_t bytes;
  475. uint64_t DoneAmoEnable;
  476. uint64_t DoneIntEnable;
  477. uint64_t peerIO;
  478. uint64_t amoHostDest;
  479. uint64_t amoModType;
  480. uint64_t intrHostDest;
  481. uint64_t intrVector;
  482. };
  483. struct mbcs_soft {
  484. struct list_head list;
  485. struct cx_dev *cxdev;
  486. int major;
  487. int nasid;
  488. void *mmr_base;
  489. wait_queue_head_t dmawrite_queue;
  490. wait_queue_head_t dmaread_queue;
  491. wait_queue_head_t algo_queue;
  492. struct sn_irq_info *get_sn_irq;
  493. struct sn_irq_info *put_sn_irq;
  494. struct sn_irq_info *algo_sn_irq;
  495. struct getdma getdma;
  496. struct putdma putdma;
  497. struct algoblock algo;
  498. uint64_t gscr_addr; // pio addr
  499. uint64_t ram0_addr; // pio addr
  500. uint64_t ram1_addr; // pio addr
  501. uint64_t ram2_addr; // pio addr
  502. uint64_t debug_addr; // pio addr
  503. atomic_t dmawrite_done;
  504. atomic_t dmaread_done;
  505. atomic_t algo_done;
  506. struct semaphore dmawritelock;
  507. struct semaphore dmareadlock;
  508. struct semaphore algolock;
  509. };
  510. extern int mbcs_open(struct inode *ip, struct file *fp);
  511. extern ssize_t mbcs_sram_read(struct file *fp, char __user *buf, size_t len,
  512. loff_t * off);
  513. extern ssize_t mbcs_sram_write(struct file *fp, const char __user *buf, size_t len,
  514. loff_t * off);
  515. extern loff_t mbcs_sram_llseek(struct file *filp, loff_t off, int whence);
  516. extern int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma);
  517. #endif // __MBCS_H__