mbcs.c 20 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
  7. */
  8. /*
  9. * MOATB Core Services driver.
  10. */
  11. #include <linux/interrupt.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/types.h>
  15. #include <linux/ioport.h>
  16. #include <linux/notifier.h>
  17. #include <linux/reboot.h>
  18. #include <linux/init.h>
  19. #include <linux/fs.h>
  20. #include <linux/delay.h>
  21. #include <linux/device.h>
  22. #include <linux/mm.h>
  23. #include <linux/fs.h>
  24. #include <linux/uio.h>
  25. #include <asm/io.h>
  26. #include <asm/uaccess.h>
  27. #include <asm/system.h>
  28. #include <asm/pgtable.h>
  29. #include <asm/sn/addrs.h>
  30. #include <asm/sn/intr.h>
  31. #include <asm/sn/tiocx.h>
  32. #include "mbcs.h"
  33. #define MBCS_DEBUG 0
  34. #if MBCS_DEBUG
  35. #define DBG(fmt...) printk(KERN_ALERT fmt)
  36. #else
  37. #define DBG(fmt...)
  38. #endif
  39. int mbcs_major;
  40. LIST_HEAD(soft_list);
  41. /*
  42. * file operations
  43. */
  44. const struct file_operations mbcs_ops = {
  45. .open = mbcs_open,
  46. .llseek = mbcs_sram_llseek,
  47. .read = mbcs_sram_read,
  48. .write = mbcs_sram_write,
  49. .mmap = mbcs_gscr_mmap,
  50. };
  51. struct mbcs_callback_arg {
  52. int minor;
  53. struct cx_dev *cx_dev;
  54. };
  55. static inline void mbcs_getdma_init(struct getdma *gdma)
  56. {
  57. memset(gdma, 0, sizeof(struct getdma));
  58. gdma->DoneIntEnable = 1;
  59. }
  60. static inline void mbcs_putdma_init(struct putdma *pdma)
  61. {
  62. memset(pdma, 0, sizeof(struct putdma));
  63. pdma->DoneIntEnable = 1;
  64. }
  65. static inline void mbcs_algo_init(struct algoblock *algo_soft)
  66. {
  67. memset(algo_soft, 0, sizeof(struct algoblock));
  68. }
  69. static inline void mbcs_getdma_set(void *mmr,
  70. uint64_t hostAddr,
  71. uint64_t localAddr,
  72. uint64_t localRamSel,
  73. uint64_t numPkts,
  74. uint64_t amoEnable,
  75. uint64_t intrEnable,
  76. uint64_t peerIO,
  77. uint64_t amoHostDest,
  78. uint64_t amoModType, uint64_t intrHostDest,
  79. uint64_t intrVector)
  80. {
  81. union dma_control rdma_control;
  82. union dma_amo_dest amo_dest;
  83. union intr_dest intr_dest;
  84. union dma_localaddr local_addr;
  85. union dma_hostaddr host_addr;
  86. rdma_control.dma_control_reg = 0;
  87. amo_dest.dma_amo_dest_reg = 0;
  88. intr_dest.intr_dest_reg = 0;
  89. local_addr.dma_localaddr_reg = 0;
  90. host_addr.dma_hostaddr_reg = 0;
  91. host_addr.dma_sys_addr = hostAddr;
  92. MBCS_MMR_SET(mmr, MBCS_RD_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  93. local_addr.dma_ram_addr = localAddr;
  94. local_addr.dma_ram_sel = localRamSel;
  95. MBCS_MMR_SET(mmr, MBCS_RD_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  96. rdma_control.dma_op_length = numPkts;
  97. rdma_control.done_amo_en = amoEnable;
  98. rdma_control.done_int_en = intrEnable;
  99. rdma_control.pio_mem_n = peerIO;
  100. MBCS_MMR_SET(mmr, MBCS_RD_DMA_CTRL, rdma_control.dma_control_reg);
  101. amo_dest.dma_amo_sys_addr = amoHostDest;
  102. amo_dest.dma_amo_mod_type = amoModType;
  103. MBCS_MMR_SET(mmr, MBCS_RD_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  104. intr_dest.address = intrHostDest;
  105. intr_dest.int_vector = intrVector;
  106. MBCS_MMR_SET(mmr, MBCS_RD_DMA_INT_DEST, intr_dest.intr_dest_reg);
  107. }
  108. static inline void mbcs_putdma_set(void *mmr,
  109. uint64_t hostAddr,
  110. uint64_t localAddr,
  111. uint64_t localRamSel,
  112. uint64_t numPkts,
  113. uint64_t amoEnable,
  114. uint64_t intrEnable,
  115. uint64_t peerIO,
  116. uint64_t amoHostDest,
  117. uint64_t amoModType,
  118. uint64_t intrHostDest, uint64_t intrVector)
  119. {
  120. union dma_control wdma_control;
  121. union dma_amo_dest amo_dest;
  122. union intr_dest intr_dest;
  123. union dma_localaddr local_addr;
  124. union dma_hostaddr host_addr;
  125. wdma_control.dma_control_reg = 0;
  126. amo_dest.dma_amo_dest_reg = 0;
  127. intr_dest.intr_dest_reg = 0;
  128. local_addr.dma_localaddr_reg = 0;
  129. host_addr.dma_hostaddr_reg = 0;
  130. host_addr.dma_sys_addr = hostAddr;
  131. MBCS_MMR_SET(mmr, MBCS_WR_DMA_SYS_ADDR, host_addr.dma_hostaddr_reg);
  132. local_addr.dma_ram_addr = localAddr;
  133. local_addr.dma_ram_sel = localRamSel;
  134. MBCS_MMR_SET(mmr, MBCS_WR_DMA_LOC_ADDR, local_addr.dma_localaddr_reg);
  135. wdma_control.dma_op_length = numPkts;
  136. wdma_control.done_amo_en = amoEnable;
  137. wdma_control.done_int_en = intrEnable;
  138. wdma_control.pio_mem_n = peerIO;
  139. MBCS_MMR_SET(mmr, MBCS_WR_DMA_CTRL, wdma_control.dma_control_reg);
  140. amo_dest.dma_amo_sys_addr = amoHostDest;
  141. amo_dest.dma_amo_mod_type = amoModType;
  142. MBCS_MMR_SET(mmr, MBCS_WR_DMA_AMO_DEST, amo_dest.dma_amo_dest_reg);
  143. intr_dest.address = intrHostDest;
  144. intr_dest.int_vector = intrVector;
  145. MBCS_MMR_SET(mmr, MBCS_WR_DMA_INT_DEST, intr_dest.intr_dest_reg);
  146. }
  147. static inline void mbcs_algo_set(void *mmr,
  148. uint64_t amoHostDest,
  149. uint64_t amoModType,
  150. uint64_t intrHostDest,
  151. uint64_t intrVector, uint64_t algoStepCount)
  152. {
  153. union dma_amo_dest amo_dest;
  154. union intr_dest intr_dest;
  155. union algo_step step;
  156. step.algo_step_reg = 0;
  157. intr_dest.intr_dest_reg = 0;
  158. amo_dest.dma_amo_dest_reg = 0;
  159. amo_dest.dma_amo_sys_addr = amoHostDest;
  160. amo_dest.dma_amo_mod_type = amoModType;
  161. MBCS_MMR_SET(mmr, MBCS_ALG_AMO_DEST, amo_dest.dma_amo_dest_reg);
  162. intr_dest.address = intrHostDest;
  163. intr_dest.int_vector = intrVector;
  164. MBCS_MMR_SET(mmr, MBCS_ALG_INT_DEST, intr_dest.intr_dest_reg);
  165. step.alg_step_cnt = algoStepCount;
  166. MBCS_MMR_SET(mmr, MBCS_ALG_STEP, step.algo_step_reg);
  167. }
  168. static inline int mbcs_getdma_start(struct mbcs_soft *soft)
  169. {
  170. void *mmr_base;
  171. struct getdma *gdma;
  172. uint64_t numPkts;
  173. union cm_control cm_control;
  174. mmr_base = soft->mmr_base;
  175. gdma = &soft->getdma;
  176. /* check that host address got setup */
  177. if (!gdma->hostAddr)
  178. return -1;
  179. numPkts =
  180. (gdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  181. /* program engine */
  182. mbcs_getdma_set(mmr_base, tiocx_dma_addr(gdma->hostAddr),
  183. gdma->localAddr,
  184. (gdma->localAddr < MB2) ? 0 :
  185. (gdma->localAddr < MB4) ? 1 :
  186. (gdma->localAddr < MB6) ? 2 : 3,
  187. numPkts,
  188. gdma->DoneAmoEnable,
  189. gdma->DoneIntEnable,
  190. gdma->peerIO,
  191. gdma->amoHostDest,
  192. gdma->amoModType,
  193. gdma->intrHostDest, gdma->intrVector);
  194. /* start engine */
  195. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  196. cm_control.rd_dma_go = 1;
  197. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  198. return 0;
  199. }
  200. static inline int mbcs_putdma_start(struct mbcs_soft *soft)
  201. {
  202. void *mmr_base;
  203. struct putdma *pdma;
  204. uint64_t numPkts;
  205. union cm_control cm_control;
  206. mmr_base = soft->mmr_base;
  207. pdma = &soft->putdma;
  208. /* check that host address got setup */
  209. if (!pdma->hostAddr)
  210. return -1;
  211. numPkts =
  212. (pdma->bytes + (MBCS_CACHELINE_SIZE - 1)) / MBCS_CACHELINE_SIZE;
  213. /* program engine */
  214. mbcs_putdma_set(mmr_base, tiocx_dma_addr(pdma->hostAddr),
  215. pdma->localAddr,
  216. (pdma->localAddr < MB2) ? 0 :
  217. (pdma->localAddr < MB4) ? 1 :
  218. (pdma->localAddr < MB6) ? 2 : 3,
  219. numPkts,
  220. pdma->DoneAmoEnable,
  221. pdma->DoneIntEnable,
  222. pdma->peerIO,
  223. pdma->amoHostDest,
  224. pdma->amoModType,
  225. pdma->intrHostDest, pdma->intrVector);
  226. /* start engine */
  227. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  228. cm_control.wr_dma_go = 1;
  229. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  230. return 0;
  231. }
  232. static inline int mbcs_algo_start(struct mbcs_soft *soft)
  233. {
  234. struct algoblock *algo_soft = &soft->algo;
  235. void *mmr_base = soft->mmr_base;
  236. union cm_control cm_control;
  237. if (down_interruptible(&soft->algolock))
  238. return -ERESTARTSYS;
  239. atomic_set(&soft->algo_done, 0);
  240. mbcs_algo_set(mmr_base,
  241. algo_soft->amoHostDest,
  242. algo_soft->amoModType,
  243. algo_soft->intrHostDest,
  244. algo_soft->intrVector, algo_soft->algoStepCount);
  245. /* start algorithm */
  246. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  247. cm_control.alg_done_int_en = 1;
  248. cm_control.alg_go = 1;
  249. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  250. up(&soft->algolock);
  251. return 0;
  252. }
  253. static inline ssize_t
  254. do_mbcs_sram_dmawrite(struct mbcs_soft *soft, uint64_t hostAddr,
  255. size_t len, loff_t * off)
  256. {
  257. int rv = 0;
  258. if (down_interruptible(&soft->dmawritelock))
  259. return -ERESTARTSYS;
  260. atomic_set(&soft->dmawrite_done, 0);
  261. soft->putdma.hostAddr = hostAddr;
  262. soft->putdma.localAddr = *off;
  263. soft->putdma.bytes = len;
  264. if (mbcs_putdma_start(soft) < 0) {
  265. DBG(KERN_ALERT "do_mbcs_sram_dmawrite: "
  266. "mbcs_putdma_start failed\n");
  267. rv = -EAGAIN;
  268. goto dmawrite_exit;
  269. }
  270. if (wait_event_interruptible(soft->dmawrite_queue,
  271. atomic_read(&soft->dmawrite_done))) {
  272. rv = -ERESTARTSYS;
  273. goto dmawrite_exit;
  274. }
  275. rv = len;
  276. *off += len;
  277. dmawrite_exit:
  278. up(&soft->dmawritelock);
  279. return rv;
  280. }
  281. static inline ssize_t
  282. do_mbcs_sram_dmaread(struct mbcs_soft *soft, uint64_t hostAddr,
  283. size_t len, loff_t * off)
  284. {
  285. int rv = 0;
  286. if (down_interruptible(&soft->dmareadlock))
  287. return -ERESTARTSYS;
  288. atomic_set(&soft->dmawrite_done, 0);
  289. soft->getdma.hostAddr = hostAddr;
  290. soft->getdma.localAddr = *off;
  291. soft->getdma.bytes = len;
  292. if (mbcs_getdma_start(soft) < 0) {
  293. DBG(KERN_ALERT "mbcs_strategy: mbcs_getdma_start failed\n");
  294. rv = -EAGAIN;
  295. goto dmaread_exit;
  296. }
  297. if (wait_event_interruptible(soft->dmaread_queue,
  298. atomic_read(&soft->dmaread_done))) {
  299. rv = -ERESTARTSYS;
  300. goto dmaread_exit;
  301. }
  302. rv = len;
  303. *off += len;
  304. dmaread_exit:
  305. up(&soft->dmareadlock);
  306. return rv;
  307. }
  308. int mbcs_open(struct inode *ip, struct file *fp)
  309. {
  310. struct mbcs_soft *soft;
  311. int minor;
  312. minor = iminor(ip);
  313. list_for_each_entry(soft, &soft_list, list) {
  314. if (soft->nasid == minor) {
  315. fp->private_data = soft->cxdev;
  316. return 0;
  317. }
  318. }
  319. return -ENODEV;
  320. }
  321. ssize_t mbcs_sram_read(struct file * fp, char __user *buf, size_t len, loff_t * off)
  322. {
  323. struct cx_dev *cx_dev = fp->private_data;
  324. struct mbcs_soft *soft = cx_dev->soft;
  325. uint64_t hostAddr;
  326. int rv = 0;
  327. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  328. if (hostAddr == 0)
  329. return -ENOMEM;
  330. rv = do_mbcs_sram_dmawrite(soft, hostAddr, len, off);
  331. if (rv < 0)
  332. goto exit;
  333. if (copy_to_user(buf, (void *)hostAddr, len))
  334. rv = -EFAULT;
  335. exit:
  336. free_pages(hostAddr, get_order(len));
  337. return rv;
  338. }
  339. ssize_t
  340. mbcs_sram_write(struct file * fp, const char __user *buf, size_t len, loff_t * off)
  341. {
  342. struct cx_dev *cx_dev = fp->private_data;
  343. struct mbcs_soft *soft = cx_dev->soft;
  344. uint64_t hostAddr;
  345. int rv = 0;
  346. hostAddr = __get_dma_pages(GFP_KERNEL, get_order(len));
  347. if (hostAddr == 0)
  348. return -ENOMEM;
  349. if (copy_from_user((void *)hostAddr, buf, len)) {
  350. rv = -EFAULT;
  351. goto exit;
  352. }
  353. rv = do_mbcs_sram_dmaread(soft, hostAddr, len, off);
  354. exit:
  355. free_pages(hostAddr, get_order(len));
  356. return rv;
  357. }
  358. loff_t mbcs_sram_llseek(struct file * filp, loff_t off, int whence)
  359. {
  360. loff_t newpos;
  361. switch (whence) {
  362. case SEEK_SET:
  363. newpos = off;
  364. break;
  365. case SEEK_CUR:
  366. newpos = filp->f_pos + off;
  367. break;
  368. case SEEK_END:
  369. newpos = MBCS_SRAM_SIZE + off;
  370. break;
  371. default: /* can't happen */
  372. return -EINVAL;
  373. }
  374. if (newpos < 0)
  375. return -EINVAL;
  376. filp->f_pos = newpos;
  377. return newpos;
  378. }
  379. static uint64_t mbcs_pioaddr(struct mbcs_soft *soft, uint64_t offset)
  380. {
  381. uint64_t mmr_base;
  382. mmr_base = (uint64_t) (soft->mmr_base + offset);
  383. return mmr_base;
  384. }
  385. static void mbcs_debug_pioaddr_set(struct mbcs_soft *soft)
  386. {
  387. soft->debug_addr = mbcs_pioaddr(soft, MBCS_DEBUG_START);
  388. }
  389. static void mbcs_gscr_pioaddr_set(struct mbcs_soft *soft)
  390. {
  391. soft->gscr_addr = mbcs_pioaddr(soft, MBCS_GSCR_START);
  392. }
  393. int mbcs_gscr_mmap(struct file *fp, struct vm_area_struct *vma)
  394. {
  395. struct cx_dev *cx_dev = fp->private_data;
  396. struct mbcs_soft *soft = cx_dev->soft;
  397. if (vma->vm_pgoff != 0)
  398. return -EINVAL;
  399. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  400. /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */
  401. if (remap_pfn_range(vma,
  402. vma->vm_start,
  403. __pa(soft->gscr_addr) >> PAGE_SHIFT,
  404. PAGE_SIZE,
  405. vma->vm_page_prot))
  406. return -EAGAIN;
  407. return 0;
  408. }
  409. /**
  410. * mbcs_completion_intr_handler - Primary completion handler.
  411. * @irq: irq
  412. * @arg: soft struct for device
  413. *
  414. */
  415. static irqreturn_t
  416. mbcs_completion_intr_handler(int irq, void *arg)
  417. {
  418. struct mbcs_soft *soft = (struct mbcs_soft *)arg;
  419. void *mmr_base;
  420. union cm_status cm_status;
  421. union cm_control cm_control;
  422. mmr_base = soft->mmr_base;
  423. cm_status.cm_status_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_STATUS);
  424. if (cm_status.rd_dma_done) {
  425. /* stop dma-read engine, clear status */
  426. cm_control.cm_control_reg =
  427. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  428. cm_control.rd_dma_clr = 1;
  429. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  430. cm_control.cm_control_reg);
  431. atomic_set(&soft->dmaread_done, 1);
  432. wake_up(&soft->dmaread_queue);
  433. }
  434. if (cm_status.wr_dma_done) {
  435. /* stop dma-write engine, clear status */
  436. cm_control.cm_control_reg =
  437. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  438. cm_control.wr_dma_clr = 1;
  439. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  440. cm_control.cm_control_reg);
  441. atomic_set(&soft->dmawrite_done, 1);
  442. wake_up(&soft->dmawrite_queue);
  443. }
  444. if (cm_status.alg_done) {
  445. /* clear status */
  446. cm_control.cm_control_reg =
  447. MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  448. cm_control.alg_done_clr = 1;
  449. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL,
  450. cm_control.cm_control_reg);
  451. atomic_set(&soft->algo_done, 1);
  452. wake_up(&soft->algo_queue);
  453. }
  454. return IRQ_HANDLED;
  455. }
  456. /**
  457. * mbcs_intr_alloc - Allocate interrupts.
  458. * @dev: device pointer
  459. *
  460. */
  461. static int mbcs_intr_alloc(struct cx_dev *dev)
  462. {
  463. struct sn_irq_info *sn_irq;
  464. struct mbcs_soft *soft;
  465. struct getdma *getdma;
  466. struct putdma *putdma;
  467. struct algoblock *algo;
  468. soft = dev->soft;
  469. getdma = &soft->getdma;
  470. putdma = &soft->putdma;
  471. algo = &soft->algo;
  472. soft->get_sn_irq = NULL;
  473. soft->put_sn_irq = NULL;
  474. soft->algo_sn_irq = NULL;
  475. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  476. if (sn_irq == NULL)
  477. return -EAGAIN;
  478. soft->get_sn_irq = sn_irq;
  479. getdma->intrHostDest = sn_irq->irq_xtalkaddr;
  480. getdma->intrVector = sn_irq->irq_irq;
  481. if (request_irq(sn_irq->irq_irq,
  482. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  483. "MBCS get intr", (void *)soft)) {
  484. tiocx_irq_free(soft->get_sn_irq);
  485. return -EAGAIN;
  486. }
  487. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  488. if (sn_irq == NULL) {
  489. free_irq(soft->get_sn_irq->irq_irq, soft);
  490. tiocx_irq_free(soft->get_sn_irq);
  491. return -EAGAIN;
  492. }
  493. soft->put_sn_irq = sn_irq;
  494. putdma->intrHostDest = sn_irq->irq_xtalkaddr;
  495. putdma->intrVector = sn_irq->irq_irq;
  496. if (request_irq(sn_irq->irq_irq,
  497. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  498. "MBCS put intr", (void *)soft)) {
  499. tiocx_irq_free(soft->put_sn_irq);
  500. free_irq(soft->get_sn_irq->irq_irq, soft);
  501. tiocx_irq_free(soft->get_sn_irq);
  502. return -EAGAIN;
  503. }
  504. sn_irq = tiocx_irq_alloc(dev->cx_id.nasid, TIOCX_CORELET, -1, -1, -1);
  505. if (sn_irq == NULL) {
  506. free_irq(soft->put_sn_irq->irq_irq, soft);
  507. tiocx_irq_free(soft->put_sn_irq);
  508. free_irq(soft->get_sn_irq->irq_irq, soft);
  509. tiocx_irq_free(soft->get_sn_irq);
  510. return -EAGAIN;
  511. }
  512. soft->algo_sn_irq = sn_irq;
  513. algo->intrHostDest = sn_irq->irq_xtalkaddr;
  514. algo->intrVector = sn_irq->irq_irq;
  515. if (request_irq(sn_irq->irq_irq,
  516. (void *)mbcs_completion_intr_handler, IRQF_SHARED,
  517. "MBCS algo intr", (void *)soft)) {
  518. tiocx_irq_free(soft->algo_sn_irq);
  519. free_irq(soft->put_sn_irq->irq_irq, soft);
  520. tiocx_irq_free(soft->put_sn_irq);
  521. free_irq(soft->get_sn_irq->irq_irq, soft);
  522. tiocx_irq_free(soft->get_sn_irq);
  523. return -EAGAIN;
  524. }
  525. return 0;
  526. }
  527. /**
  528. * mbcs_intr_dealloc - Remove interrupts.
  529. * @dev: device pointer
  530. *
  531. */
  532. static void mbcs_intr_dealloc(struct cx_dev *dev)
  533. {
  534. struct mbcs_soft *soft;
  535. soft = dev->soft;
  536. free_irq(soft->get_sn_irq->irq_irq, soft);
  537. tiocx_irq_free(soft->get_sn_irq);
  538. free_irq(soft->put_sn_irq->irq_irq, soft);
  539. tiocx_irq_free(soft->put_sn_irq);
  540. free_irq(soft->algo_sn_irq->irq_irq, soft);
  541. tiocx_irq_free(soft->algo_sn_irq);
  542. }
  543. static inline int mbcs_hw_init(struct mbcs_soft *soft)
  544. {
  545. void *mmr_base = soft->mmr_base;
  546. union cm_control cm_control;
  547. union cm_req_timeout cm_req_timeout;
  548. uint64_t err_stat;
  549. cm_req_timeout.cm_req_timeout_reg =
  550. MBCS_MMR_GET(mmr_base, MBCS_CM_REQ_TOUT);
  551. cm_req_timeout.time_out = MBCS_CM_CONTROL_REQ_TOUT_MASK;
  552. MBCS_MMR_SET(mmr_base, MBCS_CM_REQ_TOUT,
  553. cm_req_timeout.cm_req_timeout_reg);
  554. mbcs_gscr_pioaddr_set(soft);
  555. mbcs_debug_pioaddr_set(soft);
  556. /* clear errors */
  557. err_stat = MBCS_MMR_GET(mmr_base, MBCS_CM_ERR_STAT);
  558. MBCS_MMR_SET(mmr_base, MBCS_CM_CLR_ERR_STAT, err_stat);
  559. MBCS_MMR_ZERO(mmr_base, MBCS_CM_ERROR_DETAIL1);
  560. /* enable interrupts */
  561. /* turn off 2^23 (INT_EN_PIO_REQ_ADDR_INV) */
  562. MBCS_MMR_SET(mmr_base, MBCS_CM_ERR_INT_EN, 0x3ffffff7e00ffUL);
  563. /* arm status regs and clear engines */
  564. cm_control.cm_control_reg = MBCS_MMR_GET(mmr_base, MBCS_CM_CONTROL);
  565. cm_control.rearm_stat_regs = 1;
  566. cm_control.alg_clr = 1;
  567. cm_control.wr_dma_clr = 1;
  568. cm_control.rd_dma_clr = 1;
  569. MBCS_MMR_SET(mmr_base, MBCS_CM_CONTROL, cm_control.cm_control_reg);
  570. return 0;
  571. }
  572. static ssize_t show_algo(struct device *dev, struct device_attribute *attr, char *buf)
  573. {
  574. struct cx_dev *cx_dev = to_cx_dev(dev);
  575. struct mbcs_soft *soft = cx_dev->soft;
  576. uint64_t debug0;
  577. /*
  578. * By convention, the first debug register contains the
  579. * algorithm number and revision.
  580. */
  581. debug0 = *(uint64_t *) soft->debug_addr;
  582. return sprintf(buf, "0x%lx 0x%lx\n",
  583. (debug0 >> 32), (debug0 & 0xffffffff));
  584. }
  585. static ssize_t store_algo(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
  586. {
  587. int n;
  588. struct cx_dev *cx_dev = to_cx_dev(dev);
  589. struct mbcs_soft *soft = cx_dev->soft;
  590. if (count <= 0)
  591. return 0;
  592. n = simple_strtoul(buf, NULL, 0);
  593. if (n == 1) {
  594. mbcs_algo_start(soft);
  595. if (wait_event_interruptible(soft->algo_queue,
  596. atomic_read(&soft->algo_done)))
  597. return -ERESTARTSYS;
  598. }
  599. return count;
  600. }
  601. DEVICE_ATTR(algo, 0644, show_algo, store_algo);
  602. /**
  603. * mbcs_probe - Initialize for device
  604. * @dev: device pointer
  605. * @device_id: id table pointer
  606. *
  607. */
  608. static int mbcs_probe(struct cx_dev *dev, const struct cx_device_id *id)
  609. {
  610. struct mbcs_soft *soft;
  611. dev->soft = NULL;
  612. soft = kzalloc(sizeof(struct mbcs_soft), GFP_KERNEL);
  613. if (soft == NULL)
  614. return -ENOMEM;
  615. soft->nasid = dev->cx_id.nasid;
  616. list_add(&soft->list, &soft_list);
  617. soft->mmr_base = (void *)tiocx_swin_base(dev->cx_id.nasid);
  618. dev->soft = soft;
  619. soft->cxdev = dev;
  620. init_waitqueue_head(&soft->dmawrite_queue);
  621. init_waitqueue_head(&soft->dmaread_queue);
  622. init_waitqueue_head(&soft->algo_queue);
  623. init_MUTEX(&soft->dmawritelock);
  624. init_MUTEX(&soft->dmareadlock);
  625. init_MUTEX(&soft->algolock);
  626. mbcs_getdma_init(&soft->getdma);
  627. mbcs_putdma_init(&soft->putdma);
  628. mbcs_algo_init(&soft->algo);
  629. mbcs_hw_init(soft);
  630. /* Allocate interrupts */
  631. mbcs_intr_alloc(dev);
  632. device_create_file(&dev->dev, &dev_attr_algo);
  633. return 0;
  634. }
  635. static int mbcs_remove(struct cx_dev *dev)
  636. {
  637. if (dev->soft) {
  638. mbcs_intr_dealloc(dev);
  639. kfree(dev->soft);
  640. }
  641. device_remove_file(&dev->dev, &dev_attr_algo);
  642. return 0;
  643. }
  644. const struct cx_device_id __devinitdata mbcs_id_table[] = {
  645. {
  646. .part_num = MBCS_PART_NUM,
  647. .mfg_num = MBCS_MFG_NUM,
  648. },
  649. {
  650. .part_num = MBCS_PART_NUM_ALG0,
  651. .mfg_num = MBCS_MFG_NUM,
  652. },
  653. {0, 0}
  654. };
  655. MODULE_DEVICE_TABLE(cx, mbcs_id_table);
  656. struct cx_drv mbcs_driver = {
  657. .name = DEVICE_NAME,
  658. .id_table = mbcs_id_table,
  659. .probe = mbcs_probe,
  660. .remove = mbcs_remove,
  661. };
  662. static void __exit mbcs_exit(void)
  663. {
  664. int rv;
  665. rv = unregister_chrdev(mbcs_major, DEVICE_NAME);
  666. if (rv < 0)
  667. DBG(KERN_ALERT "Error in unregister_chrdev: %d\n", rv);
  668. cx_driver_unregister(&mbcs_driver);
  669. }
  670. static int __init mbcs_init(void)
  671. {
  672. int rv;
  673. if (!ia64_platform_is("sn2"))
  674. return -ENODEV;
  675. // Put driver into chrdevs[]. Get major number.
  676. rv = register_chrdev(mbcs_major, DEVICE_NAME, &mbcs_ops);
  677. if (rv < 0) {
  678. DBG(KERN_ALERT "mbcs_init: can't get major number. %d\n", rv);
  679. return rv;
  680. }
  681. mbcs_major = rv;
  682. return cx_driver_register(&mbcs_driver);
  683. }
  684. module_init(mbcs_init);
  685. module_exit(mbcs_exit);
  686. MODULE_AUTHOR("Bruce Losure <blosure@sgi.com>");
  687. MODULE_DESCRIPTION("Driver for MOATB Core Services");
  688. MODULE_LICENSE("GPL");