cs5535_gpio.c 5.6 KB

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  1. /*
  2. * AMD CS5535/CS5536 GPIO driver.
  3. * Allows a user space process to play with the GPIO pins.
  4. *
  5. * Copyright (c) 2005 Ben Gardner <bgardner@wabtec.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the smems of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. */
  11. #include <linux/fs.h>
  12. #include <linux/module.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/cdev.h>
  17. #include <linux/ioport.h>
  18. #include <linux/pci.h>
  19. #include <asm/uaccess.h>
  20. #include <asm/io.h>
  21. #define NAME "cs5535_gpio"
  22. MODULE_AUTHOR("Ben Gardner <bgardner@wabtec.com>");
  23. MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO Pin Driver");
  24. MODULE_LICENSE("GPL");
  25. static int major;
  26. module_param(major, int, 0);
  27. MODULE_PARM_DESC(major, "Major device number");
  28. static ulong mask;
  29. module_param(mask, ulong, 0);
  30. MODULE_PARM_DESC(mask, "GPIO channel mask");
  31. #define MSR_LBAR_GPIO 0x5140000C
  32. static u32 gpio_base;
  33. static struct pci_device_id divil_pci[] = {
  34. { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
  35. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
  36. { } /* NULL entry */
  37. };
  38. static struct cdev cs5535_gpio_cdev;
  39. /* reserve 32 entries even though some aren't usable */
  40. #define CS5535_GPIO_COUNT 32
  41. /* IO block size */
  42. #define CS5535_GPIO_SIZE 256
  43. struct gpio_regmap {
  44. u32 rd_offset;
  45. u32 wr_offset;
  46. char on;
  47. char off;
  48. };
  49. static struct gpio_regmap rm[] =
  50. {
  51. { 0x30, 0x00, '1', '0' }, /* GPIOx_READ_BACK / GPIOx_OUT_VAL */
  52. { 0x20, 0x20, 'I', 'i' }, /* GPIOx_IN_EN */
  53. { 0x04, 0x04, 'O', 'o' }, /* GPIOx_OUT_EN */
  54. { 0x08, 0x08, 't', 'T' }, /* GPIOx_OUT_OD_EN */
  55. { 0x18, 0x18, 'P', 'p' }, /* GPIOx_OUT_PU_EN */
  56. { 0x1c, 0x1c, 'D', 'd' }, /* GPIOx_OUT_PD_EN */
  57. };
  58. /**
  59. * Gets the register offset for the GPIO bank.
  60. * Low (0-15) starts at 0x00, high (16-31) starts at 0x80
  61. */
  62. static inline u32 cs5535_lowhigh_base(int reg)
  63. {
  64. return (reg & 0x10) << 3;
  65. }
  66. static ssize_t cs5535_gpio_write(struct file *file, const char __user *data,
  67. size_t len, loff_t *ppos)
  68. {
  69. u32 m = iminor(file->f_path.dentry->d_inode);
  70. int i, j;
  71. u32 base = gpio_base + cs5535_lowhigh_base(m);
  72. u32 m0, m1;
  73. char c;
  74. /**
  75. * Creates the mask for atomic bit programming.
  76. * The high 16 bits and the low 16 bits are used to set the mask.
  77. * For example, GPIO 15 maps to 31,15: 0,1 => On; 1,0=> Off
  78. */
  79. m1 = 1 << (m & 0x0F);
  80. m0 = m1 << 16;
  81. for (i = 0; i < len; ++i) {
  82. if (get_user(c, data+i))
  83. return -EFAULT;
  84. for (j = 0; j < ARRAY_SIZE(rm); j++) {
  85. if (c == rm[j].on) {
  86. outl(m1, base + rm[j].wr_offset);
  87. break;
  88. } else if (c == rm[j].off) {
  89. outl(m0, base + rm[j].wr_offset);
  90. break;
  91. }
  92. }
  93. }
  94. *ppos = 0;
  95. return len;
  96. }
  97. static ssize_t cs5535_gpio_read(struct file *file, char __user *buf,
  98. size_t len, loff_t *ppos)
  99. {
  100. u32 m = iminor(file->f_path.dentry->d_inode);
  101. u32 base = gpio_base + cs5535_lowhigh_base(m);
  102. int rd_bit = 1 << (m & 0x0f);
  103. int i;
  104. char ch;
  105. ssize_t count = 0;
  106. if (*ppos >= ARRAY_SIZE(rm))
  107. return 0;
  108. for (i = *ppos; (i < (*ppos + len)) && (i < ARRAY_SIZE(rm)); i++) {
  109. ch = (inl(base + rm[i].rd_offset) & rd_bit) ?
  110. rm[i].on : rm[i].off;
  111. if (put_user(ch, buf+count))
  112. return -EFAULT;
  113. count++;
  114. }
  115. /* add a line-feed if there is room */
  116. if ((i == ARRAY_SIZE(rm)) && (count < len)) {
  117. put_user('\n', buf + count);
  118. count++;
  119. }
  120. *ppos += count;
  121. return count;
  122. }
  123. static int cs5535_gpio_open(struct inode *inode, struct file *file)
  124. {
  125. u32 m = iminor(inode);
  126. /* the mask says which pins are usable by this driver */
  127. if ((mask & (1 << m)) == 0)
  128. return -EINVAL;
  129. return nonseekable_open(inode, file);
  130. }
  131. static const struct file_operations cs5535_gpio_fops = {
  132. .owner = THIS_MODULE,
  133. .write = cs5535_gpio_write,
  134. .read = cs5535_gpio_read,
  135. .open = cs5535_gpio_open
  136. };
  137. static int __init cs5535_gpio_init(void)
  138. {
  139. dev_t dev_id;
  140. u32 low, hi;
  141. int retval;
  142. if (pci_dev_present(divil_pci) == 0) {
  143. printk(KERN_WARNING NAME ": DIVIL not found\n");
  144. return -ENODEV;
  145. }
  146. /* Grab the GPIO I/O range */
  147. rdmsr(MSR_LBAR_GPIO, low, hi);
  148. /* Check the mask and whether GPIO is enabled (sanity check) */
  149. if (hi != 0x0000f001) {
  150. printk(KERN_WARNING NAME ": GPIO not enabled\n");
  151. return -ENODEV;
  152. }
  153. /* Mask off the IO base address */
  154. gpio_base = low & 0x0000ff00;
  155. /**
  156. * Some GPIO pins
  157. * 31-29,23 : reserved (always mask out)
  158. * 28 : Power Button
  159. * 26 : PME#
  160. * 22-16 : LPC
  161. * 14,15 : SMBus
  162. * 9,8 : UART1
  163. * 7 : PCI INTB
  164. * 3,4 : UART2/DDC
  165. * 2 : IDE_IRQ0
  166. * 0 : PCI INTA
  167. *
  168. * If a mask was not specified, be conservative and only allow:
  169. * 1,2,5,6,10-13,24,25,27
  170. */
  171. if (mask != 0)
  172. mask &= 0x1f7fffff;
  173. else
  174. mask = 0x0b003c66;
  175. if (request_region(gpio_base, CS5535_GPIO_SIZE, NAME) == 0) {
  176. printk(KERN_ERR NAME ": can't allocate I/O for GPIO\n");
  177. return -ENODEV;
  178. }
  179. if (major) {
  180. dev_id = MKDEV(major, 0);
  181. retval = register_chrdev_region(dev_id, CS5535_GPIO_COUNT,
  182. NAME);
  183. } else {
  184. retval = alloc_chrdev_region(&dev_id, 0, CS5535_GPIO_COUNT,
  185. NAME);
  186. major = MAJOR(dev_id);
  187. }
  188. if (retval) {
  189. release_region(gpio_base, CS5535_GPIO_SIZE);
  190. return -1;
  191. }
  192. printk(KERN_DEBUG NAME ": base=%#x mask=%#lx major=%d\n",
  193. gpio_base, mask, major);
  194. cdev_init(&cs5535_gpio_cdev, &cs5535_gpio_fops);
  195. cdev_add(&cs5535_gpio_cdev, dev_id, CS5535_GPIO_COUNT);
  196. return 0;
  197. }
  198. static void __exit cs5535_gpio_cleanup(void)
  199. {
  200. dev_t dev_id = MKDEV(major, 0);
  201. cdev_del(&cs5535_gpio_cdev);
  202. unregister_chrdev_region(dev_id, CS5535_GPIO_COUNT);
  203. release_region(gpio_base, CS5535_GPIO_SIZE);
  204. }
  205. module_init(cs5535_gpio_init);
  206. module_exit(cs5535_gpio_cleanup);