cd1865.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263
  1. /*
  2. * linux/drivers/char/cd1865.h -- Definitions relating to the CD1865
  3. * for the Specialix IO8+ multiport serial driver.
  4. *
  5. * Copyright (C) 1997 Roger Wolff (R.E.Wolff@BitWizard.nl)
  6. * Copyright (C) 1994-1996 Dmitry Gorodchanin (pgmdsg@ibi.com)
  7. *
  8. * Specialix pays for the development and support of this driver.
  9. * Please DO contact io8-linux@specialix.co.uk if you require
  10. * support.
  11. *
  12. * This driver was developped in the BitWizard linux device
  13. * driver service. If you require a linux device driver for your
  14. * product, please contact devices@BitWizard.nl for a quote.
  15. *
  16. */
  17. /*
  18. * Definitions for Driving CD180/CD1864/CD1865 based eightport serial cards.
  19. */
  20. /* Values of choice for Interrupt ACKs */
  21. /* These values are "obligatory" if you use the register based
  22. * interrupt acknowledgements. See page 99-101 of V2.0 of the CD1865
  23. * databook */
  24. #define SX_ACK_MINT 0x75 /* goes to PILR1 */
  25. #define SX_ACK_TINT 0x76 /* goes to PILR2 */
  26. #define SX_ACK_RINT 0x77 /* goes to PILR3 */
  27. /* Chip ID (is used when chips ar daisy chained.) */
  28. #define SX_ID 0x10
  29. /* Definitions for Cirrus Logic CL-CD186x 8-port async mux chip */
  30. #define CD186x_NCH 8 /* Total number of channels */
  31. #define CD186x_TPC 16 /* Ticks per character */
  32. #define CD186x_NFIFO 8 /* TX FIFO size */
  33. /* Global registers */
  34. #define CD186x_GIVR 0x40 /* Global Interrupt Vector Register */
  35. #define CD186x_GICR 0x41 /* Global Interrupting Channel Register */
  36. #define CD186x_PILR1 0x61 /* Priority Interrupt Level Register 1 */
  37. #define CD186x_PILR2 0x62 /* Priority Interrupt Level Register 2 */
  38. #define CD186x_PILR3 0x63 /* Priority Interrupt Level Register 3 */
  39. #define CD186x_CAR 0x64 /* Channel Access Register */
  40. #define CD186x_SRSR 0x65 /* Channel Access Register */
  41. #define CD186x_GFRCR 0x6b /* Global Firmware Revision Code Register */
  42. #define CD186x_PPRH 0x70 /* Prescaler Period Register High */
  43. #define CD186x_PPRL 0x71 /* Prescaler Period Register Low */
  44. #define CD186x_RDR 0x78 /* Receiver Data Register */
  45. #define CD186x_RCSR 0x7a /* Receiver Character Status Register */
  46. #define CD186x_TDR 0x7b /* Transmit Data Register */
  47. #define CD186x_EOIR 0x7f /* End of Interrupt Register */
  48. #define CD186x_MRAR 0x75 /* Modem Request Acknowledge register */
  49. #define CD186x_TRAR 0x76 /* Transmit Request Acknowledge register */
  50. #define CD186x_RRAR 0x77 /* Receive Request Acknowledge register */
  51. #define CD186x_SRCR 0x66 /* Service Request Configuration register */
  52. /* Channel Registers */
  53. #define CD186x_CCR 0x01 /* Channel Command Register */
  54. #define CD186x_IER 0x02 /* Interrupt Enable Register */
  55. #define CD186x_COR1 0x03 /* Channel Option Register 1 */
  56. #define CD186x_COR2 0x04 /* Channel Option Register 2 */
  57. #define CD186x_COR3 0x05 /* Channel Option Register 3 */
  58. #define CD186x_CCSR 0x06 /* Channel Control Status Register */
  59. #define CD186x_RDCR 0x07 /* Receive Data Count Register */
  60. #define CD186x_SCHR1 0x09 /* Special Character Register 1 */
  61. #define CD186x_SCHR2 0x0a /* Special Character Register 2 */
  62. #define CD186x_SCHR3 0x0b /* Special Character Register 3 */
  63. #define CD186x_SCHR4 0x0c /* Special Character Register 4 */
  64. #define CD186x_MCOR1 0x10 /* Modem Change Option 1 Register */
  65. #define CD186x_MCOR2 0x11 /* Modem Change Option 2 Register */
  66. #define CD186x_MCR 0x12 /* Modem Change Register */
  67. #define CD186x_RTPR 0x18 /* Receive Timeout Period Register */
  68. #define CD186x_MSVR 0x28 /* Modem Signal Value Register */
  69. #define CD186x_MSVRTS 0x29 /* Modem Signal Value Register */
  70. #define CD186x_MSVDTR 0x2a /* Modem Signal Value Register */
  71. #define CD186x_RBPRH 0x31 /* Receive Baud Rate Period Register High */
  72. #define CD186x_RBPRL 0x32 /* Receive Baud Rate Period Register Low */
  73. #define CD186x_TBPRH 0x39 /* Transmit Baud Rate Period Register High */
  74. #define CD186x_TBPRL 0x3a /* Transmit Baud Rate Period Register Low */
  75. /* Global Interrupt Vector Register (R/W) */
  76. #define GIVR_ITMASK 0x07 /* Interrupt type mask */
  77. #define GIVR_IT_MODEM 0x01 /* Modem Signal Change Interrupt */
  78. #define GIVR_IT_TX 0x02 /* Transmit Data Interrupt */
  79. #define GIVR_IT_RCV 0x03 /* Receive Good Data Interrupt */
  80. #define GIVR_IT_REXC 0x07 /* Receive Exception Interrupt */
  81. /* Global Interrupt Channel Register (R/W) */
  82. #define GICR_CHAN 0x1c /* Channel Number Mask */
  83. #define GICR_CHAN_OFF 2 /* Channel Number shift */
  84. /* Channel Address Register (R/W) */
  85. #define CAR_CHAN 0x07 /* Channel Number Mask */
  86. #define CAR_A7 0x08 /* A7 Address Extension (unused) */
  87. /* Receive Character Status Register (R/O) */
  88. #define RCSR_TOUT 0x80 /* Rx Timeout */
  89. #define RCSR_SCDET 0x70 /* Special Character Detected Mask */
  90. #define RCSR_NO_SC 0x00 /* No Special Characters Detected */
  91. #define RCSR_SC_1 0x10 /* Special Char 1 (or 1 & 3) Detected */
  92. #define RCSR_SC_2 0x20 /* Special Char 2 (or 2 & 4) Detected */
  93. #define RCSR_SC_3 0x30 /* Special Char 3 Detected */
  94. #define RCSR_SC_4 0x40 /* Special Char 4 Detected */
  95. #define RCSR_BREAK 0x08 /* Break has been detected */
  96. #define RCSR_PE 0x04 /* Parity Error */
  97. #define RCSR_FE 0x02 /* Frame Error */
  98. #define RCSR_OE 0x01 /* Overrun Error */
  99. /* Channel Command Register (R/W) (commands in groups can be OR-ed) */
  100. #define CCR_HARDRESET 0x81 /* Reset the chip */
  101. #define CCR_SOFTRESET 0x80 /* Soft Channel Reset */
  102. #define CCR_CORCHG1 0x42 /* Channel Option Register 1 Changed */
  103. #define CCR_CORCHG2 0x44 /* Channel Option Register 2 Changed */
  104. #define CCR_CORCHG3 0x48 /* Channel Option Register 3 Changed */
  105. #define CCR_SSCH1 0x21 /* Send Special Character 1 */
  106. #define CCR_SSCH2 0x22 /* Send Special Character 2 */
  107. #define CCR_SSCH3 0x23 /* Send Special Character 3 */
  108. #define CCR_SSCH4 0x24 /* Send Special Character 4 */
  109. #define CCR_TXEN 0x18 /* Enable Transmitter */
  110. #define CCR_RXEN 0x12 /* Enable Receiver */
  111. #define CCR_TXDIS 0x14 /* Disable Transmitter */
  112. #define CCR_RXDIS 0x11 /* Disable Receiver */
  113. /* Interrupt Enable Register (R/W) */
  114. #define IER_DSR 0x80 /* Enable interrupt on DSR change */
  115. #define IER_CD 0x40 /* Enable interrupt on CD change */
  116. #define IER_CTS 0x20 /* Enable interrupt on CTS change */
  117. #define IER_RXD 0x10 /* Enable interrupt on Receive Data */
  118. #define IER_RXSC 0x08 /* Enable interrupt on Receive Spec. Char */
  119. #define IER_TXRDY 0x04 /* Enable interrupt on TX FIFO empty */
  120. #define IER_TXEMPTY 0x02 /* Enable interrupt on TX completely empty */
  121. #define IER_RET 0x01 /* Enable interrupt on RX Exc. Timeout */
  122. /* Channel Option Register 1 (R/W) */
  123. #define COR1_ODDP 0x80 /* Odd Parity */
  124. #define COR1_PARMODE 0x60 /* Parity Mode mask */
  125. #define COR1_NOPAR 0x00 /* No Parity */
  126. #define COR1_FORCEPAR 0x20 /* Force Parity */
  127. #define COR1_NORMPAR 0x40 /* Normal Parity */
  128. #define COR1_IGNORE 0x10 /* Ignore Parity on RX */
  129. #define COR1_STOPBITS 0x0c /* Number of Stop Bits */
  130. #define COR1_1SB 0x00 /* 1 Stop Bit */
  131. #define COR1_15SB 0x04 /* 1.5 Stop Bits */
  132. #define COR1_2SB 0x08 /* 2 Stop Bits */
  133. #define COR1_CHARLEN 0x03 /* Character Length */
  134. #define COR1_5BITS 0x00 /* 5 bits */
  135. #define COR1_6BITS 0x01 /* 6 bits */
  136. #define COR1_7BITS 0x02 /* 7 bits */
  137. #define COR1_8BITS 0x03 /* 8 bits */
  138. /* Channel Option Register 2 (R/W) */
  139. #define COR2_IXM 0x80 /* Implied XON mode */
  140. #define COR2_TXIBE 0x40 /* Enable In-Band (XON/XOFF) Flow Control */
  141. #define COR2_ETC 0x20 /* Embedded Tx Commands Enable */
  142. #define COR2_LLM 0x10 /* Local Loopback Mode */
  143. #define COR2_RLM 0x08 /* Remote Loopback Mode */
  144. #define COR2_RTSAO 0x04 /* RTS Automatic Output Enable */
  145. #define COR2_CTSAE 0x02 /* CTS Automatic Enable */
  146. #define COR2_DSRAE 0x01 /* DSR Automatic Enable */
  147. /* Channel Option Register 3 (R/W) */
  148. #define COR3_XONCH 0x80 /* XON is a pair of characters (1 & 3) */
  149. #define COR3_XOFFCH 0x40 /* XOFF is a pair of characters (2 & 4) */
  150. #define COR3_FCT 0x20 /* Flow-Control Transparency Mode */
  151. #define COR3_SCDE 0x10 /* Special Character Detection Enable */
  152. #define COR3_RXTH 0x0f /* RX FIFO Threshold value (1-8) */
  153. /* Channel Control Status Register (R/O) */
  154. #define CCSR_RXEN 0x80 /* Receiver Enabled */
  155. #define CCSR_RXFLOFF 0x40 /* Receive Flow Off (XOFF was sent) */
  156. #define CCSR_RXFLON 0x20 /* Receive Flow On (XON was sent) */
  157. #define CCSR_TXEN 0x08 /* Transmitter Enabled */
  158. #define CCSR_TXFLOFF 0x04 /* Transmit Flow Off (got XOFF) */
  159. #define CCSR_TXFLON 0x02 /* Transmit Flow On (got XON) */
  160. /* Modem Change Option Register 1 (R/W) */
  161. #define MCOR1_DSRZD 0x80 /* Detect 0->1 transition of DSR */
  162. #define MCOR1_CDZD 0x40 /* Detect 0->1 transition of CD */
  163. #define MCOR1_CTSZD 0x20 /* Detect 0->1 transition of CTS */
  164. #define MCOR1_DTRTH 0x0f /* Auto DTR flow control Threshold (1-8) */
  165. #define MCOR1_NODTRFC 0x0 /* Automatic DTR flow control disabled */
  166. /* Modem Change Option Register 2 (R/W) */
  167. #define MCOR2_DSROD 0x80 /* Detect 1->0 transition of DSR */
  168. #define MCOR2_CDOD 0x40 /* Detect 1->0 transition of CD */
  169. #define MCOR2_CTSOD 0x20 /* Detect 1->0 transition of CTS */
  170. /* Modem Change Register (R/W) */
  171. #define MCR_DSRCHG 0x80 /* DSR Changed */
  172. #define MCR_CDCHG 0x40 /* CD Changed */
  173. #define MCR_CTSCHG 0x20 /* CTS Changed */
  174. /* Modem Signal Value Register (R/W) */
  175. #define MSVR_DSR 0x80 /* Current state of DSR input */
  176. #define MSVR_CD 0x40 /* Current state of CD input */
  177. #define MSVR_CTS 0x20 /* Current state of CTS input */
  178. #define MSVR_DTR 0x02 /* Current state of DTR output */
  179. #define MSVR_RTS 0x01 /* Current state of RTS output */
  180. /* Escape characters */
  181. #define CD186x_C_ESC 0x00 /* Escape character */
  182. #define CD186x_C_SBRK 0x81 /* Start sending BREAK */
  183. #define CD186x_C_DELAY 0x82 /* Delay output */
  184. #define CD186x_C_EBRK 0x83 /* Stop sending BREAK */
  185. #define SRSR_RREQint 0x10 /* This chip wants "rec" serviced */
  186. #define SRSR_TREQint 0x04 /* This chip wants "transmit" serviced */
  187. #define SRSR_MREQint 0x01 /* This chip wants "mdm change" serviced */
  188. #define SRCR_PKGTYPE 0x80
  189. #define SRCR_REGACKEN 0x40
  190. #define SRCR_DAISYEN 0x20
  191. #define SRCR_GLOBPRI 0x10
  192. #define SRCR_UNFAIR 0x08
  193. #define SRCR_AUTOPRI 0x02
  194. #define SRCR_PRISEL 0x01