sata_vsc.c 14 KB

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  1. /*
  2. * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
  3. *
  4. * Maintained by: Jeremy Higdon @ SGI
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2004 SGI
  9. *
  10. * Bits from Jeff Garzik, Copyright RedHat, Inc.
  11. *
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2, or (at your option)
  16. * any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; see the file COPYING. If not, write to
  25. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26. *
  27. *
  28. * libata documentation is available via 'make {ps|pdf}docs',
  29. * as Documentation/DocBook/libata.*
  30. *
  31. * Vitesse hardware documentation presumably available under NDA.
  32. * Intel 31244 (same hardware interface) documentation presumably
  33. * available from http://developer.intel.com/
  34. *
  35. */
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/pci.h>
  39. #include <linux/init.h>
  40. #include <linux/blkdev.h>
  41. #include <linux/delay.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/device.h>
  45. #include <scsi/scsi_host.h>
  46. #include <linux/libata.h>
  47. #define DRV_NAME "sata_vsc"
  48. #define DRV_VERSION "2.1"
  49. enum {
  50. VSC_MMIO_BAR = 0,
  51. /* Interrupt register offsets (from chip base address) */
  52. VSC_SATA_INT_STAT_OFFSET = 0x00,
  53. VSC_SATA_INT_MASK_OFFSET = 0x04,
  54. /* Taskfile registers offsets */
  55. VSC_SATA_TF_CMD_OFFSET = 0x00,
  56. VSC_SATA_TF_DATA_OFFSET = 0x00,
  57. VSC_SATA_TF_ERROR_OFFSET = 0x04,
  58. VSC_SATA_TF_FEATURE_OFFSET = 0x06,
  59. VSC_SATA_TF_NSECT_OFFSET = 0x08,
  60. VSC_SATA_TF_LBAL_OFFSET = 0x0c,
  61. VSC_SATA_TF_LBAM_OFFSET = 0x10,
  62. VSC_SATA_TF_LBAH_OFFSET = 0x14,
  63. VSC_SATA_TF_DEVICE_OFFSET = 0x18,
  64. VSC_SATA_TF_STATUS_OFFSET = 0x1c,
  65. VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
  66. VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
  67. VSC_SATA_TF_CTL_OFFSET = 0x29,
  68. /* DMA base */
  69. VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
  70. VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
  71. VSC_SATA_DMA_CMD_OFFSET = 0x70,
  72. /* SCRs base */
  73. VSC_SATA_SCR_STATUS_OFFSET = 0x100,
  74. VSC_SATA_SCR_ERROR_OFFSET = 0x104,
  75. VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
  76. /* Port stride */
  77. VSC_SATA_PORT_OFFSET = 0x200,
  78. /* Error interrupt status bit offsets */
  79. VSC_SATA_INT_ERROR_CRC = 0x40,
  80. VSC_SATA_INT_ERROR_T = 0x20,
  81. VSC_SATA_INT_ERROR_P = 0x10,
  82. VSC_SATA_INT_ERROR_R = 0x8,
  83. VSC_SATA_INT_ERROR_E = 0x4,
  84. VSC_SATA_INT_ERROR_M = 0x2,
  85. VSC_SATA_INT_PHY_CHANGE = 0x1,
  86. VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
  87. VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
  88. VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
  89. VSC_SATA_INT_PHY_CHANGE),
  90. };
  91. static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  92. {
  93. if (sc_reg > SCR_CONTROL)
  94. return 0xffffffffU;
  95. return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
  96. }
  97. static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  98. u32 val)
  99. {
  100. if (sc_reg > SCR_CONTROL)
  101. return;
  102. writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
  103. }
  104. static void vsc_freeze(struct ata_port *ap)
  105. {
  106. void __iomem *mask_addr;
  107. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  108. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  109. writeb(0, mask_addr);
  110. }
  111. static void vsc_thaw(struct ata_port *ap)
  112. {
  113. void __iomem *mask_addr;
  114. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  115. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  116. writeb(0xff, mask_addr);
  117. }
  118. static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
  119. {
  120. void __iomem *mask_addr;
  121. u8 mask;
  122. mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
  123. VSC_SATA_INT_MASK_OFFSET + ap->port_no;
  124. mask = readb(mask_addr);
  125. if (ctl & ATA_NIEN)
  126. mask |= 0x80;
  127. else
  128. mask &= 0x7F;
  129. writeb(mask, mask_addr);
  130. }
  131. static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  132. {
  133. struct ata_ioports *ioaddr = &ap->ioaddr;
  134. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  135. /*
  136. * The only thing the ctl register is used for is SRST.
  137. * That is not enabled or disabled via tf_load.
  138. * However, if ATA_NIEN is changed, then we need to change the interrupt register.
  139. */
  140. if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
  141. ap->last_ctl = tf->ctl;
  142. vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
  143. }
  144. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  145. writew(tf->feature | (((u16)tf->hob_feature) << 8),
  146. ioaddr->feature_addr);
  147. writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
  148. ioaddr->nsect_addr);
  149. writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
  150. ioaddr->lbal_addr);
  151. writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
  152. ioaddr->lbam_addr);
  153. writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
  154. ioaddr->lbah_addr);
  155. } else if (is_addr) {
  156. writew(tf->feature, ioaddr->feature_addr);
  157. writew(tf->nsect, ioaddr->nsect_addr);
  158. writew(tf->lbal, ioaddr->lbal_addr);
  159. writew(tf->lbam, ioaddr->lbam_addr);
  160. writew(tf->lbah, ioaddr->lbah_addr);
  161. }
  162. if (tf->flags & ATA_TFLAG_DEVICE)
  163. writeb(tf->device, ioaddr->device_addr);
  164. ata_wait_idle(ap);
  165. }
  166. static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  167. {
  168. struct ata_ioports *ioaddr = &ap->ioaddr;
  169. u16 nsect, lbal, lbam, lbah, feature;
  170. tf->command = ata_check_status(ap);
  171. tf->device = readw(ioaddr->device_addr);
  172. feature = readw(ioaddr->error_addr);
  173. nsect = readw(ioaddr->nsect_addr);
  174. lbal = readw(ioaddr->lbal_addr);
  175. lbam = readw(ioaddr->lbam_addr);
  176. lbah = readw(ioaddr->lbah_addr);
  177. tf->feature = feature;
  178. tf->nsect = nsect;
  179. tf->lbal = lbal;
  180. tf->lbam = lbam;
  181. tf->lbah = lbah;
  182. if (tf->flags & ATA_TFLAG_LBA48) {
  183. tf->hob_feature = feature >> 8;
  184. tf->hob_nsect = nsect >> 8;
  185. tf->hob_lbal = lbal >> 8;
  186. tf->hob_lbam = lbam >> 8;
  187. tf->hob_lbah = lbah >> 8;
  188. }
  189. }
  190. static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
  191. {
  192. if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
  193. ata_port_freeze(ap);
  194. else
  195. ata_port_abort(ap);
  196. }
  197. static void vsc_port_intr(u8 port_status, struct ata_port *ap)
  198. {
  199. struct ata_queued_cmd *qc;
  200. int handled = 0;
  201. if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
  202. vsc_error_intr(port_status, ap);
  203. return;
  204. }
  205. qc = ata_qc_from_tag(ap, ap->active_tag);
  206. if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
  207. handled = ata_host_intr(ap, qc);
  208. /* We received an interrupt during a polled command,
  209. * or some other spurious condition. Interrupt reporting
  210. * with this hardware is fairly reliable so it is safe to
  211. * simply clear the interrupt
  212. */
  213. if (unlikely(!handled))
  214. ata_chk_status(ap);
  215. }
  216. /*
  217. * vsc_sata_interrupt
  218. *
  219. * Read the interrupt register and process for the devices that have them pending.
  220. */
  221. static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
  222. {
  223. struct ata_host *host = dev_instance;
  224. unsigned int i;
  225. unsigned int handled = 0;
  226. u32 status;
  227. status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
  228. if (unlikely(status == 0xffffffff || status == 0)) {
  229. if (status)
  230. dev_printk(KERN_ERR, host->dev,
  231. ": IRQ status == 0xffffffff, "
  232. "PCI fault or device removal?\n");
  233. goto out;
  234. }
  235. spin_lock(&host->lock);
  236. for (i = 0; i < host->n_ports; i++) {
  237. u8 port_status = (status >> (8 * i)) & 0xff;
  238. if (port_status) {
  239. struct ata_port *ap = host->ports[i];
  240. if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
  241. vsc_port_intr(port_status, ap);
  242. handled++;
  243. } else
  244. dev_printk(KERN_ERR, host->dev,
  245. ": interrupt from disabled port %d\n", i);
  246. }
  247. }
  248. spin_unlock(&host->lock);
  249. out:
  250. return IRQ_RETVAL(handled);
  251. }
  252. static struct scsi_host_template vsc_sata_sht = {
  253. .module = THIS_MODULE,
  254. .name = DRV_NAME,
  255. .ioctl = ata_scsi_ioctl,
  256. .queuecommand = ata_scsi_queuecmd,
  257. .can_queue = ATA_DEF_QUEUE,
  258. .this_id = ATA_SHT_THIS_ID,
  259. .sg_tablesize = LIBATA_MAX_PRD,
  260. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  261. .emulated = ATA_SHT_EMULATED,
  262. .use_clustering = ATA_SHT_USE_CLUSTERING,
  263. .proc_name = DRV_NAME,
  264. .dma_boundary = ATA_DMA_BOUNDARY,
  265. .slave_configure = ata_scsi_slave_config,
  266. .slave_destroy = ata_scsi_slave_destroy,
  267. .bios_param = ata_std_bios_param,
  268. };
  269. static const struct ata_port_operations vsc_sata_ops = {
  270. .port_disable = ata_port_disable,
  271. .tf_load = vsc_sata_tf_load,
  272. .tf_read = vsc_sata_tf_read,
  273. .exec_command = ata_exec_command,
  274. .check_status = ata_check_status,
  275. .dev_select = ata_std_dev_select,
  276. .bmdma_setup = ata_bmdma_setup,
  277. .bmdma_start = ata_bmdma_start,
  278. .bmdma_stop = ata_bmdma_stop,
  279. .bmdma_status = ata_bmdma_status,
  280. .qc_prep = ata_qc_prep,
  281. .qc_issue = ata_qc_issue_prot,
  282. .data_xfer = ata_data_xfer,
  283. .freeze = vsc_freeze,
  284. .thaw = vsc_thaw,
  285. .error_handler = ata_bmdma_error_handler,
  286. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  287. .irq_handler = vsc_sata_interrupt,
  288. .irq_clear = ata_bmdma_irq_clear,
  289. .irq_on = ata_irq_on,
  290. .irq_ack = ata_irq_ack,
  291. .scr_read = vsc_sata_scr_read,
  292. .scr_write = vsc_sata_scr_write,
  293. .port_start = ata_port_start,
  294. };
  295. static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
  296. void __iomem *base)
  297. {
  298. port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
  299. port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
  300. port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
  301. port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
  302. port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
  303. port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
  304. port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
  305. port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
  306. port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
  307. port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
  308. port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
  309. port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
  310. port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
  311. port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
  312. port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
  313. writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
  314. writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
  315. }
  316. static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  317. {
  318. static int printed_version;
  319. struct ata_probe_ent *probe_ent;
  320. void __iomem *mmio_base;
  321. int rc;
  322. u8 cls;
  323. if (!printed_version++)
  324. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  325. rc = pcim_enable_device(pdev);
  326. if (rc)
  327. return rc;
  328. /*
  329. * Check if we have needed resource mapped.
  330. */
  331. if (pci_resource_len(pdev, 0) == 0)
  332. return -ENODEV;
  333. rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
  334. if (rc == -EBUSY)
  335. pcim_pin_device(pdev);
  336. if (rc)
  337. return rc;
  338. /*
  339. * Use 32 bit DMA mask, because 64 bit address support is poor.
  340. */
  341. rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  342. if (rc)
  343. return rc;
  344. rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  345. if (rc)
  346. return rc;
  347. probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
  348. if (probe_ent == NULL)
  349. return -ENOMEM;
  350. probe_ent->dev = pci_dev_to_dev(pdev);
  351. INIT_LIST_HEAD(&probe_ent->node);
  352. /*
  353. * Due to a bug in the chip, the default cache line size can't be
  354. * used (unless the default is non-zero).
  355. */
  356. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
  357. if (cls == 0x00)
  358. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
  359. if (pci_enable_msi(pdev) == 0)
  360. pci_intx(pdev, 0);
  361. else
  362. probe_ent->irq_flags = IRQF_SHARED;
  363. probe_ent->sht = &vsc_sata_sht;
  364. probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  365. ATA_FLAG_MMIO;
  366. probe_ent->port_ops = &vsc_sata_ops;
  367. probe_ent->n_ports = 4;
  368. probe_ent->irq = pdev->irq;
  369. probe_ent->iomap = pcim_iomap_table(pdev);
  370. /* We don't care much about the PIO/UDMA masks, but the core won't like us
  371. * if we don't fill these
  372. */
  373. probe_ent->pio_mask = 0x1f;
  374. probe_ent->mwdma_mask = 0x07;
  375. probe_ent->udma_mask = 0x7f;
  376. mmio_base = probe_ent->iomap[VSC_MMIO_BAR];
  377. /* We have 4 ports per PCI function */
  378. vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET);
  379. vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET);
  380. vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET);
  381. vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET);
  382. pci_set_master(pdev);
  383. /*
  384. * Config offset 0x98 is "Extended Control and Status Register 0"
  385. * Default value is (1 << 28). All bits except bit 28 are reserved in
  386. * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
  387. * If bit 28 is clear, each port has its own LED.
  388. */
  389. pci_write_config_dword(pdev, 0x98, 0);
  390. if (!ata_device_add(probe_ent))
  391. return -ENODEV;
  392. devm_kfree(&pdev->dev, probe_ent);
  393. return 0;
  394. }
  395. static const struct pci_device_id vsc_sata_pci_tbl[] = {
  396. { PCI_VENDOR_ID_VITESSE, 0x7174,
  397. PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
  398. { PCI_VENDOR_ID_INTEL, 0x3200,
  399. PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
  400. { } /* terminate list */
  401. };
  402. static struct pci_driver vsc_sata_pci_driver = {
  403. .name = DRV_NAME,
  404. .id_table = vsc_sata_pci_tbl,
  405. .probe = vsc_sata_init_one,
  406. .remove = ata_pci_remove_one,
  407. };
  408. static int __init vsc_sata_init(void)
  409. {
  410. return pci_register_driver(&vsc_sata_pci_driver);
  411. }
  412. static void __exit vsc_sata_exit(void)
  413. {
  414. pci_unregister_driver(&vsc_sata_pci_driver);
  415. }
  416. MODULE_AUTHOR("Jeremy Higdon");
  417. MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
  418. MODULE_LICENSE("GPL");
  419. MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
  420. MODULE_VERSION(DRV_VERSION);
  421. module_init(vsc_sata_init);
  422. module_exit(vsc_sata_exit);