sata_sx4.c 37 KB

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  1. /*
  2. * sata_sx4.c - Promise SATA
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2003-2004 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * Hardware documentation available under NDA.
  30. *
  31. */
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/pci.h>
  35. #include <linux/init.h>
  36. #include <linux/blkdev.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/device.h>
  40. #include <scsi/scsi_host.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <linux/libata.h>
  43. #include "sata_promise.h"
  44. #define DRV_NAME "sata_sx4"
  45. #define DRV_VERSION "0.10"
  46. enum {
  47. PDC_MMIO_BAR = 3,
  48. PDC_DIMM_BAR = 4,
  49. PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
  50. PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
  51. PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
  52. PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
  53. PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
  54. PDC_20621_SEQCTL = 0x400,
  55. PDC_20621_SEQMASK = 0x480,
  56. PDC_20621_GENERAL_CTL = 0x484,
  57. PDC_20621_PAGE_SIZE = (32 * 1024),
  58. /* chosen, not constant, values; we design our own DIMM mem map */
  59. PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
  60. PDC_20621_DIMM_BASE = 0x00200000,
  61. PDC_20621_DIMM_DATA = (64 * 1024),
  62. PDC_DIMM_DATA_STEP = (256 * 1024),
  63. PDC_DIMM_WINDOW_STEP = (8 * 1024),
  64. PDC_DIMM_HOST_PRD = (6 * 1024),
  65. PDC_DIMM_HOST_PKT = (128 * 0),
  66. PDC_DIMM_HPKT_PRD = (128 * 1),
  67. PDC_DIMM_ATA_PKT = (128 * 2),
  68. PDC_DIMM_APKT_PRD = (128 * 3),
  69. PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
  70. PDC_PAGE_WINDOW = 0x40,
  71. PDC_PAGE_DATA = PDC_PAGE_WINDOW +
  72. (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  73. PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  74. PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
  75. PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  76. (1<<23),
  77. board_20621 = 0, /* FastTrak S150 SX4 */
  78. PDC_RESET = (1 << 11), /* HDMA reset */
  79. PDC_MAX_HDMA = 32,
  80. PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
  81. PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
  82. PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
  83. PDC_MAX_DIMM_MODULE = 0x02,
  84. PDC_I2C_CONTROL_OFFSET = 0x48,
  85. PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
  86. PDC_DIMM0_CONTROL_OFFSET = 0x80,
  87. PDC_DIMM1_CONTROL_OFFSET = 0x84,
  88. PDC_SDRAM_CONTROL_OFFSET = 0x88,
  89. PDC_I2C_WRITE = 0x00000000,
  90. PDC_I2C_READ = 0x00000040,
  91. PDC_I2C_START = 0x00000080,
  92. PDC_I2C_MASK_INT = 0x00000020,
  93. PDC_I2C_COMPLETE = 0x00010000,
  94. PDC_I2C_NO_ACK = 0x00100000,
  95. PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
  96. PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
  97. PDC_DIMM_SPD_ROW_NUM = 3,
  98. PDC_DIMM_SPD_COLUMN_NUM = 4,
  99. PDC_DIMM_SPD_MODULE_ROW = 5,
  100. PDC_DIMM_SPD_TYPE = 11,
  101. PDC_DIMM_SPD_FRESH_RATE = 12,
  102. PDC_DIMM_SPD_BANK_NUM = 17,
  103. PDC_DIMM_SPD_CAS_LATENCY = 18,
  104. PDC_DIMM_SPD_ATTRIBUTE = 21,
  105. PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
  106. PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
  107. PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
  108. PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
  109. PDC_DIMM_SPD_SYSTEM_FREQ = 126,
  110. PDC_CTL_STATUS = 0x08,
  111. PDC_DIMM_WINDOW_CTLR = 0x0C,
  112. PDC_TIME_CONTROL = 0x3C,
  113. PDC_TIME_PERIOD = 0x40,
  114. PDC_TIME_COUNTER = 0x44,
  115. PDC_GENERAL_CTLR = 0x484,
  116. PCI_PLL_INIT = 0x8A531824,
  117. PCI_X_TCOUNT = 0xEE1E5CFF
  118. };
  119. struct pdc_port_priv {
  120. u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
  121. u8 *pkt;
  122. dma_addr_t pkt_dma;
  123. };
  124. struct pdc_host_priv {
  125. unsigned int doing_hdma;
  126. unsigned int hdma_prod;
  127. unsigned int hdma_cons;
  128. struct {
  129. struct ata_queued_cmd *qc;
  130. unsigned int seq;
  131. unsigned long pkt_ofs;
  132. } hdma[32];
  133. };
  134. static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  135. static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance);
  136. static void pdc_eng_timeout(struct ata_port *ap);
  137. static void pdc_20621_phy_reset (struct ata_port *ap);
  138. static int pdc_port_start(struct ata_port *ap);
  139. static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
  140. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  141. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  142. static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
  143. static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
  144. static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
  145. u32 device, u32 subaddr, u32 *pdata);
  146. static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
  147. static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
  148. #ifdef ATA_VERBOSE_DEBUG
  149. static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
  150. void *psource, u32 offset, u32 size);
  151. #endif
  152. static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
  153. void *psource, u32 offset, u32 size);
  154. static void pdc20621_irq_clear(struct ata_port *ap);
  155. static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
  156. static struct scsi_host_template pdc_sata_sht = {
  157. .module = THIS_MODULE,
  158. .name = DRV_NAME,
  159. .ioctl = ata_scsi_ioctl,
  160. .queuecommand = ata_scsi_queuecmd,
  161. .can_queue = ATA_DEF_QUEUE,
  162. .this_id = ATA_SHT_THIS_ID,
  163. .sg_tablesize = LIBATA_MAX_PRD,
  164. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  165. .emulated = ATA_SHT_EMULATED,
  166. .use_clustering = ATA_SHT_USE_CLUSTERING,
  167. .proc_name = DRV_NAME,
  168. .dma_boundary = ATA_DMA_BOUNDARY,
  169. .slave_configure = ata_scsi_slave_config,
  170. .slave_destroy = ata_scsi_slave_destroy,
  171. .bios_param = ata_std_bios_param,
  172. };
  173. static const struct ata_port_operations pdc_20621_ops = {
  174. .port_disable = ata_port_disable,
  175. .tf_load = pdc_tf_load_mmio,
  176. .tf_read = ata_tf_read,
  177. .check_status = ata_check_status,
  178. .exec_command = pdc_exec_command_mmio,
  179. .dev_select = ata_std_dev_select,
  180. .phy_reset = pdc_20621_phy_reset,
  181. .qc_prep = pdc20621_qc_prep,
  182. .qc_issue = pdc20621_qc_issue_prot,
  183. .data_xfer = ata_data_xfer,
  184. .eng_timeout = pdc_eng_timeout,
  185. .irq_handler = pdc20621_interrupt,
  186. .irq_clear = pdc20621_irq_clear,
  187. .irq_on = ata_irq_on,
  188. .irq_ack = ata_irq_ack,
  189. .port_start = pdc_port_start,
  190. };
  191. static const struct ata_port_info pdc_port_info[] = {
  192. /* board_20621 */
  193. {
  194. .sht = &pdc_sata_sht,
  195. .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  196. ATA_FLAG_SRST | ATA_FLAG_MMIO |
  197. ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
  198. .pio_mask = 0x1f, /* pio0-4 */
  199. .mwdma_mask = 0x07, /* mwdma0-2 */
  200. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  201. .port_ops = &pdc_20621_ops,
  202. },
  203. };
  204. static const struct pci_device_id pdc_sata_pci_tbl[] = {
  205. { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
  206. { } /* terminate list */
  207. };
  208. static struct pci_driver pdc_sata_pci_driver = {
  209. .name = DRV_NAME,
  210. .id_table = pdc_sata_pci_tbl,
  211. .probe = pdc_sata_init_one,
  212. .remove = ata_pci_remove_one,
  213. };
  214. static int pdc_port_start(struct ata_port *ap)
  215. {
  216. struct device *dev = ap->host->dev;
  217. struct pdc_port_priv *pp;
  218. int rc;
  219. rc = ata_port_start(ap);
  220. if (rc)
  221. return rc;
  222. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  223. if (!pp)
  224. return -ENOMEM;
  225. pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
  226. if (!pp->pkt)
  227. return -ENOMEM;
  228. ap->private_data = pp;
  229. return 0;
  230. }
  231. static void pdc_20621_phy_reset (struct ata_port *ap)
  232. {
  233. VPRINTK("ENTER\n");
  234. ap->cbl = ATA_CBL_SATA;
  235. ata_port_probe(ap);
  236. ata_bus_reset(ap);
  237. }
  238. static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
  239. unsigned int portno,
  240. unsigned int total_len)
  241. {
  242. u32 addr;
  243. unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
  244. u32 *buf32 = (u32 *) buf;
  245. /* output ATA packet S/G table */
  246. addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
  247. (PDC_DIMM_DATA_STEP * portno);
  248. VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
  249. buf32[dw] = cpu_to_le32(addr);
  250. buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
  251. VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
  252. PDC_20621_DIMM_BASE +
  253. (PDC_DIMM_WINDOW_STEP * portno) +
  254. PDC_DIMM_APKT_PRD,
  255. buf32[dw], buf32[dw + 1]);
  256. }
  257. static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
  258. unsigned int portno,
  259. unsigned int total_len)
  260. {
  261. u32 addr;
  262. unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
  263. u32 *buf32 = (u32 *) buf;
  264. /* output Host DMA packet S/G table */
  265. addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
  266. (PDC_DIMM_DATA_STEP * portno);
  267. buf32[dw] = cpu_to_le32(addr);
  268. buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
  269. VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
  270. PDC_20621_DIMM_BASE +
  271. (PDC_DIMM_WINDOW_STEP * portno) +
  272. PDC_DIMM_HPKT_PRD,
  273. buf32[dw], buf32[dw + 1]);
  274. }
  275. static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
  276. unsigned int devno, u8 *buf,
  277. unsigned int portno)
  278. {
  279. unsigned int i, dw;
  280. u32 *buf32 = (u32 *) buf;
  281. u8 dev_reg;
  282. unsigned int dimm_sg = PDC_20621_DIMM_BASE +
  283. (PDC_DIMM_WINDOW_STEP * portno) +
  284. PDC_DIMM_APKT_PRD;
  285. VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
  286. i = PDC_DIMM_ATA_PKT;
  287. /*
  288. * Set up ATA packet
  289. */
  290. if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
  291. buf[i++] = PDC_PKT_READ;
  292. else if (tf->protocol == ATA_PROT_NODATA)
  293. buf[i++] = PDC_PKT_NODATA;
  294. else
  295. buf[i++] = 0;
  296. buf[i++] = 0; /* reserved */
  297. buf[i++] = portno + 1; /* seq. id */
  298. buf[i++] = 0xff; /* delay seq. id */
  299. /* dimm dma S/G, and next-pkt */
  300. dw = i >> 2;
  301. if (tf->protocol == ATA_PROT_NODATA)
  302. buf32[dw] = 0;
  303. else
  304. buf32[dw] = cpu_to_le32(dimm_sg);
  305. buf32[dw + 1] = 0;
  306. i += 8;
  307. if (devno == 0)
  308. dev_reg = ATA_DEVICE_OBS;
  309. else
  310. dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
  311. /* select device */
  312. buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
  313. buf[i++] = dev_reg;
  314. /* device control register */
  315. buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
  316. buf[i++] = tf->ctl;
  317. return i;
  318. }
  319. static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
  320. unsigned int portno)
  321. {
  322. unsigned int dw;
  323. u32 tmp, *buf32 = (u32 *) buf;
  324. unsigned int host_sg = PDC_20621_DIMM_BASE +
  325. (PDC_DIMM_WINDOW_STEP * portno) +
  326. PDC_DIMM_HOST_PRD;
  327. unsigned int dimm_sg = PDC_20621_DIMM_BASE +
  328. (PDC_DIMM_WINDOW_STEP * portno) +
  329. PDC_DIMM_HPKT_PRD;
  330. VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
  331. VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
  332. dw = PDC_DIMM_HOST_PKT >> 2;
  333. /*
  334. * Set up Host DMA packet
  335. */
  336. if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
  337. tmp = PDC_PKT_READ;
  338. else
  339. tmp = 0;
  340. tmp |= ((portno + 1 + 4) << 16); /* seq. id */
  341. tmp |= (0xff << 24); /* delay seq. id */
  342. buf32[dw + 0] = cpu_to_le32(tmp);
  343. buf32[dw + 1] = cpu_to_le32(host_sg);
  344. buf32[dw + 2] = cpu_to_le32(dimm_sg);
  345. buf32[dw + 3] = 0;
  346. VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
  347. PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
  348. PDC_DIMM_HOST_PKT,
  349. buf32[dw + 0],
  350. buf32[dw + 1],
  351. buf32[dw + 2],
  352. buf32[dw + 3]);
  353. }
  354. static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
  355. {
  356. struct scatterlist *sg;
  357. struct ata_port *ap = qc->ap;
  358. struct pdc_port_priv *pp = ap->private_data;
  359. void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
  360. void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
  361. unsigned int portno = ap->port_no;
  362. unsigned int i, idx, total_len = 0, sgt_len;
  363. u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
  364. WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
  365. VPRINTK("ata%u: ENTER\n", ap->print_id);
  366. /* hard-code chip #0 */
  367. mmio += PDC_CHIP0_OFS;
  368. /*
  369. * Build S/G table
  370. */
  371. idx = 0;
  372. ata_for_each_sg(sg, qc) {
  373. buf[idx++] = cpu_to_le32(sg_dma_address(sg));
  374. buf[idx++] = cpu_to_le32(sg_dma_len(sg));
  375. total_len += sg_dma_len(sg);
  376. }
  377. buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
  378. sgt_len = idx * 4;
  379. /*
  380. * Build ATA, host DMA packets
  381. */
  382. pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
  383. pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
  384. pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
  385. i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
  386. if (qc->tf.flags & ATA_TFLAG_LBA48)
  387. i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
  388. else
  389. i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
  390. pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
  391. /* copy three S/G tables and two packets to DIMM MMIO window */
  392. memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
  393. &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
  394. memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
  395. PDC_DIMM_HOST_PRD,
  396. &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
  397. /* force host FIFO dump */
  398. writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
  399. readl(dimm_mmio); /* MMIO PCI posting flush */
  400. VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
  401. }
  402. static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
  403. {
  404. struct ata_port *ap = qc->ap;
  405. struct pdc_port_priv *pp = ap->private_data;
  406. void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
  407. void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
  408. unsigned int portno = ap->port_no;
  409. unsigned int i;
  410. VPRINTK("ata%u: ENTER\n", ap->print_id);
  411. /* hard-code chip #0 */
  412. mmio += PDC_CHIP0_OFS;
  413. i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
  414. if (qc->tf.flags & ATA_TFLAG_LBA48)
  415. i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
  416. else
  417. i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
  418. pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
  419. /* copy three S/G tables and two packets to DIMM MMIO window */
  420. memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
  421. &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
  422. /* force host FIFO dump */
  423. writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
  424. readl(dimm_mmio); /* MMIO PCI posting flush */
  425. VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
  426. }
  427. static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
  428. {
  429. switch (qc->tf.protocol) {
  430. case ATA_PROT_DMA:
  431. pdc20621_dma_prep(qc);
  432. break;
  433. case ATA_PROT_NODATA:
  434. pdc20621_nodata_prep(qc);
  435. break;
  436. default:
  437. break;
  438. }
  439. }
  440. static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
  441. unsigned int seq,
  442. u32 pkt_ofs)
  443. {
  444. struct ata_port *ap = qc->ap;
  445. struct ata_host *host = ap->host;
  446. void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
  447. /* hard-code chip #0 */
  448. mmio += PDC_CHIP0_OFS;
  449. writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
  450. readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
  451. writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
  452. readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
  453. }
  454. static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
  455. unsigned int seq,
  456. u32 pkt_ofs)
  457. {
  458. struct ata_port *ap = qc->ap;
  459. struct pdc_host_priv *pp = ap->host->private_data;
  460. unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
  461. if (!pp->doing_hdma) {
  462. __pdc20621_push_hdma(qc, seq, pkt_ofs);
  463. pp->doing_hdma = 1;
  464. return;
  465. }
  466. pp->hdma[idx].qc = qc;
  467. pp->hdma[idx].seq = seq;
  468. pp->hdma[idx].pkt_ofs = pkt_ofs;
  469. pp->hdma_prod++;
  470. }
  471. static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
  472. {
  473. struct ata_port *ap = qc->ap;
  474. struct pdc_host_priv *pp = ap->host->private_data;
  475. unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
  476. /* if nothing on queue, we're done */
  477. if (pp->hdma_prod == pp->hdma_cons) {
  478. pp->doing_hdma = 0;
  479. return;
  480. }
  481. __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
  482. pp->hdma[idx].pkt_ofs);
  483. pp->hdma_cons++;
  484. }
  485. #ifdef ATA_VERBOSE_DEBUG
  486. static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
  487. {
  488. struct ata_port *ap = qc->ap;
  489. unsigned int port_no = ap->port_no;
  490. void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
  491. dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
  492. dimm_mmio += PDC_DIMM_HOST_PKT;
  493. printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
  494. printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
  495. printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
  496. printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
  497. }
  498. #else
  499. static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
  500. #endif /* ATA_VERBOSE_DEBUG */
  501. static void pdc20621_packet_start(struct ata_queued_cmd *qc)
  502. {
  503. struct ata_port *ap = qc->ap;
  504. struct ata_host *host = ap->host;
  505. unsigned int port_no = ap->port_no;
  506. void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
  507. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  508. u8 seq = (u8) (port_no + 1);
  509. unsigned int port_ofs;
  510. /* hard-code chip #0 */
  511. mmio += PDC_CHIP0_OFS;
  512. VPRINTK("ata%u: ENTER\n", ap->print_id);
  513. wmb(); /* flush PRD, pkt writes */
  514. port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
  515. /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
  516. if (rw && qc->tf.protocol == ATA_PROT_DMA) {
  517. seq += 4;
  518. pdc20621_dump_hdma(qc);
  519. pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
  520. VPRINTK("queued ofs 0x%x (%u), seq %u\n",
  521. port_ofs + PDC_DIMM_HOST_PKT,
  522. port_ofs + PDC_DIMM_HOST_PKT,
  523. seq);
  524. } else {
  525. writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
  526. readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
  527. writel(port_ofs + PDC_DIMM_ATA_PKT,
  528. ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  529. readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  530. VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
  531. port_ofs + PDC_DIMM_ATA_PKT,
  532. port_ofs + PDC_DIMM_ATA_PKT,
  533. seq);
  534. }
  535. }
  536. static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
  537. {
  538. switch (qc->tf.protocol) {
  539. case ATA_PROT_DMA:
  540. case ATA_PROT_NODATA:
  541. pdc20621_packet_start(qc);
  542. return 0;
  543. case ATA_PROT_ATAPI_DMA:
  544. BUG();
  545. break;
  546. default:
  547. break;
  548. }
  549. return ata_qc_issue_prot(qc);
  550. }
  551. static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
  552. struct ata_queued_cmd *qc,
  553. unsigned int doing_hdma,
  554. void __iomem *mmio)
  555. {
  556. unsigned int port_no = ap->port_no;
  557. unsigned int port_ofs =
  558. PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
  559. u8 status;
  560. unsigned int handled = 0;
  561. VPRINTK("ENTER\n");
  562. if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
  563. (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
  564. /* step two - DMA from DIMM to host */
  565. if (doing_hdma) {
  566. VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
  567. readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
  568. /* get drive status; clear intr; complete txn */
  569. qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
  570. ata_qc_complete(qc);
  571. pdc20621_pop_hdma(qc);
  572. }
  573. /* step one - exec ATA command */
  574. else {
  575. u8 seq = (u8) (port_no + 1 + 4);
  576. VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
  577. readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
  578. /* submit hdma pkt */
  579. pdc20621_dump_hdma(qc);
  580. pdc20621_push_hdma(qc, seq,
  581. port_ofs + PDC_DIMM_HOST_PKT);
  582. }
  583. handled = 1;
  584. } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
  585. /* step one - DMA from host to DIMM */
  586. if (doing_hdma) {
  587. u8 seq = (u8) (port_no + 1);
  588. VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
  589. readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
  590. /* submit ata pkt */
  591. writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
  592. readl(mmio + PDC_20621_SEQCTL + (seq * 4));
  593. writel(port_ofs + PDC_DIMM_ATA_PKT,
  594. ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  595. readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  596. }
  597. /* step two - execute ATA command */
  598. else {
  599. VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
  600. readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
  601. /* get drive status; clear intr; complete txn */
  602. qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
  603. ata_qc_complete(qc);
  604. pdc20621_pop_hdma(qc);
  605. }
  606. handled = 1;
  607. /* command completion, but no data xfer */
  608. } else if (qc->tf.protocol == ATA_PROT_NODATA) {
  609. status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
  610. DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
  611. qc->err_mask |= ac_err_mask(status);
  612. ata_qc_complete(qc);
  613. handled = 1;
  614. } else {
  615. ap->stats.idle_irq++;
  616. }
  617. return handled;
  618. }
  619. static void pdc20621_irq_clear(struct ata_port *ap)
  620. {
  621. struct ata_host *host = ap->host;
  622. void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
  623. mmio += PDC_CHIP0_OFS;
  624. readl(mmio + PDC_20621_SEQMASK);
  625. }
  626. static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
  627. {
  628. struct ata_host *host = dev_instance;
  629. struct ata_port *ap;
  630. u32 mask = 0;
  631. unsigned int i, tmp, port_no;
  632. unsigned int handled = 0;
  633. void __iomem *mmio_base;
  634. VPRINTK("ENTER\n");
  635. if (!host || !host->iomap[PDC_MMIO_BAR]) {
  636. VPRINTK("QUICK EXIT\n");
  637. return IRQ_NONE;
  638. }
  639. mmio_base = host->iomap[PDC_MMIO_BAR];
  640. /* reading should also clear interrupts */
  641. mmio_base += PDC_CHIP0_OFS;
  642. mask = readl(mmio_base + PDC_20621_SEQMASK);
  643. VPRINTK("mask == 0x%x\n", mask);
  644. if (mask == 0xffffffff) {
  645. VPRINTK("QUICK EXIT 2\n");
  646. return IRQ_NONE;
  647. }
  648. mask &= 0xffff; /* only 16 tags possible */
  649. if (!mask) {
  650. VPRINTK("QUICK EXIT 3\n");
  651. return IRQ_NONE;
  652. }
  653. spin_lock(&host->lock);
  654. for (i = 1; i < 9; i++) {
  655. port_no = i - 1;
  656. if (port_no > 3)
  657. port_no -= 4;
  658. if (port_no >= host->n_ports)
  659. ap = NULL;
  660. else
  661. ap = host->ports[port_no];
  662. tmp = mask & (1 << i);
  663. VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
  664. if (tmp && ap &&
  665. !(ap->flags & ATA_FLAG_DISABLED)) {
  666. struct ata_queued_cmd *qc;
  667. qc = ata_qc_from_tag(ap, ap->active_tag);
  668. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
  669. handled += pdc20621_host_intr(ap, qc, (i > 4),
  670. mmio_base);
  671. }
  672. }
  673. spin_unlock(&host->lock);
  674. VPRINTK("mask == 0x%x\n", mask);
  675. VPRINTK("EXIT\n");
  676. return IRQ_RETVAL(handled);
  677. }
  678. static void pdc_eng_timeout(struct ata_port *ap)
  679. {
  680. u8 drv_stat;
  681. struct ata_host *host = ap->host;
  682. struct ata_queued_cmd *qc;
  683. unsigned long flags;
  684. DPRINTK("ENTER\n");
  685. spin_lock_irqsave(&host->lock, flags);
  686. qc = ata_qc_from_tag(ap, ap->active_tag);
  687. switch (qc->tf.protocol) {
  688. case ATA_PROT_DMA:
  689. case ATA_PROT_NODATA:
  690. ata_port_printk(ap, KERN_ERR, "command timeout\n");
  691. qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
  692. break;
  693. default:
  694. drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
  695. ata_port_printk(ap, KERN_ERR,
  696. "unknown timeout, cmd 0x%x stat 0x%x\n",
  697. qc->tf.command, drv_stat);
  698. qc->err_mask |= ac_err_mask(drv_stat);
  699. break;
  700. }
  701. spin_unlock_irqrestore(&host->lock, flags);
  702. ata_eh_qc_complete(qc);
  703. DPRINTK("EXIT\n");
  704. }
  705. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  706. {
  707. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  708. tf->protocol == ATA_PROT_NODATA);
  709. ata_tf_load(ap, tf);
  710. }
  711. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  712. {
  713. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  714. tf->protocol == ATA_PROT_NODATA);
  715. ata_exec_command(ap, tf);
  716. }
  717. static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
  718. {
  719. port->cmd_addr = base;
  720. port->data_addr = base;
  721. port->feature_addr =
  722. port->error_addr = base + 0x4;
  723. port->nsect_addr = base + 0x8;
  724. port->lbal_addr = base + 0xc;
  725. port->lbam_addr = base + 0x10;
  726. port->lbah_addr = base + 0x14;
  727. port->device_addr = base + 0x18;
  728. port->command_addr =
  729. port->status_addr = base + 0x1c;
  730. port->altstatus_addr =
  731. port->ctl_addr = base + 0x38;
  732. }
  733. #ifdef ATA_VERBOSE_DEBUG
  734. static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
  735. u32 offset, u32 size)
  736. {
  737. u32 window_size;
  738. u16 idx;
  739. u8 page_mask;
  740. long dist;
  741. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  742. void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
  743. /* hard-code chip #0 */
  744. mmio += PDC_CHIP0_OFS;
  745. page_mask = 0x00;
  746. window_size = 0x2000 * 4; /* 32K byte uchar size */
  747. idx = (u16) (offset / window_size);
  748. writel(0x01, mmio + PDC_GENERAL_CTLR);
  749. readl(mmio + PDC_GENERAL_CTLR);
  750. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  751. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  752. offset -= (idx * window_size);
  753. idx++;
  754. dist = ((long) (window_size - (offset + size))) >= 0 ? size :
  755. (long) (window_size - offset);
  756. memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
  757. dist);
  758. psource += dist;
  759. size -= dist;
  760. for (; (long) size >= (long) window_size ;) {
  761. writel(0x01, mmio + PDC_GENERAL_CTLR);
  762. readl(mmio + PDC_GENERAL_CTLR);
  763. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  764. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  765. memcpy_fromio((char *) psource, (char *) (dimm_mmio),
  766. window_size / 4);
  767. psource += window_size;
  768. size -= window_size;
  769. idx ++;
  770. }
  771. if (size) {
  772. writel(0x01, mmio + PDC_GENERAL_CTLR);
  773. readl(mmio + PDC_GENERAL_CTLR);
  774. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  775. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  776. memcpy_fromio((char *) psource, (char *) (dimm_mmio),
  777. size / 4);
  778. }
  779. }
  780. #endif
  781. static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
  782. u32 offset, u32 size)
  783. {
  784. u32 window_size;
  785. u16 idx;
  786. u8 page_mask;
  787. long dist;
  788. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  789. void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
  790. /* hard-code chip #0 */
  791. mmio += PDC_CHIP0_OFS;
  792. page_mask = 0x00;
  793. window_size = 0x2000 * 4; /* 32K byte uchar size */
  794. idx = (u16) (offset / window_size);
  795. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  796. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  797. offset -= (idx * window_size);
  798. idx++;
  799. dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
  800. (long) (window_size - offset);
  801. memcpy_toio(dimm_mmio + offset / 4, psource, dist);
  802. writel(0x01, mmio + PDC_GENERAL_CTLR);
  803. readl(mmio + PDC_GENERAL_CTLR);
  804. psource += dist;
  805. size -= dist;
  806. for (; (long) size >= (long) window_size ;) {
  807. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  808. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  809. memcpy_toio(dimm_mmio, psource, window_size / 4);
  810. writel(0x01, mmio + PDC_GENERAL_CTLR);
  811. readl(mmio + PDC_GENERAL_CTLR);
  812. psource += window_size;
  813. size -= window_size;
  814. idx ++;
  815. }
  816. if (size) {
  817. writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
  818. readl(mmio + PDC_DIMM_WINDOW_CTLR);
  819. memcpy_toio(dimm_mmio, psource, size / 4);
  820. writel(0x01, mmio + PDC_GENERAL_CTLR);
  821. readl(mmio + PDC_GENERAL_CTLR);
  822. }
  823. }
  824. static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
  825. u32 subaddr, u32 *pdata)
  826. {
  827. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  828. u32 i2creg = 0;
  829. u32 status;
  830. u32 count =0;
  831. /* hard-code chip #0 */
  832. mmio += PDC_CHIP0_OFS;
  833. i2creg |= device << 24;
  834. i2creg |= subaddr << 16;
  835. /* Set the device and subaddress */
  836. writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
  837. readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
  838. /* Write Control to perform read operation, mask int */
  839. writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
  840. mmio + PDC_I2C_CONTROL_OFFSET);
  841. for (count = 0; count <= 1000; count ++) {
  842. status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
  843. if (status & PDC_I2C_COMPLETE) {
  844. status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
  845. break;
  846. } else if (count == 1000)
  847. return 0;
  848. }
  849. *pdata = (status >> 8) & 0x000000ff;
  850. return 1;
  851. }
  852. static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
  853. {
  854. u32 data=0 ;
  855. if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
  856. PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
  857. if (data == 100)
  858. return 100;
  859. } else
  860. return 0;
  861. if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
  862. if(data <= 0x75)
  863. return 133;
  864. } else
  865. return 0;
  866. return 0;
  867. }
  868. static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
  869. {
  870. u32 spd0[50];
  871. u32 data = 0;
  872. int size, i;
  873. u8 bdimmsize;
  874. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  875. static const struct {
  876. unsigned int reg;
  877. unsigned int ofs;
  878. } pdc_i2c_read_data [] = {
  879. { PDC_DIMM_SPD_TYPE, 11 },
  880. { PDC_DIMM_SPD_FRESH_RATE, 12 },
  881. { PDC_DIMM_SPD_COLUMN_NUM, 4 },
  882. { PDC_DIMM_SPD_ATTRIBUTE, 21 },
  883. { PDC_DIMM_SPD_ROW_NUM, 3 },
  884. { PDC_DIMM_SPD_BANK_NUM, 17 },
  885. { PDC_DIMM_SPD_MODULE_ROW, 5 },
  886. { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
  887. { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
  888. { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
  889. { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
  890. { PDC_DIMM_SPD_CAS_LATENCY, 18 },
  891. };
  892. /* hard-code chip #0 */
  893. mmio += PDC_CHIP0_OFS;
  894. for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
  895. pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
  896. pdc_i2c_read_data[i].reg,
  897. &spd0[pdc_i2c_read_data[i].ofs]);
  898. data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
  899. data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
  900. ((((spd0[27] + 9) / 10) - 1) << 8) ;
  901. data |= (((((spd0[29] > spd0[28])
  902. ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
  903. data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
  904. if (spd0[18] & 0x08)
  905. data |= ((0x03) << 14);
  906. else if (spd0[18] & 0x04)
  907. data |= ((0x02) << 14);
  908. else if (spd0[18] & 0x01)
  909. data |= ((0x01) << 14);
  910. else
  911. data |= (0 << 14);
  912. /*
  913. Calculate the size of bDIMMSize (power of 2) and
  914. merge the DIMM size by program start/end address.
  915. */
  916. bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
  917. size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
  918. data |= (((size / 16) - 1) << 16);
  919. data |= (0 << 23);
  920. data |= 8;
  921. writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
  922. readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
  923. return size;
  924. }
  925. static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
  926. {
  927. u32 data, spd0;
  928. int error, i;
  929. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  930. /* hard-code chip #0 */
  931. mmio += PDC_CHIP0_OFS;
  932. /*
  933. Set To Default : DIMM Module Global Control Register (0x022259F1)
  934. DIMM Arbitration Disable (bit 20)
  935. DIMM Data/Control Output Driving Selection (bit12 - bit15)
  936. Refresh Enable (bit 17)
  937. */
  938. data = 0x022259F1;
  939. writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
  940. readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
  941. /* Turn on for ECC */
  942. pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
  943. PDC_DIMM_SPD_TYPE, &spd0);
  944. if (spd0 == 0x02) {
  945. data |= (0x01 << 16);
  946. writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
  947. readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
  948. printk(KERN_ERR "Local DIMM ECC Enabled\n");
  949. }
  950. /* DIMM Initialization Select/Enable (bit 18/19) */
  951. data &= (~(1<<18));
  952. data |= (1<<19);
  953. writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
  954. error = 1;
  955. for (i = 1; i <= 10; i++) { /* polling ~5 secs */
  956. data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
  957. if (!(data & (1<<19))) {
  958. error = 0;
  959. break;
  960. }
  961. msleep(i*100);
  962. }
  963. return error;
  964. }
  965. static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
  966. {
  967. int speed, size, length;
  968. u32 addr,spd0,pci_status;
  969. u32 tmp=0;
  970. u32 time_period=0;
  971. u32 tcount=0;
  972. u32 ticks=0;
  973. u32 clock=0;
  974. u32 fparam=0;
  975. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  976. /* hard-code chip #0 */
  977. mmio += PDC_CHIP0_OFS;
  978. /* Initialize PLL based upon PCI Bus Frequency */
  979. /* Initialize Time Period Register */
  980. writel(0xffffffff, mmio + PDC_TIME_PERIOD);
  981. time_period = readl(mmio + PDC_TIME_PERIOD);
  982. VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
  983. /* Enable timer */
  984. writel(0x00001a0, mmio + PDC_TIME_CONTROL);
  985. readl(mmio + PDC_TIME_CONTROL);
  986. /* Wait 3 seconds */
  987. msleep(3000);
  988. /*
  989. When timer is enabled, counter is decreased every internal
  990. clock cycle.
  991. */
  992. tcount = readl(mmio + PDC_TIME_COUNTER);
  993. VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
  994. /*
  995. If SX4 is on PCI-X bus, after 3 seconds, the timer counter
  996. register should be >= (0xffffffff - 3x10^8).
  997. */
  998. if(tcount >= PCI_X_TCOUNT) {
  999. ticks = (time_period - tcount);
  1000. VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
  1001. clock = (ticks / 300000);
  1002. VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
  1003. clock = (clock * 33);
  1004. VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
  1005. /* PLL F Param (bit 22:16) */
  1006. fparam = (1400000 / clock) - 2;
  1007. VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
  1008. /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
  1009. pci_status = (0x8a001824 | (fparam << 16));
  1010. } else
  1011. pci_status = PCI_PLL_INIT;
  1012. /* Initialize PLL. */
  1013. VPRINTK("pci_status: 0x%x\n", pci_status);
  1014. writel(pci_status, mmio + PDC_CTL_STATUS);
  1015. readl(mmio + PDC_CTL_STATUS);
  1016. /*
  1017. Read SPD of DIMM by I2C interface,
  1018. and program the DIMM Module Controller.
  1019. */
  1020. if (!(speed = pdc20621_detect_dimm(pe))) {
  1021. printk(KERN_ERR "Detect Local DIMM Fail\n");
  1022. return 1; /* DIMM error */
  1023. }
  1024. VPRINTK("Local DIMM Speed = %d\n", speed);
  1025. /* Programming DIMM0 Module Control Register (index_CID0:80h) */
  1026. size = pdc20621_prog_dimm0(pe);
  1027. VPRINTK("Local DIMM Size = %dMB\n",size);
  1028. /* Programming DIMM Module Global Control Register (index_CID0:88h) */
  1029. if (pdc20621_prog_dimm_global(pe)) {
  1030. printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
  1031. return 1;
  1032. }
  1033. #ifdef ATA_VERBOSE_DEBUG
  1034. {
  1035. u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
  1036. 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
  1037. '1','.','1','0',
  1038. '9','8','0','3','1','6','1','2',0,0};
  1039. u8 test_parttern2[40] = {0};
  1040. pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
  1041. pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
  1042. pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
  1043. pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
  1044. printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
  1045. test_parttern2[1], &(test_parttern2[2]));
  1046. pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
  1047. 40);
  1048. printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
  1049. test_parttern2[1], &(test_parttern2[2]));
  1050. pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
  1051. pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
  1052. printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
  1053. test_parttern2[1], &(test_parttern2[2]));
  1054. }
  1055. #endif
  1056. /* ECC initiliazation. */
  1057. pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
  1058. PDC_DIMM_SPD_TYPE, &spd0);
  1059. if (spd0 == 0x02) {
  1060. VPRINTK("Start ECC initialization\n");
  1061. addr = 0;
  1062. length = size * 1024 * 1024;
  1063. while (addr < length) {
  1064. pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
  1065. sizeof(u32));
  1066. addr += sizeof(u32);
  1067. }
  1068. VPRINTK("Finish ECC initialization\n");
  1069. }
  1070. return 0;
  1071. }
  1072. static void pdc_20621_init(struct ata_probe_ent *pe)
  1073. {
  1074. u32 tmp;
  1075. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  1076. /* hard-code chip #0 */
  1077. mmio += PDC_CHIP0_OFS;
  1078. /*
  1079. * Select page 0x40 for our 32k DIMM window
  1080. */
  1081. tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
  1082. tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
  1083. writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
  1084. /*
  1085. * Reset Host DMA
  1086. */
  1087. tmp = readl(mmio + PDC_HDMA_CTLSTAT);
  1088. tmp |= PDC_RESET;
  1089. writel(tmp, mmio + PDC_HDMA_CTLSTAT);
  1090. readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
  1091. udelay(10);
  1092. tmp = readl(mmio + PDC_HDMA_CTLSTAT);
  1093. tmp &= ~PDC_RESET;
  1094. writel(tmp, mmio + PDC_HDMA_CTLSTAT);
  1095. readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
  1096. }
  1097. static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  1098. {
  1099. static int printed_version;
  1100. struct ata_probe_ent *probe_ent;
  1101. void __iomem *base;
  1102. struct pdc_host_priv *hpriv;
  1103. unsigned int board_idx = (unsigned int) ent->driver_data;
  1104. int rc;
  1105. if (!printed_version++)
  1106. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  1107. rc = pcim_enable_device(pdev);
  1108. if (rc)
  1109. return rc;
  1110. rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
  1111. DRV_NAME);
  1112. if (rc == -EBUSY)
  1113. pcim_pin_device(pdev);
  1114. if (rc)
  1115. return rc;
  1116. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  1117. if (rc)
  1118. return rc;
  1119. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  1120. if (rc)
  1121. return rc;
  1122. probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
  1123. if (probe_ent == NULL)
  1124. return -ENOMEM;
  1125. probe_ent->dev = pci_dev_to_dev(pdev);
  1126. INIT_LIST_HEAD(&probe_ent->node);
  1127. hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
  1128. if (!hpriv)
  1129. return -ENOMEM;
  1130. probe_ent->sht = pdc_port_info[board_idx].sht;
  1131. probe_ent->port_flags = pdc_port_info[board_idx].flags;
  1132. probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
  1133. probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
  1134. probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
  1135. probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
  1136. probe_ent->irq = pdev->irq;
  1137. probe_ent->irq_flags = IRQF_SHARED;
  1138. probe_ent->iomap = pcim_iomap_table(pdev);
  1139. probe_ent->private_data = hpriv;
  1140. base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
  1141. probe_ent->n_ports = 4;
  1142. pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
  1143. pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
  1144. pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
  1145. pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
  1146. pci_set_master(pdev);
  1147. /* initialize adapter */
  1148. /* initialize local dimm */
  1149. if (pdc20621_dimm_init(probe_ent))
  1150. return -ENOMEM;
  1151. pdc_20621_init(probe_ent);
  1152. if (!ata_device_add(probe_ent))
  1153. return -ENODEV;
  1154. devm_kfree(&pdev->dev, probe_ent);
  1155. return 0;
  1156. }
  1157. static int __init pdc_sata_init(void)
  1158. {
  1159. return pci_register_driver(&pdc_sata_pci_driver);
  1160. }
  1161. static void __exit pdc_sata_exit(void)
  1162. {
  1163. pci_unregister_driver(&pdc_sata_pci_driver);
  1164. }
  1165. MODULE_AUTHOR("Jeff Garzik");
  1166. MODULE_DESCRIPTION("Promise SATA low-level driver");
  1167. MODULE_LICENSE("GPL");
  1168. MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
  1169. MODULE_VERSION(DRV_VERSION);
  1170. module_init(pdc_sata_init);
  1171. module_exit(pdc_sata_exit);