sata_svw.c 15 KB

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  1. /*
  2. * sata_svw.c - ServerWorks / Apple K2 SATA
  3. *
  4. * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
  5. * Jeff Garzik <jgarzik@pobox.com>
  6. * Please ALWAYS copy linux-ide@vger.kernel.org
  7. * on emails.
  8. *
  9. * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
  10. *
  11. * Bits from Jeff Garzik, Copyright RedHat, Inc.
  12. *
  13. * This driver probably works with non-Apple versions of the
  14. * Broadcom chipset...
  15. *
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License as published by
  19. * the Free Software Foundation; either version 2, or (at your option)
  20. * any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; see the file COPYING. If not, write to
  29. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  30. *
  31. *
  32. * libata documentation is available via 'make {ps|pdf}docs',
  33. * as Documentation/DocBook/libata.*
  34. *
  35. * Hardware documentation available under NDA.
  36. *
  37. */
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/pci.h>
  41. #include <linux/init.h>
  42. #include <linux/blkdev.h>
  43. #include <linux/delay.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/device.h>
  46. #include <scsi/scsi_host.h>
  47. #include <linux/libata.h>
  48. #ifdef CONFIG_PPC_OF
  49. #include <asm/prom.h>
  50. #include <asm/pci-bridge.h>
  51. #endif /* CONFIG_PPC_OF */
  52. #define DRV_NAME "sata_svw"
  53. #define DRV_VERSION "2.1"
  54. enum {
  55. K2_FLAG_NO_ATAPI_DMA = (1 << 29),
  56. /* Taskfile registers offsets */
  57. K2_SATA_TF_CMD_OFFSET = 0x00,
  58. K2_SATA_TF_DATA_OFFSET = 0x00,
  59. K2_SATA_TF_ERROR_OFFSET = 0x04,
  60. K2_SATA_TF_NSECT_OFFSET = 0x08,
  61. K2_SATA_TF_LBAL_OFFSET = 0x0c,
  62. K2_SATA_TF_LBAM_OFFSET = 0x10,
  63. K2_SATA_TF_LBAH_OFFSET = 0x14,
  64. K2_SATA_TF_DEVICE_OFFSET = 0x18,
  65. K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
  66. K2_SATA_TF_CTL_OFFSET = 0x20,
  67. /* DMA base */
  68. K2_SATA_DMA_CMD_OFFSET = 0x30,
  69. /* SCRs base */
  70. K2_SATA_SCR_STATUS_OFFSET = 0x40,
  71. K2_SATA_SCR_ERROR_OFFSET = 0x44,
  72. K2_SATA_SCR_CONTROL_OFFSET = 0x48,
  73. /* Others */
  74. K2_SATA_SICR1_OFFSET = 0x80,
  75. K2_SATA_SICR2_OFFSET = 0x84,
  76. K2_SATA_SIM_OFFSET = 0x88,
  77. /* Port stride */
  78. K2_SATA_PORT_OFFSET = 0x100,
  79. board_svw4 = 0,
  80. board_svw8 = 1,
  81. };
  82. static const struct k2_board_info {
  83. unsigned int n_ports;
  84. unsigned long port_flags;
  85. } k2_board_info[] = {
  86. /* board_svw4 */
  87. { 4, K2_FLAG_NO_ATAPI_DMA },
  88. /* board_svw8 */
  89. { 8, K2_FLAG_NO_ATAPI_DMA },
  90. };
  91. static u8 k2_stat_check_status(struct ata_port *ap);
  92. static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
  93. {
  94. if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
  95. return -1; /* ATAPI DMA not supported */
  96. return 0;
  97. }
  98. static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  99. {
  100. if (sc_reg > SCR_CONTROL)
  101. return 0xffffffffU;
  102. return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
  103. }
  104. static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  105. u32 val)
  106. {
  107. if (sc_reg > SCR_CONTROL)
  108. return;
  109. writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
  110. }
  111. static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
  112. {
  113. struct ata_ioports *ioaddr = &ap->ioaddr;
  114. unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
  115. if (tf->ctl != ap->last_ctl) {
  116. writeb(tf->ctl, ioaddr->ctl_addr);
  117. ap->last_ctl = tf->ctl;
  118. ata_wait_idle(ap);
  119. }
  120. if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
  121. writew(tf->feature | (((u16)tf->hob_feature) << 8),
  122. ioaddr->feature_addr);
  123. writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
  124. ioaddr->nsect_addr);
  125. writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
  126. ioaddr->lbal_addr);
  127. writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
  128. ioaddr->lbam_addr);
  129. writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
  130. ioaddr->lbah_addr);
  131. } else if (is_addr) {
  132. writew(tf->feature, ioaddr->feature_addr);
  133. writew(tf->nsect, ioaddr->nsect_addr);
  134. writew(tf->lbal, ioaddr->lbal_addr);
  135. writew(tf->lbam, ioaddr->lbam_addr);
  136. writew(tf->lbah, ioaddr->lbah_addr);
  137. }
  138. if (tf->flags & ATA_TFLAG_DEVICE)
  139. writeb(tf->device, ioaddr->device_addr);
  140. ata_wait_idle(ap);
  141. }
  142. static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
  143. {
  144. struct ata_ioports *ioaddr = &ap->ioaddr;
  145. u16 nsect, lbal, lbam, lbah, feature;
  146. tf->command = k2_stat_check_status(ap);
  147. tf->device = readw(ioaddr->device_addr);
  148. feature = readw(ioaddr->error_addr);
  149. nsect = readw(ioaddr->nsect_addr);
  150. lbal = readw(ioaddr->lbal_addr);
  151. lbam = readw(ioaddr->lbam_addr);
  152. lbah = readw(ioaddr->lbah_addr);
  153. tf->feature = feature;
  154. tf->nsect = nsect;
  155. tf->lbal = lbal;
  156. tf->lbam = lbam;
  157. tf->lbah = lbah;
  158. if (tf->flags & ATA_TFLAG_LBA48) {
  159. tf->hob_feature = feature >> 8;
  160. tf->hob_nsect = nsect >> 8;
  161. tf->hob_lbal = lbal >> 8;
  162. tf->hob_lbam = lbam >> 8;
  163. tf->hob_lbah = lbah >> 8;
  164. }
  165. }
  166. /**
  167. * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
  168. * @qc: Info associated with this ATA transaction.
  169. *
  170. * LOCKING:
  171. * spin_lock_irqsave(host lock)
  172. */
  173. static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
  174. {
  175. struct ata_port *ap = qc->ap;
  176. unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
  177. u8 dmactl;
  178. void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
  179. /* load PRD table addr. */
  180. mb(); /* make sure PRD table writes are visible to controller */
  181. writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
  182. /* specify data direction, triple-check start bit is clear */
  183. dmactl = readb(mmio + ATA_DMA_CMD);
  184. dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
  185. if (!rw)
  186. dmactl |= ATA_DMA_WR;
  187. writeb(dmactl, mmio + ATA_DMA_CMD);
  188. /* issue r/w command if this is not a ATA DMA command*/
  189. if (qc->tf.protocol != ATA_PROT_DMA)
  190. ap->ops->exec_command(ap, &qc->tf);
  191. }
  192. /**
  193. * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
  194. * @qc: Info associated with this ATA transaction.
  195. *
  196. * LOCKING:
  197. * spin_lock_irqsave(host lock)
  198. */
  199. static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
  200. {
  201. struct ata_port *ap = qc->ap;
  202. void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
  203. u8 dmactl;
  204. /* start host DMA transaction */
  205. dmactl = readb(mmio + ATA_DMA_CMD);
  206. writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
  207. /* There is a race condition in certain SATA controllers that can
  208. be seen when the r/w command is given to the controller before the
  209. host DMA is started. On a Read command, the controller would initiate
  210. the command to the drive even before it sees the DMA start. When there
  211. are very fast drives connected to the controller, or when the data request
  212. hits in the drive cache, there is the possibility that the drive returns a part
  213. or all of the requested data to the controller before the DMA start is issued.
  214. In this case, the controller would become confused as to what to do with the data.
  215. In the worst case when all the data is returned back to the controller, the
  216. controller could hang. In other cases it could return partial data returning
  217. in data corruption. This problem has been seen in PPC systems and can also appear
  218. on an system with very fast disks, where the SATA controller is sitting behind a
  219. number of bridges, and hence there is significant latency between the r/w command
  220. and the start command. */
  221. /* issue r/w command if the access is to ATA*/
  222. if (qc->tf.protocol == ATA_PROT_DMA)
  223. ap->ops->exec_command(ap, &qc->tf);
  224. }
  225. static u8 k2_stat_check_status(struct ata_port *ap)
  226. {
  227. return readl((void __iomem *) ap->ioaddr.status_addr);
  228. }
  229. #ifdef CONFIG_PPC_OF
  230. /*
  231. * k2_sata_proc_info
  232. * inout : decides on the direction of the dataflow and the meaning of the
  233. * variables
  234. * buffer: If inout==FALSE data is being written to it else read from it
  235. * *start: If inout==FALSE start of the valid data in the buffer
  236. * offset: If inout==FALSE offset from the beginning of the imaginary file
  237. * from which we start writing into the buffer
  238. * length: If inout==FALSE max number of bytes to be written into the buffer
  239. * else number of bytes in the buffer
  240. */
  241. static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
  242. off_t offset, int count, int inout)
  243. {
  244. struct ata_port *ap;
  245. struct device_node *np;
  246. int len, index;
  247. /* Find the ata_port */
  248. ap = ata_shost_to_port(shost);
  249. if (ap == NULL)
  250. return 0;
  251. /* Find the OF node for the PCI device proper */
  252. np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
  253. if (np == NULL)
  254. return 0;
  255. /* Match it to a port node */
  256. index = (ap == ap->host->ports[0]) ? 0 : 1;
  257. for (np = np->child; np != NULL; np = np->sibling) {
  258. const u32 *reg = get_property(np, "reg", NULL);
  259. if (!reg)
  260. continue;
  261. if (index == *reg)
  262. break;
  263. }
  264. if (np == NULL)
  265. return 0;
  266. len = sprintf(page, "devspec: %s\n", np->full_name);
  267. return len;
  268. }
  269. #endif /* CONFIG_PPC_OF */
  270. static struct scsi_host_template k2_sata_sht = {
  271. .module = THIS_MODULE,
  272. .name = DRV_NAME,
  273. .ioctl = ata_scsi_ioctl,
  274. .queuecommand = ata_scsi_queuecmd,
  275. .can_queue = ATA_DEF_QUEUE,
  276. .this_id = ATA_SHT_THIS_ID,
  277. .sg_tablesize = LIBATA_MAX_PRD,
  278. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  279. .emulated = ATA_SHT_EMULATED,
  280. .use_clustering = ATA_SHT_USE_CLUSTERING,
  281. .proc_name = DRV_NAME,
  282. .dma_boundary = ATA_DMA_BOUNDARY,
  283. .slave_configure = ata_scsi_slave_config,
  284. .slave_destroy = ata_scsi_slave_destroy,
  285. #ifdef CONFIG_PPC_OF
  286. .proc_info = k2_sata_proc_info,
  287. #endif
  288. .bios_param = ata_std_bios_param,
  289. };
  290. static const struct ata_port_operations k2_sata_ops = {
  291. .port_disable = ata_port_disable,
  292. .tf_load = k2_sata_tf_load,
  293. .tf_read = k2_sata_tf_read,
  294. .check_status = k2_stat_check_status,
  295. .exec_command = ata_exec_command,
  296. .dev_select = ata_std_dev_select,
  297. .check_atapi_dma = k2_sata_check_atapi_dma,
  298. .bmdma_setup = k2_bmdma_setup_mmio,
  299. .bmdma_start = k2_bmdma_start_mmio,
  300. .bmdma_stop = ata_bmdma_stop,
  301. .bmdma_status = ata_bmdma_status,
  302. .qc_prep = ata_qc_prep,
  303. .qc_issue = ata_qc_issue_prot,
  304. .data_xfer = ata_data_xfer,
  305. .freeze = ata_bmdma_freeze,
  306. .thaw = ata_bmdma_thaw,
  307. .error_handler = ata_bmdma_error_handler,
  308. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  309. .irq_handler = ata_interrupt,
  310. .irq_clear = ata_bmdma_irq_clear,
  311. .irq_on = ata_irq_on,
  312. .irq_ack = ata_irq_ack,
  313. .scr_read = k2_sata_scr_read,
  314. .scr_write = k2_sata_scr_write,
  315. .port_start = ata_port_start,
  316. };
  317. static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
  318. {
  319. port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
  320. port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
  321. port->feature_addr =
  322. port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
  323. port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
  324. port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
  325. port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
  326. port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
  327. port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
  328. port->command_addr =
  329. port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
  330. port->altstatus_addr =
  331. port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
  332. port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
  333. port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
  334. }
  335. static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  336. {
  337. static int printed_version;
  338. struct device *dev = &pdev->dev;
  339. struct ata_probe_ent *probe_ent;
  340. void __iomem *mmio_base;
  341. const struct k2_board_info *board_info =
  342. &k2_board_info[ent->driver_data];
  343. int rc;
  344. int i;
  345. if (!printed_version++)
  346. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  347. /*
  348. * If this driver happens to only be useful on Apple's K2, then
  349. * we should check that here as it has a normal Serverworks ID
  350. */
  351. rc = pcim_enable_device(pdev);
  352. if (rc)
  353. return rc;
  354. /*
  355. * Check if we have resources mapped at all (second function may
  356. * have been disabled by firmware)
  357. */
  358. if (pci_resource_len(pdev, 5) == 0)
  359. return -ENODEV;
  360. /* Request and iomap PCI regions */
  361. rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
  362. if (rc == -EBUSY)
  363. pcim_pin_device(pdev);
  364. if (rc)
  365. return rc;
  366. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  367. if (rc)
  368. return rc;
  369. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  370. if (rc)
  371. return rc;
  372. probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
  373. if (probe_ent == NULL)
  374. return -ENOMEM;
  375. probe_ent->dev = pci_dev_to_dev(pdev);
  376. INIT_LIST_HEAD(&probe_ent->node);
  377. probe_ent->sht = &k2_sata_sht;
  378. probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  379. ATA_FLAG_MMIO | board_info->port_flags;
  380. probe_ent->port_ops = &k2_sata_ops;
  381. probe_ent->n_ports = 4;
  382. probe_ent->irq = pdev->irq;
  383. probe_ent->irq_flags = IRQF_SHARED;
  384. probe_ent->iomap = pcim_iomap_table(pdev);
  385. /* We don't care much about the PIO/UDMA masks, but the core won't like us
  386. * if we don't fill these
  387. */
  388. probe_ent->pio_mask = 0x1f;
  389. probe_ent->mwdma_mask = 0x7;
  390. probe_ent->udma_mask = 0x7f;
  391. mmio_base = probe_ent->iomap[5];
  392. /* different controllers have different number of ports - currently 4 or 8 */
  393. /* All ports are on the same function. Multi-function device is no
  394. * longer available. This should not be seen in any system. */
  395. for (i = 0; i < board_info->n_ports; i++)
  396. k2_sata_setup_port(&probe_ent->port[i],
  397. mmio_base + i * K2_SATA_PORT_OFFSET);
  398. /* Clear a magic bit in SCR1 according to Darwin, those help
  399. * some funky seagate drives (though so far, those were already
  400. * set by the firmware on the machines I had access to)
  401. */
  402. writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
  403. mmio_base + K2_SATA_SICR1_OFFSET);
  404. /* Clear SATA error & interrupts we don't use */
  405. writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
  406. writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
  407. pci_set_master(pdev);
  408. if (!ata_device_add(probe_ent))
  409. return -ENODEV;
  410. devm_kfree(dev, probe_ent);
  411. return 0;
  412. }
  413. /* 0x240 is device ID for Apple K2 device
  414. * 0x241 is device ID for Serverworks Frodo4
  415. * 0x242 is device ID for Serverworks Frodo8
  416. * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
  417. * controller
  418. * */
  419. static const struct pci_device_id k2_sata_pci_tbl[] = {
  420. { PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 },
  421. { PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 },
  422. { PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 },
  423. { PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 },
  424. { PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 },
  425. { }
  426. };
  427. static struct pci_driver k2_sata_pci_driver = {
  428. .name = DRV_NAME,
  429. .id_table = k2_sata_pci_tbl,
  430. .probe = k2_sata_init_one,
  431. .remove = ata_pci_remove_one,
  432. };
  433. static int __init k2_sata_init(void)
  434. {
  435. return pci_register_driver(&k2_sata_pci_driver);
  436. }
  437. static void __exit k2_sata_exit(void)
  438. {
  439. pci_unregister_driver(&k2_sata_pci_driver);
  440. }
  441. MODULE_AUTHOR("Benjamin Herrenschmidt");
  442. MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
  443. MODULE_LICENSE("GPL");
  444. MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
  445. MODULE_VERSION(DRV_VERSION);
  446. module_init(k2_sata_init);
  447. module_exit(k2_sata_exit);