sata_promise.c 25 KB

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  1. /*
  2. * sata_promise.c - Promise SATA
  3. *
  4. * Maintained by: Jeff Garzik <jgarzik@pobox.com>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2003-2004 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * Hardware information only available under NDA.
  30. *
  31. */
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/pci.h>
  35. #include <linux/init.h>
  36. #include <linux/blkdev.h>
  37. #include <linux/delay.h>
  38. #include <linux/interrupt.h>
  39. #include <linux/device.h>
  40. #include <scsi/scsi.h>
  41. #include <scsi/scsi_host.h>
  42. #include <scsi/scsi_cmnd.h>
  43. #include <linux/libata.h>
  44. #include "sata_promise.h"
  45. #define DRV_NAME "sata_promise"
  46. #define DRV_VERSION "2.00"
  47. enum {
  48. PDC_MMIO_BAR = 3,
  49. /* register offsets */
  50. PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
  51. PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
  52. PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
  53. PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
  54. PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
  55. PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
  56. PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
  57. PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
  58. PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
  59. PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
  60. PDC_FLASH_CTL = 0x44, /* Flash control register */
  61. PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
  62. PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
  63. PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
  64. PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
  65. PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
  66. PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
  67. PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  68. (1<<8) | (1<<9) | (1<<10),
  69. board_2037x = 0, /* FastTrak S150 TX2plus */
  70. board_20319 = 1, /* FastTrak S150 TX4 */
  71. board_20619 = 2, /* FastTrak TX4000 */
  72. board_2057x = 3, /* SATAII150 Tx2plus */
  73. board_40518 = 4, /* SATAII150 Tx4 */
  74. PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
  75. /* Sequence counter control registers bit definitions */
  76. PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
  77. /* Feature register values */
  78. PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
  79. PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
  80. /* Device/Head register values */
  81. PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
  82. /* PDC_CTLSTAT bit definitions */
  83. PDC_DMA_ENABLE = (1 << 7),
  84. PDC_IRQ_DISABLE = (1 << 10),
  85. PDC_RESET = (1 << 11), /* HDMA reset */
  86. PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
  87. ATA_FLAG_MMIO |
  88. ATA_FLAG_PIO_POLLING,
  89. /* hp->flags bits */
  90. PDC_FLAG_GEN_II = (1 << 0),
  91. };
  92. struct pdc_port_priv {
  93. u8 *pkt;
  94. dma_addr_t pkt_dma;
  95. };
  96. struct pdc_host_priv {
  97. unsigned long flags;
  98. unsigned long port_flags[ATA_MAX_PORTS];
  99. };
  100. static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
  101. static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  102. static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  103. static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
  104. static int pdc_port_start(struct ata_port *ap);
  105. static void pdc_qc_prep(struct ata_queued_cmd *qc);
  106. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  107. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
  108. static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
  109. static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
  110. static void pdc_irq_clear(struct ata_port *ap);
  111. static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
  112. static void pdc_freeze(struct ata_port *ap);
  113. static void pdc_thaw(struct ata_port *ap);
  114. static void pdc_error_handler(struct ata_port *ap);
  115. static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
  116. static struct scsi_host_template pdc_ata_sht = {
  117. .module = THIS_MODULE,
  118. .name = DRV_NAME,
  119. .ioctl = ata_scsi_ioctl,
  120. .queuecommand = ata_scsi_queuecmd,
  121. .can_queue = ATA_DEF_QUEUE,
  122. .this_id = ATA_SHT_THIS_ID,
  123. .sg_tablesize = LIBATA_MAX_PRD,
  124. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  125. .emulated = ATA_SHT_EMULATED,
  126. .use_clustering = ATA_SHT_USE_CLUSTERING,
  127. .proc_name = DRV_NAME,
  128. .dma_boundary = ATA_DMA_BOUNDARY,
  129. .slave_configure = ata_scsi_slave_config,
  130. .slave_destroy = ata_scsi_slave_destroy,
  131. .bios_param = ata_std_bios_param,
  132. };
  133. static const struct ata_port_operations pdc_sata_ops = {
  134. .port_disable = ata_port_disable,
  135. .tf_load = pdc_tf_load_mmio,
  136. .tf_read = ata_tf_read,
  137. .check_status = ata_check_status,
  138. .exec_command = pdc_exec_command_mmio,
  139. .dev_select = ata_std_dev_select,
  140. .check_atapi_dma = pdc_check_atapi_dma,
  141. .qc_prep = pdc_qc_prep,
  142. .qc_issue = pdc_qc_issue_prot,
  143. .freeze = pdc_freeze,
  144. .thaw = pdc_thaw,
  145. .error_handler = pdc_error_handler,
  146. .post_internal_cmd = pdc_post_internal_cmd,
  147. .data_xfer = ata_data_xfer,
  148. .irq_handler = pdc_interrupt,
  149. .irq_clear = pdc_irq_clear,
  150. .irq_on = ata_irq_on,
  151. .irq_ack = ata_irq_ack,
  152. .scr_read = pdc_sata_scr_read,
  153. .scr_write = pdc_sata_scr_write,
  154. .port_start = pdc_port_start,
  155. };
  156. /* First-generation chips need a more restrictive ->check_atapi_dma op */
  157. static const struct ata_port_operations pdc_old_sata_ops = {
  158. .port_disable = ata_port_disable,
  159. .tf_load = pdc_tf_load_mmio,
  160. .tf_read = ata_tf_read,
  161. .check_status = ata_check_status,
  162. .exec_command = pdc_exec_command_mmio,
  163. .dev_select = ata_std_dev_select,
  164. .check_atapi_dma = pdc_old_check_atapi_dma,
  165. .qc_prep = pdc_qc_prep,
  166. .qc_issue = pdc_qc_issue_prot,
  167. .freeze = pdc_freeze,
  168. .thaw = pdc_thaw,
  169. .error_handler = pdc_error_handler,
  170. .post_internal_cmd = pdc_post_internal_cmd,
  171. .data_xfer = ata_data_xfer,
  172. .irq_handler = pdc_interrupt,
  173. .irq_clear = pdc_irq_clear,
  174. .irq_on = ata_irq_on,
  175. .irq_ack = ata_irq_ack,
  176. .scr_read = pdc_sata_scr_read,
  177. .scr_write = pdc_sata_scr_write,
  178. .port_start = pdc_port_start,
  179. };
  180. static const struct ata_port_operations pdc_pata_ops = {
  181. .port_disable = ata_port_disable,
  182. .tf_load = pdc_tf_load_mmio,
  183. .tf_read = ata_tf_read,
  184. .check_status = ata_check_status,
  185. .exec_command = pdc_exec_command_mmio,
  186. .dev_select = ata_std_dev_select,
  187. .check_atapi_dma = pdc_check_atapi_dma,
  188. .qc_prep = pdc_qc_prep,
  189. .qc_issue = pdc_qc_issue_prot,
  190. .freeze = pdc_freeze,
  191. .thaw = pdc_thaw,
  192. .error_handler = pdc_error_handler,
  193. .post_internal_cmd = pdc_post_internal_cmd,
  194. .data_xfer = ata_data_xfer,
  195. .irq_handler = pdc_interrupt,
  196. .irq_clear = pdc_irq_clear,
  197. .irq_on = ata_irq_on,
  198. .irq_ack = ata_irq_ack,
  199. .port_start = pdc_port_start,
  200. };
  201. static const struct ata_port_info pdc_port_info[] = {
  202. /* board_2037x */
  203. {
  204. .sht = &pdc_ata_sht,
  205. .flags = PDC_COMMON_FLAGS,
  206. .pio_mask = 0x1f, /* pio0-4 */
  207. .mwdma_mask = 0x07, /* mwdma0-2 */
  208. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  209. .port_ops = &pdc_old_sata_ops,
  210. },
  211. /* board_20319 */
  212. {
  213. .sht = &pdc_ata_sht,
  214. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  215. .pio_mask = 0x1f, /* pio0-4 */
  216. .mwdma_mask = 0x07, /* mwdma0-2 */
  217. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  218. .port_ops = &pdc_old_sata_ops,
  219. },
  220. /* board_20619 */
  221. {
  222. .sht = &pdc_ata_sht,
  223. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
  224. .pio_mask = 0x1f, /* pio0-4 */
  225. .mwdma_mask = 0x07, /* mwdma0-2 */
  226. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  227. .port_ops = &pdc_pata_ops,
  228. },
  229. /* board_2057x */
  230. {
  231. .sht = &pdc_ata_sht,
  232. .flags = PDC_COMMON_FLAGS,
  233. .pio_mask = 0x1f, /* pio0-4 */
  234. .mwdma_mask = 0x07, /* mwdma0-2 */
  235. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  236. .port_ops = &pdc_sata_ops,
  237. },
  238. /* board_40518 */
  239. {
  240. .sht = &pdc_ata_sht,
  241. .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
  242. .pio_mask = 0x1f, /* pio0-4 */
  243. .mwdma_mask = 0x07, /* mwdma0-2 */
  244. .udma_mask = 0x7f, /* udma0-6 ; FIXME */
  245. .port_ops = &pdc_sata_ops,
  246. },
  247. };
  248. static const struct pci_device_id pdc_ata_pci_tbl[] = {
  249. { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
  250. { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
  251. { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
  252. { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
  253. { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
  254. { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
  255. { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
  256. { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
  257. { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
  258. { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
  259. { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
  260. { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
  261. { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
  262. { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
  263. { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
  264. { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
  265. { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
  266. { } /* terminate list */
  267. };
  268. static struct pci_driver pdc_ata_pci_driver = {
  269. .name = DRV_NAME,
  270. .id_table = pdc_ata_pci_tbl,
  271. .probe = pdc_ata_init_one,
  272. .remove = ata_pci_remove_one,
  273. };
  274. static int pdc_port_start(struct ata_port *ap)
  275. {
  276. struct device *dev = ap->host->dev;
  277. struct pdc_host_priv *hp = ap->host->private_data;
  278. struct pdc_port_priv *pp;
  279. int rc;
  280. /* fix up port flags and cable type for SATA+PATA chips */
  281. ap->flags |= hp->port_flags[ap->port_no];
  282. if (ap->flags & ATA_FLAG_SATA)
  283. ap->cbl = ATA_CBL_SATA;
  284. rc = ata_port_start(ap);
  285. if (rc)
  286. return rc;
  287. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  288. if (!pp)
  289. return -ENOMEM;
  290. pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
  291. if (!pp->pkt)
  292. return -ENOMEM;
  293. ap->private_data = pp;
  294. /* fix up PHYMODE4 align timing */
  295. if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
  296. void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
  297. unsigned int tmp;
  298. tmp = readl(mmio + 0x014);
  299. tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
  300. writel(tmp, mmio + 0x014);
  301. }
  302. return 0;
  303. }
  304. static void pdc_reset_port(struct ata_port *ap)
  305. {
  306. void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
  307. unsigned int i;
  308. u32 tmp;
  309. for (i = 11; i > 0; i--) {
  310. tmp = readl(mmio);
  311. if (tmp & PDC_RESET)
  312. break;
  313. udelay(100);
  314. tmp |= PDC_RESET;
  315. writel(tmp, mmio);
  316. }
  317. tmp &= ~PDC_RESET;
  318. writel(tmp, mmio);
  319. readl(mmio); /* flush */
  320. }
  321. static void pdc_pata_cbl_detect(struct ata_port *ap)
  322. {
  323. u8 tmp;
  324. void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
  325. tmp = readb(mmio);
  326. if (tmp & 0x01) {
  327. ap->cbl = ATA_CBL_PATA40;
  328. ap->udma_mask &= ATA_UDMA_MASK_40C;
  329. } else
  330. ap->cbl = ATA_CBL_PATA80;
  331. }
  332. static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  333. {
  334. if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
  335. return 0xffffffffU;
  336. return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
  337. }
  338. static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  339. u32 val)
  340. {
  341. if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
  342. return;
  343. writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
  344. }
  345. static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
  346. {
  347. struct ata_port *ap = qc->ap;
  348. dma_addr_t sg_table = ap->prd_dma;
  349. unsigned int cdb_len = qc->dev->cdb_len;
  350. u8 *cdb = qc->cdb;
  351. struct pdc_port_priv *pp = ap->private_data;
  352. u8 *buf = pp->pkt;
  353. u32 *buf32 = (u32 *) buf;
  354. unsigned int dev_sel, feature, nbytes;
  355. /* set control bits (byte 0), zero delay seq id (byte 3),
  356. * and seq id (byte 2)
  357. */
  358. switch (qc->tf.protocol) {
  359. case ATA_PROT_ATAPI_DMA:
  360. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  361. buf32[0] = cpu_to_le32(PDC_PKT_READ);
  362. else
  363. buf32[0] = 0;
  364. break;
  365. case ATA_PROT_ATAPI_NODATA:
  366. buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
  367. break;
  368. default:
  369. BUG();
  370. break;
  371. }
  372. buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
  373. buf32[2] = 0; /* no next-packet */
  374. /* select drive */
  375. if (sata_scr_valid(ap)) {
  376. dev_sel = PDC_DEVICE_SATA;
  377. } else {
  378. dev_sel = ATA_DEVICE_OBS;
  379. if (qc->dev->devno != 0)
  380. dev_sel |= ATA_DEV1;
  381. }
  382. buf[12] = (1 << 5) | ATA_REG_DEVICE;
  383. buf[13] = dev_sel;
  384. buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
  385. buf[15] = dev_sel; /* once more, waiting for BSY to clear */
  386. buf[16] = (1 << 5) | ATA_REG_NSECT;
  387. buf[17] = 0x00;
  388. buf[18] = (1 << 5) | ATA_REG_LBAL;
  389. buf[19] = 0x00;
  390. /* set feature and byte counter registers */
  391. if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
  392. feature = PDC_FEATURE_ATAPI_PIO;
  393. /* set byte counter register to real transfer byte count */
  394. nbytes = qc->nbytes;
  395. if (nbytes > 0xffff)
  396. nbytes = 0xffff;
  397. } else {
  398. feature = PDC_FEATURE_ATAPI_DMA;
  399. /* set byte counter register to 0 */
  400. nbytes = 0;
  401. }
  402. buf[20] = (1 << 5) | ATA_REG_FEATURE;
  403. buf[21] = feature;
  404. buf[22] = (1 << 5) | ATA_REG_BYTEL;
  405. buf[23] = nbytes & 0xFF;
  406. buf[24] = (1 << 5) | ATA_REG_BYTEH;
  407. buf[25] = (nbytes >> 8) & 0xFF;
  408. /* send ATAPI packet command 0xA0 */
  409. buf[26] = (1 << 5) | ATA_REG_CMD;
  410. buf[27] = ATA_CMD_PACKET;
  411. /* select drive and check DRQ */
  412. buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
  413. buf[29] = dev_sel;
  414. /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
  415. BUG_ON(cdb_len & ~0x1E);
  416. /* append the CDB as the final part */
  417. buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
  418. memcpy(buf+31, cdb, cdb_len);
  419. }
  420. static void pdc_qc_prep(struct ata_queued_cmd *qc)
  421. {
  422. struct pdc_port_priv *pp = qc->ap->private_data;
  423. unsigned int i;
  424. VPRINTK("ENTER\n");
  425. switch (qc->tf.protocol) {
  426. case ATA_PROT_DMA:
  427. ata_qc_prep(qc);
  428. /* fall through */
  429. case ATA_PROT_NODATA:
  430. i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
  431. qc->dev->devno, pp->pkt);
  432. if (qc->tf.flags & ATA_TFLAG_LBA48)
  433. i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
  434. else
  435. i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
  436. pdc_pkt_footer(&qc->tf, pp->pkt, i);
  437. break;
  438. case ATA_PROT_ATAPI:
  439. ata_qc_prep(qc);
  440. break;
  441. case ATA_PROT_ATAPI_DMA:
  442. ata_qc_prep(qc);
  443. /*FALLTHROUGH*/
  444. case ATA_PROT_ATAPI_NODATA:
  445. pdc_atapi_pkt(qc);
  446. break;
  447. default:
  448. break;
  449. }
  450. }
  451. static void pdc_freeze(struct ata_port *ap)
  452. {
  453. void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
  454. u32 tmp;
  455. tmp = readl(mmio + PDC_CTLSTAT);
  456. tmp |= PDC_IRQ_DISABLE;
  457. tmp &= ~PDC_DMA_ENABLE;
  458. writel(tmp, mmio + PDC_CTLSTAT);
  459. readl(mmio + PDC_CTLSTAT); /* flush */
  460. }
  461. static void pdc_thaw(struct ata_port *ap)
  462. {
  463. void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
  464. u32 tmp;
  465. /* clear IRQ */
  466. readl(mmio + PDC_INT_SEQMASK);
  467. /* turn IRQ back on */
  468. tmp = readl(mmio + PDC_CTLSTAT);
  469. tmp &= ~PDC_IRQ_DISABLE;
  470. writel(tmp, mmio + PDC_CTLSTAT);
  471. readl(mmio + PDC_CTLSTAT); /* flush */
  472. }
  473. static int pdc_pre_reset(struct ata_port *ap)
  474. {
  475. if (!sata_scr_valid(ap))
  476. pdc_pata_cbl_detect(ap);
  477. return ata_std_prereset(ap);
  478. }
  479. static void pdc_error_handler(struct ata_port *ap)
  480. {
  481. ata_reset_fn_t hardreset;
  482. if (!(ap->pflags & ATA_PFLAG_FROZEN))
  483. pdc_reset_port(ap);
  484. hardreset = NULL;
  485. if (sata_scr_valid(ap))
  486. hardreset = sata_std_hardreset;
  487. /* perform recovery */
  488. ata_do_eh(ap, pdc_pre_reset, ata_std_softreset, hardreset,
  489. ata_std_postreset);
  490. }
  491. static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
  492. {
  493. struct ata_port *ap = qc->ap;
  494. if (qc->flags & ATA_QCFLAG_FAILED)
  495. qc->err_mask |= AC_ERR_OTHER;
  496. /* make DMA engine forget about the failed command */
  497. if (qc->err_mask)
  498. pdc_reset_port(ap);
  499. }
  500. static inline unsigned int pdc_host_intr( struct ata_port *ap,
  501. struct ata_queued_cmd *qc)
  502. {
  503. unsigned int handled = 0;
  504. u32 tmp;
  505. void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
  506. tmp = readl(mmio);
  507. if (tmp & PDC_ERR_MASK) {
  508. qc->err_mask |= AC_ERR_DEV;
  509. pdc_reset_port(ap);
  510. }
  511. switch (qc->tf.protocol) {
  512. case ATA_PROT_DMA:
  513. case ATA_PROT_NODATA:
  514. case ATA_PROT_ATAPI_DMA:
  515. case ATA_PROT_ATAPI_NODATA:
  516. qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
  517. ata_qc_complete(qc);
  518. handled = 1;
  519. break;
  520. default:
  521. ap->stats.idle_irq++;
  522. break;
  523. }
  524. return handled;
  525. }
  526. static void pdc_irq_clear(struct ata_port *ap)
  527. {
  528. struct ata_host *host = ap->host;
  529. void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
  530. readl(mmio + PDC_INT_SEQMASK);
  531. }
  532. static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
  533. {
  534. struct ata_host *host = dev_instance;
  535. struct ata_port *ap;
  536. u32 mask = 0;
  537. unsigned int i, tmp;
  538. unsigned int handled = 0;
  539. void __iomem *mmio_base;
  540. VPRINTK("ENTER\n");
  541. if (!host || !host->iomap[PDC_MMIO_BAR]) {
  542. VPRINTK("QUICK EXIT\n");
  543. return IRQ_NONE;
  544. }
  545. mmio_base = host->iomap[PDC_MMIO_BAR];
  546. /* reading should also clear interrupts */
  547. mask = readl(mmio_base + PDC_INT_SEQMASK);
  548. if (mask == 0xffffffff) {
  549. VPRINTK("QUICK EXIT 2\n");
  550. return IRQ_NONE;
  551. }
  552. spin_lock(&host->lock);
  553. mask &= 0xffff; /* only 16 tags possible */
  554. if (!mask) {
  555. VPRINTK("QUICK EXIT 3\n");
  556. goto done_irq;
  557. }
  558. writel(mask, mmio_base + PDC_INT_SEQMASK);
  559. for (i = 0; i < host->n_ports; i++) {
  560. VPRINTK("port %u\n", i);
  561. ap = host->ports[i];
  562. tmp = mask & (1 << (i + 1));
  563. if (tmp && ap &&
  564. !(ap->flags & ATA_FLAG_DISABLED)) {
  565. struct ata_queued_cmd *qc;
  566. qc = ata_qc_from_tag(ap, ap->active_tag);
  567. if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
  568. handled += pdc_host_intr(ap, qc);
  569. }
  570. }
  571. VPRINTK("EXIT\n");
  572. done_irq:
  573. spin_unlock(&host->lock);
  574. return IRQ_RETVAL(handled);
  575. }
  576. static inline void pdc_packet_start(struct ata_queued_cmd *qc)
  577. {
  578. struct ata_port *ap = qc->ap;
  579. struct pdc_port_priv *pp = ap->private_data;
  580. void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
  581. unsigned int port_no = ap->port_no;
  582. u8 seq = (u8) (port_no + 1);
  583. VPRINTK("ENTER, ap %p\n", ap);
  584. writel(0x00000001, mmio + (seq * 4));
  585. readl(mmio + (seq * 4)); /* flush */
  586. pp->pkt[2] = seq;
  587. wmb(); /* flush PRD, pkt writes */
  588. writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
  589. readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
  590. }
  591. static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
  592. {
  593. switch (qc->tf.protocol) {
  594. case ATA_PROT_ATAPI_NODATA:
  595. if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
  596. break;
  597. /*FALLTHROUGH*/
  598. case ATA_PROT_ATAPI_DMA:
  599. case ATA_PROT_DMA:
  600. case ATA_PROT_NODATA:
  601. pdc_packet_start(qc);
  602. return 0;
  603. default:
  604. break;
  605. }
  606. return ata_qc_issue_prot(qc);
  607. }
  608. static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  609. {
  610. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  611. tf->protocol == ATA_PROT_NODATA);
  612. ata_tf_load(ap, tf);
  613. }
  614. static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
  615. {
  616. WARN_ON (tf->protocol == ATA_PROT_DMA ||
  617. tf->protocol == ATA_PROT_NODATA);
  618. ata_exec_command(ap, tf);
  619. }
  620. static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
  621. {
  622. u8 *scsicmd = qc->scsicmd->cmnd;
  623. int pio = 1; /* atapi dma off by default */
  624. /* Whitelist commands that may use DMA. */
  625. switch (scsicmd[0]) {
  626. case WRITE_12:
  627. case WRITE_10:
  628. case WRITE_6:
  629. case READ_12:
  630. case READ_10:
  631. case READ_6:
  632. case 0xad: /* READ_DVD_STRUCTURE */
  633. case 0xbe: /* READ_CD */
  634. pio = 0;
  635. }
  636. /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
  637. if (scsicmd[0] == WRITE_10) {
  638. unsigned int lba;
  639. lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
  640. if (lba >= 0xFFFF4FA2)
  641. pio = 1;
  642. }
  643. return pio;
  644. }
  645. static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
  646. {
  647. struct ata_port *ap = qc->ap;
  648. /* First generation chips cannot use ATAPI DMA on SATA ports */
  649. if (sata_scr_valid(ap))
  650. return 1;
  651. return pdc_check_atapi_dma(qc);
  652. }
  653. static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base,
  654. void __iomem *scr_addr)
  655. {
  656. port->cmd_addr = base;
  657. port->data_addr = base;
  658. port->feature_addr =
  659. port->error_addr = base + 0x4;
  660. port->nsect_addr = base + 0x8;
  661. port->lbal_addr = base + 0xc;
  662. port->lbam_addr = base + 0x10;
  663. port->lbah_addr = base + 0x14;
  664. port->device_addr = base + 0x18;
  665. port->command_addr =
  666. port->status_addr = base + 0x1c;
  667. port->altstatus_addr =
  668. port->ctl_addr = base + 0x38;
  669. port->scr_addr = scr_addr;
  670. }
  671. static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
  672. {
  673. void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
  674. struct pdc_host_priv *hp = pe->private_data;
  675. int hotplug_offset;
  676. u32 tmp;
  677. if (hp->flags & PDC_FLAG_GEN_II)
  678. hotplug_offset = PDC2_SATA_PLUG_CSR;
  679. else
  680. hotplug_offset = PDC_SATA_PLUG_CSR;
  681. /*
  682. * Except for the hotplug stuff, this is voodoo from the
  683. * Promise driver. Label this entire section
  684. * "TODO: figure out why we do this"
  685. */
  686. /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
  687. tmp = readl(mmio + PDC_FLASH_CTL);
  688. tmp |= 0x02000; /* bit 13 (enable bmr burst) */
  689. if (!(hp->flags & PDC_FLAG_GEN_II))
  690. tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
  691. writel(tmp, mmio + PDC_FLASH_CTL);
  692. /* clear plug/unplug flags for all ports */
  693. tmp = readl(mmio + hotplug_offset);
  694. writel(tmp | 0xff, mmio + hotplug_offset);
  695. /* mask plug/unplug ints */
  696. tmp = readl(mmio + hotplug_offset);
  697. writel(tmp | 0xff0000, mmio + hotplug_offset);
  698. /* don't initialise TBG or SLEW on 2nd generation chips */
  699. if (hp->flags & PDC_FLAG_GEN_II)
  700. return;
  701. /* reduce TBG clock to 133 Mhz. */
  702. tmp = readl(mmio + PDC_TBG_MODE);
  703. tmp &= ~0x30000; /* clear bit 17, 16*/
  704. tmp |= 0x10000; /* set bit 17:16 = 0:1 */
  705. writel(tmp, mmio + PDC_TBG_MODE);
  706. readl(mmio + PDC_TBG_MODE); /* flush */
  707. msleep(10);
  708. /* adjust slew rate control register. */
  709. tmp = readl(mmio + PDC_SLEW_CTL);
  710. tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
  711. tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
  712. writel(tmp, mmio + PDC_SLEW_CTL);
  713. }
  714. static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
  715. {
  716. static int printed_version;
  717. struct ata_probe_ent *probe_ent;
  718. struct pdc_host_priv *hp;
  719. void __iomem *base;
  720. unsigned int board_idx = (unsigned int) ent->driver_data;
  721. int rc;
  722. u8 tmp;
  723. if (!printed_version++)
  724. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  725. rc = pcim_enable_device(pdev);
  726. if (rc)
  727. return rc;
  728. rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
  729. if (rc == -EBUSY)
  730. pcim_pin_device(pdev);
  731. if (rc)
  732. return rc;
  733. rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
  734. if (rc)
  735. return rc;
  736. rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
  737. if (rc)
  738. return rc;
  739. probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
  740. if (probe_ent == NULL)
  741. return -ENOMEM;
  742. probe_ent->dev = pci_dev_to_dev(pdev);
  743. INIT_LIST_HEAD(&probe_ent->node);
  744. hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
  745. if (hp == NULL)
  746. return -ENOMEM;
  747. probe_ent->private_data = hp;
  748. probe_ent->sht = pdc_port_info[board_idx].sht;
  749. probe_ent->port_flags = pdc_port_info[board_idx].flags;
  750. probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
  751. probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
  752. probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
  753. probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
  754. probe_ent->irq = pdev->irq;
  755. probe_ent->irq_flags = IRQF_SHARED;
  756. probe_ent->iomap = pcim_iomap_table(pdev);
  757. base = probe_ent->iomap[PDC_MMIO_BAR];
  758. pdc_ata_setup_port(&probe_ent->port[0], base + 0x200, base + 0x400);
  759. pdc_ata_setup_port(&probe_ent->port[1], base + 0x280, base + 0x500);
  760. /* notice 4-port boards */
  761. switch (board_idx) {
  762. case board_40518:
  763. hp->flags |= PDC_FLAG_GEN_II;
  764. /* Fall through */
  765. case board_20319:
  766. probe_ent->n_ports = 4;
  767. pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, base + 0x600);
  768. pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, base + 0x700);
  769. break;
  770. case board_2057x:
  771. hp->flags |= PDC_FLAG_GEN_II;
  772. /* Fall through */
  773. case board_2037x:
  774. /* TX2plus boards also have a PATA port */
  775. tmp = readb(base + PDC_FLASH_CTL+1);
  776. if (!(tmp & 0x80)) {
  777. probe_ent->n_ports = 3;
  778. pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
  779. hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
  780. printk(KERN_INFO DRV_NAME " PATA port found\n");
  781. } else
  782. probe_ent->n_ports = 2;
  783. hp->port_flags[0] = ATA_FLAG_SATA;
  784. hp->port_flags[1] = ATA_FLAG_SATA;
  785. break;
  786. case board_20619:
  787. probe_ent->n_ports = 4;
  788. pdc_ata_setup_port(&probe_ent->port[2], base + 0x300, NULL);
  789. pdc_ata_setup_port(&probe_ent->port[3], base + 0x380, NULL);
  790. break;
  791. default:
  792. BUG();
  793. break;
  794. }
  795. pci_set_master(pdev);
  796. /* initialize adapter */
  797. pdc_host_init(board_idx, probe_ent);
  798. if (!ata_device_add(probe_ent))
  799. return -ENODEV;
  800. devm_kfree(&pdev->dev, probe_ent);
  801. return 0;
  802. }
  803. static int __init pdc_ata_init(void)
  804. {
  805. return pci_register_driver(&pdc_ata_pci_driver);
  806. }
  807. static void __exit pdc_ata_exit(void)
  808. {
  809. pci_unregister_driver(&pdc_ata_pci_driver);
  810. }
  811. MODULE_AUTHOR("Jeff Garzik");
  812. MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
  813. MODULE_LICENSE("GPL");
  814. MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
  815. MODULE_VERSION(DRV_VERSION);
  816. module_init(pdc_ata_init);
  817. module_exit(pdc_ata_exit);