sata_mv.c 63 KB

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  1. /*
  2. * sata_mv.c - Marvell SATA support
  3. *
  4. * Copyright 2005: EMC Corporation, all rights reserved.
  5. * Copyright 2005 Red Hat, Inc. All rights reserved.
  6. *
  7. * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/init.h>
  27. #include <linux/blkdev.h>
  28. #include <linux/delay.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/device.h>
  32. #include <scsi/scsi_host.h>
  33. #include <scsi/scsi_cmnd.h>
  34. #include <linux/libata.h>
  35. #define DRV_NAME "sata_mv"
  36. #define DRV_VERSION "0.8"
  37. enum {
  38. /* BAR's are enumerated in terms of pci_resource_start() terms */
  39. MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
  40. MV_IO_BAR = 2, /* offset 0x18: IO space */
  41. MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
  42. MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
  43. MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
  44. MV_PCI_REG_BASE = 0,
  45. MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
  46. MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
  47. MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
  48. MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
  49. MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
  50. MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
  51. MV_SATAHC0_REG_BASE = 0x20000,
  52. MV_FLASH_CTL = 0x1046c,
  53. MV_GPIO_PORT_CTL = 0x104f0,
  54. MV_RESET_CFG = 0x180d8,
  55. MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  56. MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
  57. MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
  58. MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
  59. MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
  60. MV_MAX_Q_DEPTH = 32,
  61. MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
  62. /* CRQB needs alignment on a 1KB boundary. Size == 1KB
  63. * CRPB needs alignment on a 256B boundary. Size == 256B
  64. * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
  65. * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
  66. */
  67. MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
  68. MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
  69. MV_MAX_SG_CT = 176,
  70. MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
  71. MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
  72. MV_PORTS_PER_HC = 4,
  73. /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
  74. MV_PORT_HC_SHIFT = 2,
  75. /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
  76. MV_PORT_MASK = 3,
  77. /* Host Flags */
  78. MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
  79. MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
  80. MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  81. ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
  82. ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
  83. MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
  84. CRQB_FLAG_READ = (1 << 0),
  85. CRQB_TAG_SHIFT = 1,
  86. CRQB_CMD_ADDR_SHIFT = 8,
  87. CRQB_CMD_CS = (0x2 << 11),
  88. CRQB_CMD_LAST = (1 << 15),
  89. CRPB_FLAG_STATUS_SHIFT = 8,
  90. EPRD_FLAG_END_OF_TBL = (1 << 31),
  91. /* PCI interface registers */
  92. PCI_COMMAND_OFS = 0xc00,
  93. PCI_MAIN_CMD_STS_OFS = 0xd30,
  94. STOP_PCI_MASTER = (1 << 2),
  95. PCI_MASTER_EMPTY = (1 << 3),
  96. GLOB_SFT_RST = (1 << 4),
  97. MV_PCI_MODE = 0xd00,
  98. MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
  99. MV_PCI_DISC_TIMER = 0xd04,
  100. MV_PCI_MSI_TRIGGER = 0xc38,
  101. MV_PCI_SERR_MASK = 0xc28,
  102. MV_PCI_XBAR_TMOUT = 0x1d04,
  103. MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
  104. MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
  105. MV_PCI_ERR_ATTRIBUTE = 0x1d48,
  106. MV_PCI_ERR_COMMAND = 0x1d50,
  107. PCI_IRQ_CAUSE_OFS = 0x1d58,
  108. PCI_IRQ_MASK_OFS = 0x1d5c,
  109. PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
  110. HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
  111. HC_MAIN_IRQ_MASK_OFS = 0x1d64,
  112. PORT0_ERR = (1 << 0), /* shift by port # */
  113. PORT0_DONE = (1 << 1), /* shift by port # */
  114. HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
  115. HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
  116. PCI_ERR = (1 << 18),
  117. TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
  118. TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
  119. PORTS_0_3_COAL_DONE = (1 << 8),
  120. PORTS_4_7_COAL_DONE = (1 << 17),
  121. PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
  122. GPIO_INT = (1 << 22),
  123. SELF_INT = (1 << 23),
  124. TWSI_INT = (1 << 24),
  125. HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
  126. HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
  127. HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
  128. PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
  129. HC_MAIN_RSVD),
  130. HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
  131. HC_MAIN_RSVD_5),
  132. /* SATAHC registers */
  133. HC_CFG_OFS = 0,
  134. HC_IRQ_CAUSE_OFS = 0x14,
  135. CRPB_DMA_DONE = (1 << 0), /* shift by port # */
  136. HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
  137. DEV_IRQ = (1 << 8), /* shift by port # */
  138. /* Shadow block registers */
  139. SHD_BLK_OFS = 0x100,
  140. SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
  141. /* SATA registers */
  142. SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
  143. SATA_ACTIVE_OFS = 0x350,
  144. PHY_MODE3 = 0x310,
  145. PHY_MODE4 = 0x314,
  146. PHY_MODE2 = 0x330,
  147. MV5_PHY_MODE = 0x74,
  148. MV5_LT_MODE = 0x30,
  149. MV5_PHY_CTL = 0x0C,
  150. SATA_INTERFACE_CTL = 0x050,
  151. MV_M2_PREAMP_MASK = 0x7e0,
  152. /* Port registers */
  153. EDMA_CFG_OFS = 0,
  154. EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
  155. EDMA_CFG_NCQ = (1 << 5),
  156. EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
  157. EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
  158. EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
  159. EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
  160. EDMA_ERR_IRQ_MASK_OFS = 0xc,
  161. EDMA_ERR_D_PAR = (1 << 0),
  162. EDMA_ERR_PRD_PAR = (1 << 1),
  163. EDMA_ERR_DEV = (1 << 2),
  164. EDMA_ERR_DEV_DCON = (1 << 3),
  165. EDMA_ERR_DEV_CON = (1 << 4),
  166. EDMA_ERR_SERR = (1 << 5),
  167. EDMA_ERR_SELF_DIS = (1 << 7),
  168. EDMA_ERR_BIST_ASYNC = (1 << 8),
  169. EDMA_ERR_CRBQ_PAR = (1 << 9),
  170. EDMA_ERR_CRPB_PAR = (1 << 10),
  171. EDMA_ERR_INTRL_PAR = (1 << 11),
  172. EDMA_ERR_IORDY = (1 << 12),
  173. EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
  174. EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
  175. EDMA_ERR_LNK_DATA_RX = (0xf << 17),
  176. EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
  177. EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
  178. EDMA_ERR_TRANS_PROTO = (1 << 31),
  179. EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
  180. EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
  181. EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
  182. EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
  183. EDMA_ERR_LNK_DATA_RX |
  184. EDMA_ERR_LNK_DATA_TX |
  185. EDMA_ERR_TRANS_PROTO),
  186. EDMA_REQ_Q_BASE_HI_OFS = 0x10,
  187. EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
  188. EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
  189. EDMA_REQ_Q_PTR_SHIFT = 5,
  190. EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
  191. EDMA_RSP_Q_IN_PTR_OFS = 0x20,
  192. EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
  193. EDMA_RSP_Q_PTR_SHIFT = 3,
  194. EDMA_CMD_OFS = 0x28,
  195. EDMA_EN = (1 << 0),
  196. EDMA_DS = (1 << 1),
  197. ATA_RST = (1 << 2),
  198. EDMA_IORDY_TMOUT = 0x34,
  199. EDMA_ARB_CFG = 0x38,
  200. /* Host private flags (hp_flags) */
  201. MV_HP_FLAG_MSI = (1 << 0),
  202. MV_HP_ERRATA_50XXB0 = (1 << 1),
  203. MV_HP_ERRATA_50XXB2 = (1 << 2),
  204. MV_HP_ERRATA_60X1B2 = (1 << 3),
  205. MV_HP_ERRATA_60X1C0 = (1 << 4),
  206. MV_HP_ERRATA_XX42A0 = (1 << 5),
  207. MV_HP_50XX = (1 << 6),
  208. MV_HP_GEN_IIE = (1 << 7),
  209. /* Port private flags (pp_flags) */
  210. MV_PP_FLAG_EDMA_EN = (1 << 0),
  211. MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
  212. };
  213. #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
  214. #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
  215. #define IS_GEN_I(hpriv) IS_50XX(hpriv)
  216. #define IS_GEN_II(hpriv) IS_60XX(hpriv)
  217. #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
  218. enum {
  219. /* Our DMA boundary is determined by an ePRD being unable to handle
  220. * anything larger than 64KB
  221. */
  222. MV_DMA_BOUNDARY = 0xffffU,
  223. EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
  224. EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
  225. };
  226. enum chip_type {
  227. chip_504x,
  228. chip_508x,
  229. chip_5080,
  230. chip_604x,
  231. chip_608x,
  232. chip_6042,
  233. chip_7042,
  234. };
  235. /* Command ReQuest Block: 32B */
  236. struct mv_crqb {
  237. __le32 sg_addr;
  238. __le32 sg_addr_hi;
  239. __le16 ctrl_flags;
  240. __le16 ata_cmd[11];
  241. };
  242. struct mv_crqb_iie {
  243. __le32 addr;
  244. __le32 addr_hi;
  245. __le32 flags;
  246. __le32 len;
  247. __le32 ata_cmd[4];
  248. };
  249. /* Command ResPonse Block: 8B */
  250. struct mv_crpb {
  251. __le16 id;
  252. __le16 flags;
  253. __le32 tmstmp;
  254. };
  255. /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
  256. struct mv_sg {
  257. __le32 addr;
  258. __le32 flags_size;
  259. __le32 addr_hi;
  260. __le32 reserved;
  261. };
  262. struct mv_port_priv {
  263. struct mv_crqb *crqb;
  264. dma_addr_t crqb_dma;
  265. struct mv_crpb *crpb;
  266. dma_addr_t crpb_dma;
  267. struct mv_sg *sg_tbl;
  268. dma_addr_t sg_tbl_dma;
  269. u32 pp_flags;
  270. };
  271. struct mv_port_signal {
  272. u32 amps;
  273. u32 pre;
  274. };
  275. struct mv_host_priv;
  276. struct mv_hw_ops {
  277. void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
  278. unsigned int port);
  279. void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
  280. void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
  281. void __iomem *mmio);
  282. int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
  283. unsigned int n_hc);
  284. void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
  285. void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
  286. };
  287. struct mv_host_priv {
  288. u32 hp_flags;
  289. struct mv_port_signal signal[8];
  290. const struct mv_hw_ops *ops;
  291. };
  292. static void mv_irq_clear(struct ata_port *ap);
  293. static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
  294. static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
  295. static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
  296. static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
  297. static void mv_phy_reset(struct ata_port *ap);
  298. static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
  299. static int mv_port_start(struct ata_port *ap);
  300. static void mv_port_stop(struct ata_port *ap);
  301. static void mv_qc_prep(struct ata_queued_cmd *qc);
  302. static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
  303. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
  304. static irqreturn_t mv_interrupt(int irq, void *dev_instance);
  305. static void mv_eng_timeout(struct ata_port *ap);
  306. static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
  307. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  308. unsigned int port);
  309. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  310. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  311. void __iomem *mmio);
  312. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  313. unsigned int n_hc);
  314. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  315. static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
  316. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  317. unsigned int port);
  318. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
  319. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  320. void __iomem *mmio);
  321. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  322. unsigned int n_hc);
  323. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
  324. static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
  325. static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
  326. unsigned int port_no);
  327. static void mv_stop_and_reset(struct ata_port *ap);
  328. static struct scsi_host_template mv_sht = {
  329. .module = THIS_MODULE,
  330. .name = DRV_NAME,
  331. .ioctl = ata_scsi_ioctl,
  332. .queuecommand = ata_scsi_queuecmd,
  333. .can_queue = MV_USE_Q_DEPTH,
  334. .this_id = ATA_SHT_THIS_ID,
  335. .sg_tablesize = MV_MAX_SG_CT / 2,
  336. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  337. .emulated = ATA_SHT_EMULATED,
  338. .use_clustering = ATA_SHT_USE_CLUSTERING,
  339. .proc_name = DRV_NAME,
  340. .dma_boundary = MV_DMA_BOUNDARY,
  341. .slave_configure = ata_scsi_slave_config,
  342. .slave_destroy = ata_scsi_slave_destroy,
  343. .bios_param = ata_std_bios_param,
  344. };
  345. static const struct ata_port_operations mv5_ops = {
  346. .port_disable = ata_port_disable,
  347. .tf_load = ata_tf_load,
  348. .tf_read = ata_tf_read,
  349. .check_status = ata_check_status,
  350. .exec_command = ata_exec_command,
  351. .dev_select = ata_std_dev_select,
  352. .phy_reset = mv_phy_reset,
  353. .qc_prep = mv_qc_prep,
  354. .qc_issue = mv_qc_issue,
  355. .data_xfer = ata_data_xfer,
  356. .eng_timeout = mv_eng_timeout,
  357. .irq_handler = mv_interrupt,
  358. .irq_clear = mv_irq_clear,
  359. .irq_on = ata_irq_on,
  360. .irq_ack = ata_irq_ack,
  361. .scr_read = mv5_scr_read,
  362. .scr_write = mv5_scr_write,
  363. .port_start = mv_port_start,
  364. .port_stop = mv_port_stop,
  365. };
  366. static const struct ata_port_operations mv6_ops = {
  367. .port_disable = ata_port_disable,
  368. .tf_load = ata_tf_load,
  369. .tf_read = ata_tf_read,
  370. .check_status = ata_check_status,
  371. .exec_command = ata_exec_command,
  372. .dev_select = ata_std_dev_select,
  373. .phy_reset = mv_phy_reset,
  374. .qc_prep = mv_qc_prep,
  375. .qc_issue = mv_qc_issue,
  376. .data_xfer = ata_data_xfer,
  377. .eng_timeout = mv_eng_timeout,
  378. .irq_handler = mv_interrupt,
  379. .irq_clear = mv_irq_clear,
  380. .irq_on = ata_irq_on,
  381. .irq_ack = ata_irq_ack,
  382. .scr_read = mv_scr_read,
  383. .scr_write = mv_scr_write,
  384. .port_start = mv_port_start,
  385. .port_stop = mv_port_stop,
  386. };
  387. static const struct ata_port_operations mv_iie_ops = {
  388. .port_disable = ata_port_disable,
  389. .tf_load = ata_tf_load,
  390. .tf_read = ata_tf_read,
  391. .check_status = ata_check_status,
  392. .exec_command = ata_exec_command,
  393. .dev_select = ata_std_dev_select,
  394. .phy_reset = mv_phy_reset,
  395. .qc_prep = mv_qc_prep_iie,
  396. .qc_issue = mv_qc_issue,
  397. .data_xfer = ata_data_xfer,
  398. .eng_timeout = mv_eng_timeout,
  399. .irq_handler = mv_interrupt,
  400. .irq_clear = mv_irq_clear,
  401. .irq_on = ata_irq_on,
  402. .irq_ack = ata_irq_ack,
  403. .scr_read = mv_scr_read,
  404. .scr_write = mv_scr_write,
  405. .port_start = mv_port_start,
  406. .port_stop = mv_port_stop,
  407. };
  408. static const struct ata_port_info mv_port_info[] = {
  409. { /* chip_504x */
  410. .sht = &mv_sht,
  411. .flags = MV_COMMON_FLAGS,
  412. .pio_mask = 0x1f, /* pio0-4 */
  413. .udma_mask = 0x7f, /* udma0-6 */
  414. .port_ops = &mv5_ops,
  415. },
  416. { /* chip_508x */
  417. .sht = &mv_sht,
  418. .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
  419. .pio_mask = 0x1f, /* pio0-4 */
  420. .udma_mask = 0x7f, /* udma0-6 */
  421. .port_ops = &mv5_ops,
  422. },
  423. { /* chip_5080 */
  424. .sht = &mv_sht,
  425. .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
  426. .pio_mask = 0x1f, /* pio0-4 */
  427. .udma_mask = 0x7f, /* udma0-6 */
  428. .port_ops = &mv5_ops,
  429. },
  430. { /* chip_604x */
  431. .sht = &mv_sht,
  432. .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
  433. .pio_mask = 0x1f, /* pio0-4 */
  434. .udma_mask = 0x7f, /* udma0-6 */
  435. .port_ops = &mv6_ops,
  436. },
  437. { /* chip_608x */
  438. .sht = &mv_sht,
  439. .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
  440. MV_FLAG_DUAL_HC),
  441. .pio_mask = 0x1f, /* pio0-4 */
  442. .udma_mask = 0x7f, /* udma0-6 */
  443. .port_ops = &mv6_ops,
  444. },
  445. { /* chip_6042 */
  446. .sht = &mv_sht,
  447. .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
  448. .pio_mask = 0x1f, /* pio0-4 */
  449. .udma_mask = 0x7f, /* udma0-6 */
  450. .port_ops = &mv_iie_ops,
  451. },
  452. { /* chip_7042 */
  453. .sht = &mv_sht,
  454. .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
  455. .pio_mask = 0x1f, /* pio0-4 */
  456. .udma_mask = 0x7f, /* udma0-6 */
  457. .port_ops = &mv_iie_ops,
  458. },
  459. };
  460. static const struct pci_device_id mv_pci_tbl[] = {
  461. { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
  462. { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
  463. { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
  464. { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
  465. { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
  466. { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
  467. { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
  468. { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
  469. { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
  470. { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
  471. { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
  472. { } /* terminate list */
  473. };
  474. static struct pci_driver mv_pci_driver = {
  475. .name = DRV_NAME,
  476. .id_table = mv_pci_tbl,
  477. .probe = mv_init_one,
  478. .remove = ata_pci_remove_one,
  479. };
  480. static const struct mv_hw_ops mv5xxx_ops = {
  481. .phy_errata = mv5_phy_errata,
  482. .enable_leds = mv5_enable_leds,
  483. .read_preamp = mv5_read_preamp,
  484. .reset_hc = mv5_reset_hc,
  485. .reset_flash = mv5_reset_flash,
  486. .reset_bus = mv5_reset_bus,
  487. };
  488. static const struct mv_hw_ops mv6xxx_ops = {
  489. .phy_errata = mv6_phy_errata,
  490. .enable_leds = mv6_enable_leds,
  491. .read_preamp = mv6_read_preamp,
  492. .reset_hc = mv6_reset_hc,
  493. .reset_flash = mv6_reset_flash,
  494. .reset_bus = mv_reset_pci_bus,
  495. };
  496. /*
  497. * module options
  498. */
  499. static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
  500. /*
  501. * Functions
  502. */
  503. static inline void writelfl(unsigned long data, void __iomem *addr)
  504. {
  505. writel(data, addr);
  506. (void) readl(addr); /* flush to avoid PCI posted write */
  507. }
  508. static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
  509. {
  510. return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
  511. }
  512. static inline unsigned int mv_hc_from_port(unsigned int port)
  513. {
  514. return port >> MV_PORT_HC_SHIFT;
  515. }
  516. static inline unsigned int mv_hardport_from_port(unsigned int port)
  517. {
  518. return port & MV_PORT_MASK;
  519. }
  520. static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
  521. unsigned int port)
  522. {
  523. return mv_hc_base(base, mv_hc_from_port(port));
  524. }
  525. static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
  526. {
  527. return mv_hc_base_from_port(base, port) +
  528. MV_SATAHC_ARBTR_REG_SZ +
  529. (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
  530. }
  531. static inline void __iomem *mv_ap_base(struct ata_port *ap)
  532. {
  533. return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
  534. }
  535. static inline int mv_get_hc_count(unsigned long port_flags)
  536. {
  537. return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
  538. }
  539. static void mv_irq_clear(struct ata_port *ap)
  540. {
  541. }
  542. /**
  543. * mv_start_dma - Enable eDMA engine
  544. * @base: port base address
  545. * @pp: port private data
  546. *
  547. * Verify the local cache of the eDMA state is accurate with a
  548. * WARN_ON.
  549. *
  550. * LOCKING:
  551. * Inherited from caller.
  552. */
  553. static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
  554. {
  555. if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
  556. writelfl(EDMA_EN, base + EDMA_CMD_OFS);
  557. pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
  558. }
  559. WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
  560. }
  561. /**
  562. * mv_stop_dma - Disable eDMA engine
  563. * @ap: ATA channel to manipulate
  564. *
  565. * Verify the local cache of the eDMA state is accurate with a
  566. * WARN_ON.
  567. *
  568. * LOCKING:
  569. * Inherited from caller.
  570. */
  571. static void mv_stop_dma(struct ata_port *ap)
  572. {
  573. void __iomem *port_mmio = mv_ap_base(ap);
  574. struct mv_port_priv *pp = ap->private_data;
  575. u32 reg;
  576. int i;
  577. if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
  578. /* Disable EDMA if active. The disable bit auto clears.
  579. */
  580. writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
  581. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  582. } else {
  583. WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
  584. }
  585. /* now properly wait for the eDMA to stop */
  586. for (i = 1000; i > 0; i--) {
  587. reg = readl(port_mmio + EDMA_CMD_OFS);
  588. if (!(EDMA_EN & reg)) {
  589. break;
  590. }
  591. udelay(100);
  592. }
  593. if (EDMA_EN & reg) {
  594. ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
  595. /* FIXME: Consider doing a reset here to recover */
  596. }
  597. }
  598. #ifdef ATA_DEBUG
  599. static void mv_dump_mem(void __iomem *start, unsigned bytes)
  600. {
  601. int b, w;
  602. for (b = 0; b < bytes; ) {
  603. DPRINTK("%p: ", start + b);
  604. for (w = 0; b < bytes && w < 4; w++) {
  605. printk("%08x ",readl(start + b));
  606. b += sizeof(u32);
  607. }
  608. printk("\n");
  609. }
  610. }
  611. #endif
  612. static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
  613. {
  614. #ifdef ATA_DEBUG
  615. int b, w;
  616. u32 dw;
  617. for (b = 0; b < bytes; ) {
  618. DPRINTK("%02x: ", b);
  619. for (w = 0; b < bytes && w < 4; w++) {
  620. (void) pci_read_config_dword(pdev,b,&dw);
  621. printk("%08x ",dw);
  622. b += sizeof(u32);
  623. }
  624. printk("\n");
  625. }
  626. #endif
  627. }
  628. static void mv_dump_all_regs(void __iomem *mmio_base, int port,
  629. struct pci_dev *pdev)
  630. {
  631. #ifdef ATA_DEBUG
  632. void __iomem *hc_base = mv_hc_base(mmio_base,
  633. port >> MV_PORT_HC_SHIFT);
  634. void __iomem *port_base;
  635. int start_port, num_ports, p, start_hc, num_hcs, hc;
  636. if (0 > port) {
  637. start_hc = start_port = 0;
  638. num_ports = 8; /* shld be benign for 4 port devs */
  639. num_hcs = 2;
  640. } else {
  641. start_hc = port >> MV_PORT_HC_SHIFT;
  642. start_port = port;
  643. num_ports = num_hcs = 1;
  644. }
  645. DPRINTK("All registers for port(s) %u-%u:\n", start_port,
  646. num_ports > 1 ? num_ports - 1 : start_port);
  647. if (NULL != pdev) {
  648. DPRINTK("PCI config space regs:\n");
  649. mv_dump_pci_cfg(pdev, 0x68);
  650. }
  651. DPRINTK("PCI regs:\n");
  652. mv_dump_mem(mmio_base+0xc00, 0x3c);
  653. mv_dump_mem(mmio_base+0xd00, 0x34);
  654. mv_dump_mem(mmio_base+0xf00, 0x4);
  655. mv_dump_mem(mmio_base+0x1d00, 0x6c);
  656. for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
  657. hc_base = mv_hc_base(mmio_base, hc);
  658. DPRINTK("HC regs (HC %i):\n", hc);
  659. mv_dump_mem(hc_base, 0x1c);
  660. }
  661. for (p = start_port; p < start_port + num_ports; p++) {
  662. port_base = mv_port_base(mmio_base, p);
  663. DPRINTK("EDMA regs (port %i):\n",p);
  664. mv_dump_mem(port_base, 0x54);
  665. DPRINTK("SATA regs (port %i):\n",p);
  666. mv_dump_mem(port_base+0x300, 0x60);
  667. }
  668. #endif
  669. }
  670. static unsigned int mv_scr_offset(unsigned int sc_reg_in)
  671. {
  672. unsigned int ofs;
  673. switch (sc_reg_in) {
  674. case SCR_STATUS:
  675. case SCR_CONTROL:
  676. case SCR_ERROR:
  677. ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
  678. break;
  679. case SCR_ACTIVE:
  680. ofs = SATA_ACTIVE_OFS; /* active is not with the others */
  681. break;
  682. default:
  683. ofs = 0xffffffffU;
  684. break;
  685. }
  686. return ofs;
  687. }
  688. static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
  689. {
  690. unsigned int ofs = mv_scr_offset(sc_reg_in);
  691. if (0xffffffffU != ofs) {
  692. return readl(mv_ap_base(ap) + ofs);
  693. } else {
  694. return (u32) ofs;
  695. }
  696. }
  697. static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
  698. {
  699. unsigned int ofs = mv_scr_offset(sc_reg_in);
  700. if (0xffffffffU != ofs) {
  701. writelfl(val, mv_ap_base(ap) + ofs);
  702. }
  703. }
  704. static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
  705. {
  706. u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
  707. /* set up non-NCQ EDMA configuration */
  708. cfg &= ~(1 << 9); /* disable equeue */
  709. if (IS_GEN_I(hpriv)) {
  710. cfg &= ~0x1f; /* clear queue depth */
  711. cfg |= (1 << 8); /* enab config burst size mask */
  712. }
  713. else if (IS_GEN_II(hpriv)) {
  714. cfg &= ~0x1f; /* clear queue depth */
  715. cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
  716. cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
  717. }
  718. else if (IS_GEN_IIE(hpriv)) {
  719. cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
  720. cfg |= (1 << 22); /* enab 4-entry host queue cache */
  721. cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
  722. cfg |= (1 << 18); /* enab early completion */
  723. cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
  724. cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
  725. cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
  726. }
  727. writelfl(cfg, port_mmio + EDMA_CFG_OFS);
  728. }
  729. /**
  730. * mv_port_start - Port specific init/start routine.
  731. * @ap: ATA channel to manipulate
  732. *
  733. * Allocate and point to DMA memory, init port private memory,
  734. * zero indices.
  735. *
  736. * LOCKING:
  737. * Inherited from caller.
  738. */
  739. static int mv_port_start(struct ata_port *ap)
  740. {
  741. struct device *dev = ap->host->dev;
  742. struct mv_host_priv *hpriv = ap->host->private_data;
  743. struct mv_port_priv *pp;
  744. void __iomem *port_mmio = mv_ap_base(ap);
  745. void *mem;
  746. dma_addr_t mem_dma;
  747. int rc;
  748. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  749. if (!pp)
  750. return -ENOMEM;
  751. mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
  752. GFP_KERNEL);
  753. if (!mem)
  754. return -ENOMEM;
  755. memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
  756. rc = ata_pad_alloc(ap, dev);
  757. if (rc)
  758. return rc;
  759. /* First item in chunk of DMA memory:
  760. * 32-slot command request table (CRQB), 32 bytes each in size
  761. */
  762. pp->crqb = mem;
  763. pp->crqb_dma = mem_dma;
  764. mem += MV_CRQB_Q_SZ;
  765. mem_dma += MV_CRQB_Q_SZ;
  766. /* Second item:
  767. * 32-slot command response table (CRPB), 8 bytes each in size
  768. */
  769. pp->crpb = mem;
  770. pp->crpb_dma = mem_dma;
  771. mem += MV_CRPB_Q_SZ;
  772. mem_dma += MV_CRPB_Q_SZ;
  773. /* Third item:
  774. * Table of scatter-gather descriptors (ePRD), 16 bytes each
  775. */
  776. pp->sg_tbl = mem;
  777. pp->sg_tbl_dma = mem_dma;
  778. mv_edma_cfg(hpriv, port_mmio);
  779. writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
  780. writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
  781. port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
  782. if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
  783. writelfl(pp->crqb_dma & 0xffffffff,
  784. port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
  785. else
  786. writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
  787. writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
  788. if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
  789. writelfl(pp->crpb_dma & 0xffffffff,
  790. port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
  791. else
  792. writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
  793. writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
  794. port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
  795. /* Don't turn on EDMA here...do it before DMA commands only. Else
  796. * we'll be unable to send non-data, PIO, etc due to restricted access
  797. * to shadow regs.
  798. */
  799. ap->private_data = pp;
  800. return 0;
  801. }
  802. /**
  803. * mv_port_stop - Port specific cleanup/stop routine.
  804. * @ap: ATA channel to manipulate
  805. *
  806. * Stop DMA, cleanup port memory.
  807. *
  808. * LOCKING:
  809. * This routine uses the host lock to protect the DMA stop.
  810. */
  811. static void mv_port_stop(struct ata_port *ap)
  812. {
  813. unsigned long flags;
  814. spin_lock_irqsave(&ap->host->lock, flags);
  815. mv_stop_dma(ap);
  816. spin_unlock_irqrestore(&ap->host->lock, flags);
  817. }
  818. /**
  819. * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
  820. * @qc: queued command whose SG list to source from
  821. *
  822. * Populate the SG list and mark the last entry.
  823. *
  824. * LOCKING:
  825. * Inherited from caller.
  826. */
  827. static void mv_fill_sg(struct ata_queued_cmd *qc)
  828. {
  829. struct mv_port_priv *pp = qc->ap->private_data;
  830. unsigned int i = 0;
  831. struct scatterlist *sg;
  832. ata_for_each_sg(sg, qc) {
  833. dma_addr_t addr;
  834. u32 sg_len, len, offset;
  835. addr = sg_dma_address(sg);
  836. sg_len = sg_dma_len(sg);
  837. while (sg_len) {
  838. offset = addr & MV_DMA_BOUNDARY;
  839. len = sg_len;
  840. if ((offset + sg_len) > 0x10000)
  841. len = 0x10000 - offset;
  842. pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
  843. pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
  844. pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
  845. sg_len -= len;
  846. addr += len;
  847. if (!sg_len && ata_sg_is_last(sg, qc))
  848. pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
  849. i++;
  850. }
  851. }
  852. }
  853. static inline unsigned mv_inc_q_index(unsigned index)
  854. {
  855. return (index + 1) & MV_MAX_Q_DEPTH_MASK;
  856. }
  857. static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
  858. {
  859. u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
  860. (last ? CRQB_CMD_LAST : 0);
  861. *cmdw = cpu_to_le16(tmp);
  862. }
  863. /**
  864. * mv_qc_prep - Host specific command preparation.
  865. * @qc: queued command to prepare
  866. *
  867. * This routine simply redirects to the general purpose routine
  868. * if command is not DMA. Else, it handles prep of the CRQB
  869. * (command request block), does some sanity checking, and calls
  870. * the SG load routine.
  871. *
  872. * LOCKING:
  873. * Inherited from caller.
  874. */
  875. static void mv_qc_prep(struct ata_queued_cmd *qc)
  876. {
  877. struct ata_port *ap = qc->ap;
  878. struct mv_port_priv *pp = ap->private_data;
  879. __le16 *cw;
  880. struct ata_taskfile *tf;
  881. u16 flags = 0;
  882. unsigned in_index;
  883. if (ATA_PROT_DMA != qc->tf.protocol)
  884. return;
  885. /* Fill in command request block
  886. */
  887. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  888. flags |= CRQB_FLAG_READ;
  889. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  890. flags |= qc->tag << CRQB_TAG_SHIFT;
  891. /* get current queue index from hardware */
  892. in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
  893. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  894. pp->crqb[in_index].sg_addr =
  895. cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
  896. pp->crqb[in_index].sg_addr_hi =
  897. cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
  898. pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
  899. cw = &pp->crqb[in_index].ata_cmd[0];
  900. tf = &qc->tf;
  901. /* Sadly, the CRQB cannot accomodate all registers--there are
  902. * only 11 bytes...so we must pick and choose required
  903. * registers based on the command. So, we drop feature and
  904. * hob_feature for [RW] DMA commands, but they are needed for
  905. * NCQ. NCQ will drop hob_nsect.
  906. */
  907. switch (tf->command) {
  908. case ATA_CMD_READ:
  909. case ATA_CMD_READ_EXT:
  910. case ATA_CMD_WRITE:
  911. case ATA_CMD_WRITE_EXT:
  912. case ATA_CMD_WRITE_FUA_EXT:
  913. mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
  914. break;
  915. #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
  916. case ATA_CMD_FPDMA_READ:
  917. case ATA_CMD_FPDMA_WRITE:
  918. mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
  919. mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
  920. break;
  921. #endif /* FIXME: remove this line when NCQ added */
  922. default:
  923. /* The only other commands EDMA supports in non-queued and
  924. * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
  925. * of which are defined/used by Linux. If we get here, this
  926. * driver needs work.
  927. *
  928. * FIXME: modify libata to give qc_prep a return value and
  929. * return error here.
  930. */
  931. BUG_ON(tf->command);
  932. break;
  933. }
  934. mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
  935. mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
  936. mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
  937. mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
  938. mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
  939. mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
  940. mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
  941. mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
  942. mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
  943. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  944. return;
  945. mv_fill_sg(qc);
  946. }
  947. /**
  948. * mv_qc_prep_iie - Host specific command preparation.
  949. * @qc: queued command to prepare
  950. *
  951. * This routine simply redirects to the general purpose routine
  952. * if command is not DMA. Else, it handles prep of the CRQB
  953. * (command request block), does some sanity checking, and calls
  954. * the SG load routine.
  955. *
  956. * LOCKING:
  957. * Inherited from caller.
  958. */
  959. static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
  960. {
  961. struct ata_port *ap = qc->ap;
  962. struct mv_port_priv *pp = ap->private_data;
  963. struct mv_crqb_iie *crqb;
  964. struct ata_taskfile *tf;
  965. unsigned in_index;
  966. u32 flags = 0;
  967. if (ATA_PROT_DMA != qc->tf.protocol)
  968. return;
  969. /* Fill in Gen IIE command request block
  970. */
  971. if (!(qc->tf.flags & ATA_TFLAG_WRITE))
  972. flags |= CRQB_FLAG_READ;
  973. WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
  974. flags |= qc->tag << CRQB_TAG_SHIFT;
  975. /* get current queue index from hardware */
  976. in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
  977. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  978. crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
  979. crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
  980. crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
  981. crqb->flags = cpu_to_le32(flags);
  982. tf = &qc->tf;
  983. crqb->ata_cmd[0] = cpu_to_le32(
  984. (tf->command << 16) |
  985. (tf->feature << 24)
  986. );
  987. crqb->ata_cmd[1] = cpu_to_le32(
  988. (tf->lbal << 0) |
  989. (tf->lbam << 8) |
  990. (tf->lbah << 16) |
  991. (tf->device << 24)
  992. );
  993. crqb->ata_cmd[2] = cpu_to_le32(
  994. (tf->hob_lbal << 0) |
  995. (tf->hob_lbam << 8) |
  996. (tf->hob_lbah << 16) |
  997. (tf->hob_feature << 24)
  998. );
  999. crqb->ata_cmd[3] = cpu_to_le32(
  1000. (tf->nsect << 0) |
  1001. (tf->hob_nsect << 8)
  1002. );
  1003. if (!(qc->flags & ATA_QCFLAG_DMAMAP))
  1004. return;
  1005. mv_fill_sg(qc);
  1006. }
  1007. /**
  1008. * mv_qc_issue - Initiate a command to the host
  1009. * @qc: queued command to start
  1010. *
  1011. * This routine simply redirects to the general purpose routine
  1012. * if command is not DMA. Else, it sanity checks our local
  1013. * caches of the request producer/consumer indices then enables
  1014. * DMA and bumps the request producer index.
  1015. *
  1016. * LOCKING:
  1017. * Inherited from caller.
  1018. */
  1019. static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
  1020. {
  1021. void __iomem *port_mmio = mv_ap_base(qc->ap);
  1022. struct mv_port_priv *pp = qc->ap->private_data;
  1023. unsigned in_index;
  1024. u32 in_ptr;
  1025. if (ATA_PROT_DMA != qc->tf.protocol) {
  1026. /* We're about to send a non-EDMA capable command to the
  1027. * port. Turn off EDMA so there won't be problems accessing
  1028. * shadow block, etc registers.
  1029. */
  1030. mv_stop_dma(qc->ap);
  1031. return ata_qc_issue_prot(qc);
  1032. }
  1033. in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
  1034. in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  1035. /* until we do queuing, the queue should be empty at this point */
  1036. WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
  1037. >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
  1038. in_index = mv_inc_q_index(in_index); /* now incr producer index */
  1039. mv_start_dma(port_mmio, pp);
  1040. /* and write the request in pointer to kick the EDMA to life */
  1041. in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
  1042. in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
  1043. writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
  1044. return 0;
  1045. }
  1046. /**
  1047. * mv_get_crpb_status - get status from most recently completed cmd
  1048. * @ap: ATA channel to manipulate
  1049. *
  1050. * This routine is for use when the port is in DMA mode, when it
  1051. * will be using the CRPB (command response block) method of
  1052. * returning command completion information. We check indices
  1053. * are good, grab status, and bump the response consumer index to
  1054. * prove that we're up to date.
  1055. *
  1056. * LOCKING:
  1057. * Inherited from caller.
  1058. */
  1059. static u8 mv_get_crpb_status(struct ata_port *ap)
  1060. {
  1061. void __iomem *port_mmio = mv_ap_base(ap);
  1062. struct mv_port_priv *pp = ap->private_data;
  1063. unsigned out_index;
  1064. u32 out_ptr;
  1065. u8 ata_status;
  1066. out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
  1067. out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
  1068. ata_status = le16_to_cpu(pp->crpb[out_index].flags)
  1069. >> CRPB_FLAG_STATUS_SHIFT;
  1070. /* increment our consumer index... */
  1071. out_index = mv_inc_q_index(out_index);
  1072. /* and, until we do NCQ, there should only be 1 CRPB waiting */
  1073. WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
  1074. >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
  1075. /* write out our inc'd consumer index so EDMA knows we're caught up */
  1076. out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
  1077. out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
  1078. writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
  1079. /* Return ATA status register for completed CRPB */
  1080. return ata_status;
  1081. }
  1082. /**
  1083. * mv_err_intr - Handle error interrupts on the port
  1084. * @ap: ATA channel to manipulate
  1085. * @reset_allowed: bool: 0 == don't trigger from reset here
  1086. *
  1087. * In most cases, just clear the interrupt and move on. However,
  1088. * some cases require an eDMA reset, which is done right before
  1089. * the COMRESET in mv_phy_reset(). The SERR case requires a
  1090. * clear of pending errors in the SATA SERROR register. Finally,
  1091. * if the port disabled DMA, update our cached copy to match.
  1092. *
  1093. * LOCKING:
  1094. * Inherited from caller.
  1095. */
  1096. static void mv_err_intr(struct ata_port *ap, int reset_allowed)
  1097. {
  1098. void __iomem *port_mmio = mv_ap_base(ap);
  1099. u32 edma_err_cause, serr = 0;
  1100. edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1101. if (EDMA_ERR_SERR & edma_err_cause) {
  1102. sata_scr_read(ap, SCR_ERROR, &serr);
  1103. sata_scr_write_flush(ap, SCR_ERROR, serr);
  1104. }
  1105. if (EDMA_ERR_SELF_DIS & edma_err_cause) {
  1106. struct mv_port_priv *pp = ap->private_data;
  1107. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1108. }
  1109. DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
  1110. "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
  1111. /* Clear EDMA now that SERR cleanup done */
  1112. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1113. /* check for fatal here and recover if needed */
  1114. if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
  1115. mv_stop_and_reset(ap);
  1116. }
  1117. /**
  1118. * mv_host_intr - Handle all interrupts on the given host controller
  1119. * @host: host specific structure
  1120. * @relevant: port error bits relevant to this host controller
  1121. * @hc: which host controller we're to look at
  1122. *
  1123. * Read then write clear the HC interrupt status then walk each
  1124. * port connected to the HC and see if it needs servicing. Port
  1125. * success ints are reported in the HC interrupt status reg, the
  1126. * port error ints are reported in the higher level main
  1127. * interrupt status register and thus are passed in via the
  1128. * 'relevant' argument.
  1129. *
  1130. * LOCKING:
  1131. * Inherited from caller.
  1132. */
  1133. static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
  1134. {
  1135. void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
  1136. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  1137. struct ata_queued_cmd *qc;
  1138. u32 hc_irq_cause;
  1139. int shift, port, port0, hard_port, handled;
  1140. unsigned int err_mask;
  1141. if (hc == 0) {
  1142. port0 = 0;
  1143. } else {
  1144. port0 = MV_PORTS_PER_HC;
  1145. }
  1146. /* we'll need the HC success int register in most cases */
  1147. hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
  1148. if (hc_irq_cause) {
  1149. writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
  1150. }
  1151. VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
  1152. hc,relevant,hc_irq_cause);
  1153. for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
  1154. u8 ata_status = 0;
  1155. struct ata_port *ap = host->ports[port];
  1156. struct mv_port_priv *pp = ap->private_data;
  1157. hard_port = mv_hardport_from_port(port); /* range 0..3 */
  1158. handled = 0; /* ensure ata_status is set if handled++ */
  1159. /* Note that DEV_IRQ might happen spuriously during EDMA,
  1160. * and should be ignored in such cases.
  1161. * The cause of this is still under investigation.
  1162. */
  1163. if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
  1164. /* EDMA: check for response queue interrupt */
  1165. if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
  1166. ata_status = mv_get_crpb_status(ap);
  1167. handled = 1;
  1168. }
  1169. } else {
  1170. /* PIO: check for device (drive) interrupt */
  1171. if ((DEV_IRQ << hard_port) & hc_irq_cause) {
  1172. ata_status = readb(ap->ioaddr.status_addr);
  1173. handled = 1;
  1174. /* ignore spurious intr if drive still BUSY */
  1175. if (ata_status & ATA_BUSY) {
  1176. ata_status = 0;
  1177. handled = 0;
  1178. }
  1179. }
  1180. }
  1181. if (ap && (ap->flags & ATA_FLAG_DISABLED))
  1182. continue;
  1183. err_mask = ac_err_mask(ata_status);
  1184. shift = port << 1; /* (port * 2) */
  1185. if (port >= MV_PORTS_PER_HC) {
  1186. shift++; /* skip bit 8 in the HC Main IRQ reg */
  1187. }
  1188. if ((PORT0_ERR << shift) & relevant) {
  1189. mv_err_intr(ap, 1);
  1190. err_mask |= AC_ERR_OTHER;
  1191. handled = 1;
  1192. }
  1193. if (handled) {
  1194. qc = ata_qc_from_tag(ap, ap->active_tag);
  1195. if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
  1196. VPRINTK("port %u IRQ found for qc, "
  1197. "ata_status 0x%x\n", port,ata_status);
  1198. /* mark qc status appropriately */
  1199. if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
  1200. qc->err_mask |= err_mask;
  1201. ata_qc_complete(qc);
  1202. }
  1203. }
  1204. }
  1205. }
  1206. VPRINTK("EXIT\n");
  1207. }
  1208. /**
  1209. * mv_interrupt -
  1210. * @irq: unused
  1211. * @dev_instance: private data; in this case the host structure
  1212. * @regs: unused
  1213. *
  1214. * Read the read only register to determine if any host
  1215. * controllers have pending interrupts. If so, call lower level
  1216. * routine to handle. Also check for PCI errors which are only
  1217. * reported here.
  1218. *
  1219. * LOCKING:
  1220. * This routine holds the host lock while processing pending
  1221. * interrupts.
  1222. */
  1223. static irqreturn_t mv_interrupt(int irq, void *dev_instance)
  1224. {
  1225. struct ata_host *host = dev_instance;
  1226. unsigned int hc, handled = 0, n_hcs;
  1227. void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
  1228. struct mv_host_priv *hpriv;
  1229. u32 irq_stat;
  1230. irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
  1231. /* check the cases where we either have nothing pending or have read
  1232. * a bogus register value which can indicate HW removal or PCI fault
  1233. */
  1234. if (!irq_stat || (0xffffffffU == irq_stat)) {
  1235. return IRQ_NONE;
  1236. }
  1237. n_hcs = mv_get_hc_count(host->ports[0]->flags);
  1238. spin_lock(&host->lock);
  1239. for (hc = 0; hc < n_hcs; hc++) {
  1240. u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
  1241. if (relevant) {
  1242. mv_host_intr(host, relevant, hc);
  1243. handled++;
  1244. }
  1245. }
  1246. hpriv = host->private_data;
  1247. if (IS_60XX(hpriv)) {
  1248. /* deal with the interrupt coalescing bits */
  1249. if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
  1250. writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
  1251. writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
  1252. writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
  1253. }
  1254. }
  1255. if (PCI_ERR & irq_stat) {
  1256. printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
  1257. readl(mmio + PCI_IRQ_CAUSE_OFS));
  1258. DPRINTK("All regs @ PCI error\n");
  1259. mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
  1260. writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
  1261. handled++;
  1262. }
  1263. spin_unlock(&host->lock);
  1264. return IRQ_RETVAL(handled);
  1265. }
  1266. static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
  1267. {
  1268. void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
  1269. unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
  1270. return hc_mmio + ofs;
  1271. }
  1272. static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
  1273. {
  1274. unsigned int ofs;
  1275. switch (sc_reg_in) {
  1276. case SCR_STATUS:
  1277. case SCR_ERROR:
  1278. case SCR_CONTROL:
  1279. ofs = sc_reg_in * sizeof(u32);
  1280. break;
  1281. default:
  1282. ofs = 0xffffffffU;
  1283. break;
  1284. }
  1285. return ofs;
  1286. }
  1287. static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
  1288. {
  1289. void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
  1290. void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
  1291. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  1292. if (ofs != 0xffffffffU)
  1293. return readl(addr + ofs);
  1294. else
  1295. return (u32) ofs;
  1296. }
  1297. static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
  1298. {
  1299. void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
  1300. void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
  1301. unsigned int ofs = mv5_scr_offset(sc_reg_in);
  1302. if (ofs != 0xffffffffU)
  1303. writelfl(val, addr + ofs);
  1304. }
  1305. static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
  1306. {
  1307. u8 rev_id;
  1308. int early_5080;
  1309. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
  1310. early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
  1311. if (!early_5080) {
  1312. u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1313. tmp |= (1 << 0);
  1314. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1315. }
  1316. mv_reset_pci_bus(pdev, mmio);
  1317. }
  1318. static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  1319. {
  1320. writel(0x0fcfffff, mmio + MV_FLASH_CTL);
  1321. }
  1322. static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
  1323. void __iomem *mmio)
  1324. {
  1325. void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
  1326. u32 tmp;
  1327. tmp = readl(phy_mmio + MV5_PHY_MODE);
  1328. hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
  1329. hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
  1330. }
  1331. static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  1332. {
  1333. u32 tmp;
  1334. writel(0, mmio + MV_GPIO_PORT_CTL);
  1335. /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
  1336. tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1337. tmp |= ~(1 << 0);
  1338. writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
  1339. }
  1340. static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  1341. unsigned int port)
  1342. {
  1343. void __iomem *phy_mmio = mv5_phy_base(mmio, port);
  1344. const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
  1345. u32 tmp;
  1346. int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
  1347. if (fix_apm_sq) {
  1348. tmp = readl(phy_mmio + MV5_LT_MODE);
  1349. tmp |= (1 << 19);
  1350. writel(tmp, phy_mmio + MV5_LT_MODE);
  1351. tmp = readl(phy_mmio + MV5_PHY_CTL);
  1352. tmp &= ~0x3;
  1353. tmp |= 0x1;
  1354. writel(tmp, phy_mmio + MV5_PHY_CTL);
  1355. }
  1356. tmp = readl(phy_mmio + MV5_PHY_MODE);
  1357. tmp &= ~mask;
  1358. tmp |= hpriv->signal[port].pre;
  1359. tmp |= hpriv->signal[port].amps;
  1360. writel(tmp, phy_mmio + MV5_PHY_MODE);
  1361. }
  1362. #undef ZERO
  1363. #define ZERO(reg) writel(0, port_mmio + (reg))
  1364. static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
  1365. unsigned int port)
  1366. {
  1367. void __iomem *port_mmio = mv_port_base(mmio, port);
  1368. writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
  1369. mv_channel_reset(hpriv, mmio, port);
  1370. ZERO(0x028); /* command */
  1371. writel(0x11f, port_mmio + EDMA_CFG_OFS);
  1372. ZERO(0x004); /* timer */
  1373. ZERO(0x008); /* irq err cause */
  1374. ZERO(0x00c); /* irq err mask */
  1375. ZERO(0x010); /* rq bah */
  1376. ZERO(0x014); /* rq inp */
  1377. ZERO(0x018); /* rq outp */
  1378. ZERO(0x01c); /* respq bah */
  1379. ZERO(0x024); /* respq outp */
  1380. ZERO(0x020); /* respq inp */
  1381. ZERO(0x02c); /* test control */
  1382. writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
  1383. }
  1384. #undef ZERO
  1385. #define ZERO(reg) writel(0, hc_mmio + (reg))
  1386. static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1387. unsigned int hc)
  1388. {
  1389. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  1390. u32 tmp;
  1391. ZERO(0x00c);
  1392. ZERO(0x010);
  1393. ZERO(0x014);
  1394. ZERO(0x018);
  1395. tmp = readl(hc_mmio + 0x20);
  1396. tmp &= 0x1c1c1c1c;
  1397. tmp |= 0x03030303;
  1398. writel(tmp, hc_mmio + 0x20);
  1399. }
  1400. #undef ZERO
  1401. static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1402. unsigned int n_hc)
  1403. {
  1404. unsigned int hc, port;
  1405. for (hc = 0; hc < n_hc; hc++) {
  1406. for (port = 0; port < MV_PORTS_PER_HC; port++)
  1407. mv5_reset_hc_port(hpriv, mmio,
  1408. (hc * MV_PORTS_PER_HC) + port);
  1409. mv5_reset_one_hc(hpriv, mmio, hc);
  1410. }
  1411. return 0;
  1412. }
  1413. #undef ZERO
  1414. #define ZERO(reg) writel(0, mmio + (reg))
  1415. static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
  1416. {
  1417. u32 tmp;
  1418. tmp = readl(mmio + MV_PCI_MODE);
  1419. tmp &= 0xff00ffff;
  1420. writel(tmp, mmio + MV_PCI_MODE);
  1421. ZERO(MV_PCI_DISC_TIMER);
  1422. ZERO(MV_PCI_MSI_TRIGGER);
  1423. writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
  1424. ZERO(HC_MAIN_IRQ_MASK_OFS);
  1425. ZERO(MV_PCI_SERR_MASK);
  1426. ZERO(PCI_IRQ_CAUSE_OFS);
  1427. ZERO(PCI_IRQ_MASK_OFS);
  1428. ZERO(MV_PCI_ERR_LOW_ADDRESS);
  1429. ZERO(MV_PCI_ERR_HIGH_ADDRESS);
  1430. ZERO(MV_PCI_ERR_ATTRIBUTE);
  1431. ZERO(MV_PCI_ERR_COMMAND);
  1432. }
  1433. #undef ZERO
  1434. static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
  1435. {
  1436. u32 tmp;
  1437. mv5_reset_flash(hpriv, mmio);
  1438. tmp = readl(mmio + MV_GPIO_PORT_CTL);
  1439. tmp &= 0x3;
  1440. tmp |= (1 << 5) | (1 << 6);
  1441. writel(tmp, mmio + MV_GPIO_PORT_CTL);
  1442. }
  1443. /**
  1444. * mv6_reset_hc - Perform the 6xxx global soft reset
  1445. * @mmio: base address of the HBA
  1446. *
  1447. * This routine only applies to 6xxx parts.
  1448. *
  1449. * LOCKING:
  1450. * Inherited from caller.
  1451. */
  1452. static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
  1453. unsigned int n_hc)
  1454. {
  1455. void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
  1456. int i, rc = 0;
  1457. u32 t;
  1458. /* Following procedure defined in PCI "main command and status
  1459. * register" table.
  1460. */
  1461. t = readl(reg);
  1462. writel(t | STOP_PCI_MASTER, reg);
  1463. for (i = 0; i < 1000; i++) {
  1464. udelay(1);
  1465. t = readl(reg);
  1466. if (PCI_MASTER_EMPTY & t) {
  1467. break;
  1468. }
  1469. }
  1470. if (!(PCI_MASTER_EMPTY & t)) {
  1471. printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
  1472. rc = 1;
  1473. goto done;
  1474. }
  1475. /* set reset */
  1476. i = 5;
  1477. do {
  1478. writel(t | GLOB_SFT_RST, reg);
  1479. t = readl(reg);
  1480. udelay(1);
  1481. } while (!(GLOB_SFT_RST & t) && (i-- > 0));
  1482. if (!(GLOB_SFT_RST & t)) {
  1483. printk(KERN_ERR DRV_NAME ": can't set global reset\n");
  1484. rc = 1;
  1485. goto done;
  1486. }
  1487. /* clear reset and *reenable the PCI master* (not mentioned in spec) */
  1488. i = 5;
  1489. do {
  1490. writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
  1491. t = readl(reg);
  1492. udelay(1);
  1493. } while ((GLOB_SFT_RST & t) && (i-- > 0));
  1494. if (GLOB_SFT_RST & t) {
  1495. printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
  1496. rc = 1;
  1497. }
  1498. done:
  1499. return rc;
  1500. }
  1501. static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
  1502. void __iomem *mmio)
  1503. {
  1504. void __iomem *port_mmio;
  1505. u32 tmp;
  1506. tmp = readl(mmio + MV_RESET_CFG);
  1507. if ((tmp & (1 << 0)) == 0) {
  1508. hpriv->signal[idx].amps = 0x7 << 8;
  1509. hpriv->signal[idx].pre = 0x1 << 5;
  1510. return;
  1511. }
  1512. port_mmio = mv_port_base(mmio, idx);
  1513. tmp = readl(port_mmio + PHY_MODE2);
  1514. hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
  1515. hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
  1516. }
  1517. static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
  1518. {
  1519. writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
  1520. }
  1521. static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
  1522. unsigned int port)
  1523. {
  1524. void __iomem *port_mmio = mv_port_base(mmio, port);
  1525. u32 hp_flags = hpriv->hp_flags;
  1526. int fix_phy_mode2 =
  1527. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  1528. int fix_phy_mode4 =
  1529. hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
  1530. u32 m2, tmp;
  1531. if (fix_phy_mode2) {
  1532. m2 = readl(port_mmio + PHY_MODE2);
  1533. m2 &= ~(1 << 16);
  1534. m2 |= (1 << 31);
  1535. writel(m2, port_mmio + PHY_MODE2);
  1536. udelay(200);
  1537. m2 = readl(port_mmio + PHY_MODE2);
  1538. m2 &= ~((1 << 16) | (1 << 31));
  1539. writel(m2, port_mmio + PHY_MODE2);
  1540. udelay(200);
  1541. }
  1542. /* who knows what this magic does */
  1543. tmp = readl(port_mmio + PHY_MODE3);
  1544. tmp &= ~0x7F800000;
  1545. tmp |= 0x2A800000;
  1546. writel(tmp, port_mmio + PHY_MODE3);
  1547. if (fix_phy_mode4) {
  1548. u32 m4;
  1549. m4 = readl(port_mmio + PHY_MODE4);
  1550. if (hp_flags & MV_HP_ERRATA_60X1B2)
  1551. tmp = readl(port_mmio + 0x310);
  1552. m4 = (m4 & ~(1 << 1)) | (1 << 0);
  1553. writel(m4, port_mmio + PHY_MODE4);
  1554. if (hp_flags & MV_HP_ERRATA_60X1B2)
  1555. writel(tmp, port_mmio + 0x310);
  1556. }
  1557. /* Revert values of pre-emphasis and signal amps to the saved ones */
  1558. m2 = readl(port_mmio + PHY_MODE2);
  1559. m2 &= ~MV_M2_PREAMP_MASK;
  1560. m2 |= hpriv->signal[port].amps;
  1561. m2 |= hpriv->signal[port].pre;
  1562. m2 &= ~(1 << 16);
  1563. /* according to mvSata 3.6.1, some IIE values are fixed */
  1564. if (IS_GEN_IIE(hpriv)) {
  1565. m2 &= ~0xC30FF01F;
  1566. m2 |= 0x0000900F;
  1567. }
  1568. writel(m2, port_mmio + PHY_MODE2);
  1569. }
  1570. static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
  1571. unsigned int port_no)
  1572. {
  1573. void __iomem *port_mmio = mv_port_base(mmio, port_no);
  1574. writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
  1575. if (IS_60XX(hpriv)) {
  1576. u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
  1577. ifctl |= (1 << 7); /* enable gen2i speed */
  1578. ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
  1579. writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
  1580. }
  1581. udelay(25); /* allow reset propagation */
  1582. /* Spec never mentions clearing the bit. Marvell's driver does
  1583. * clear the bit, however.
  1584. */
  1585. writelfl(0, port_mmio + EDMA_CMD_OFS);
  1586. hpriv->ops->phy_errata(hpriv, mmio, port_no);
  1587. if (IS_50XX(hpriv))
  1588. mdelay(1);
  1589. }
  1590. static void mv_stop_and_reset(struct ata_port *ap)
  1591. {
  1592. struct mv_host_priv *hpriv = ap->host->private_data;
  1593. void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
  1594. mv_stop_dma(ap);
  1595. mv_channel_reset(hpriv, mmio, ap->port_no);
  1596. __mv_phy_reset(ap, 0);
  1597. }
  1598. static inline void __msleep(unsigned int msec, int can_sleep)
  1599. {
  1600. if (can_sleep)
  1601. msleep(msec);
  1602. else
  1603. mdelay(msec);
  1604. }
  1605. /**
  1606. * __mv_phy_reset - Perform eDMA reset followed by COMRESET
  1607. * @ap: ATA channel to manipulate
  1608. *
  1609. * Part of this is taken from __sata_phy_reset and modified to
  1610. * not sleep since this routine gets called from interrupt level.
  1611. *
  1612. * LOCKING:
  1613. * Inherited from caller. This is coded to safe to call at
  1614. * interrupt level, i.e. it does not sleep.
  1615. */
  1616. static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
  1617. {
  1618. struct mv_port_priv *pp = ap->private_data;
  1619. struct mv_host_priv *hpriv = ap->host->private_data;
  1620. void __iomem *port_mmio = mv_ap_base(ap);
  1621. struct ata_taskfile tf;
  1622. struct ata_device *dev = &ap->device[0];
  1623. unsigned long timeout;
  1624. int retry = 5;
  1625. u32 sstatus;
  1626. VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
  1627. DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
  1628. "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
  1629. mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
  1630. /* Issue COMRESET via SControl */
  1631. comreset_retry:
  1632. sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
  1633. __msleep(1, can_sleep);
  1634. sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
  1635. __msleep(20, can_sleep);
  1636. timeout = jiffies + msecs_to_jiffies(200);
  1637. do {
  1638. sata_scr_read(ap, SCR_STATUS, &sstatus);
  1639. if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
  1640. break;
  1641. __msleep(1, can_sleep);
  1642. } while (time_before(jiffies, timeout));
  1643. /* work around errata */
  1644. if (IS_60XX(hpriv) &&
  1645. (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
  1646. (retry-- > 0))
  1647. goto comreset_retry;
  1648. DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
  1649. "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
  1650. mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
  1651. if (ata_port_online(ap)) {
  1652. ata_port_probe(ap);
  1653. } else {
  1654. sata_scr_read(ap, SCR_STATUS, &sstatus);
  1655. ata_port_printk(ap, KERN_INFO,
  1656. "no device found (phy stat %08x)\n", sstatus);
  1657. ata_port_disable(ap);
  1658. return;
  1659. }
  1660. ap->cbl = ATA_CBL_SATA;
  1661. /* even after SStatus reflects that device is ready,
  1662. * it seems to take a while for link to be fully
  1663. * established (and thus Status no longer 0x80/0x7F),
  1664. * so we poll a bit for that, here.
  1665. */
  1666. retry = 20;
  1667. while (1) {
  1668. u8 drv_stat = ata_check_status(ap);
  1669. if ((drv_stat != 0x80) && (drv_stat != 0x7f))
  1670. break;
  1671. __msleep(500, can_sleep);
  1672. if (retry-- <= 0)
  1673. break;
  1674. }
  1675. tf.lbah = readb(ap->ioaddr.lbah_addr);
  1676. tf.lbam = readb(ap->ioaddr.lbam_addr);
  1677. tf.lbal = readb(ap->ioaddr.lbal_addr);
  1678. tf.nsect = readb(ap->ioaddr.nsect_addr);
  1679. dev->class = ata_dev_classify(&tf);
  1680. if (!ata_dev_enabled(dev)) {
  1681. VPRINTK("Port disabled post-sig: No device present.\n");
  1682. ata_port_disable(ap);
  1683. }
  1684. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1685. pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
  1686. VPRINTK("EXIT\n");
  1687. }
  1688. static void mv_phy_reset(struct ata_port *ap)
  1689. {
  1690. __mv_phy_reset(ap, 1);
  1691. }
  1692. /**
  1693. * mv_eng_timeout - Routine called by libata when SCSI times out I/O
  1694. * @ap: ATA channel to manipulate
  1695. *
  1696. * Intent is to clear all pending error conditions, reset the
  1697. * chip/bus, fail the command, and move on.
  1698. *
  1699. * LOCKING:
  1700. * This routine holds the host lock while failing the command.
  1701. */
  1702. static void mv_eng_timeout(struct ata_port *ap)
  1703. {
  1704. void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
  1705. struct ata_queued_cmd *qc;
  1706. unsigned long flags;
  1707. ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
  1708. DPRINTK("All regs @ start of eng_timeout\n");
  1709. mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
  1710. qc = ata_qc_from_tag(ap, ap->active_tag);
  1711. printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
  1712. mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
  1713. spin_lock_irqsave(&ap->host->lock, flags);
  1714. mv_err_intr(ap, 0);
  1715. mv_stop_and_reset(ap);
  1716. spin_unlock_irqrestore(&ap->host->lock, flags);
  1717. WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
  1718. if (qc->flags & ATA_QCFLAG_ACTIVE) {
  1719. qc->err_mask |= AC_ERR_TIMEOUT;
  1720. ata_eh_qc_complete(qc);
  1721. }
  1722. }
  1723. /**
  1724. * mv_port_init - Perform some early initialization on a single port.
  1725. * @port: libata data structure storing shadow register addresses
  1726. * @port_mmio: base address of the port
  1727. *
  1728. * Initialize shadow register mmio addresses, clear outstanding
  1729. * interrupts on the port, and unmask interrupts for the future
  1730. * start of the port.
  1731. *
  1732. * LOCKING:
  1733. * Inherited from caller.
  1734. */
  1735. static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
  1736. {
  1737. void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
  1738. unsigned serr_ofs;
  1739. /* PIO related setup
  1740. */
  1741. port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
  1742. port->error_addr =
  1743. port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
  1744. port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
  1745. port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
  1746. port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
  1747. port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
  1748. port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
  1749. port->status_addr =
  1750. port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
  1751. /* special case: control/altstatus doesn't have ATA_REG_ address */
  1752. port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
  1753. /* unused: */
  1754. port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
  1755. /* Clear any currently outstanding port interrupt conditions */
  1756. serr_ofs = mv_scr_offset(SCR_ERROR);
  1757. writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
  1758. writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
  1759. /* unmask all EDMA error interrupts */
  1760. writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
  1761. VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
  1762. readl(port_mmio + EDMA_CFG_OFS),
  1763. readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
  1764. readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
  1765. }
  1766. static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
  1767. unsigned int board_idx)
  1768. {
  1769. u8 rev_id;
  1770. u32 hp_flags = hpriv->hp_flags;
  1771. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
  1772. switch(board_idx) {
  1773. case chip_5080:
  1774. hpriv->ops = &mv5xxx_ops;
  1775. hp_flags |= MV_HP_50XX;
  1776. switch (rev_id) {
  1777. case 0x1:
  1778. hp_flags |= MV_HP_ERRATA_50XXB0;
  1779. break;
  1780. case 0x3:
  1781. hp_flags |= MV_HP_ERRATA_50XXB2;
  1782. break;
  1783. default:
  1784. dev_printk(KERN_WARNING, &pdev->dev,
  1785. "Applying 50XXB2 workarounds to unknown rev\n");
  1786. hp_flags |= MV_HP_ERRATA_50XXB2;
  1787. break;
  1788. }
  1789. break;
  1790. case chip_504x:
  1791. case chip_508x:
  1792. hpriv->ops = &mv5xxx_ops;
  1793. hp_flags |= MV_HP_50XX;
  1794. switch (rev_id) {
  1795. case 0x0:
  1796. hp_flags |= MV_HP_ERRATA_50XXB0;
  1797. break;
  1798. case 0x3:
  1799. hp_flags |= MV_HP_ERRATA_50XXB2;
  1800. break;
  1801. default:
  1802. dev_printk(KERN_WARNING, &pdev->dev,
  1803. "Applying B2 workarounds to unknown rev\n");
  1804. hp_flags |= MV_HP_ERRATA_50XXB2;
  1805. break;
  1806. }
  1807. break;
  1808. case chip_604x:
  1809. case chip_608x:
  1810. hpriv->ops = &mv6xxx_ops;
  1811. switch (rev_id) {
  1812. case 0x7:
  1813. hp_flags |= MV_HP_ERRATA_60X1B2;
  1814. break;
  1815. case 0x9:
  1816. hp_flags |= MV_HP_ERRATA_60X1C0;
  1817. break;
  1818. default:
  1819. dev_printk(KERN_WARNING, &pdev->dev,
  1820. "Applying B2 workarounds to unknown rev\n");
  1821. hp_flags |= MV_HP_ERRATA_60X1B2;
  1822. break;
  1823. }
  1824. break;
  1825. case chip_7042:
  1826. case chip_6042:
  1827. hpriv->ops = &mv6xxx_ops;
  1828. hp_flags |= MV_HP_GEN_IIE;
  1829. switch (rev_id) {
  1830. case 0x0:
  1831. hp_flags |= MV_HP_ERRATA_XX42A0;
  1832. break;
  1833. case 0x1:
  1834. hp_flags |= MV_HP_ERRATA_60X1C0;
  1835. break;
  1836. default:
  1837. dev_printk(KERN_WARNING, &pdev->dev,
  1838. "Applying 60X1C0 workarounds to unknown rev\n");
  1839. hp_flags |= MV_HP_ERRATA_60X1C0;
  1840. break;
  1841. }
  1842. break;
  1843. default:
  1844. printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
  1845. return 1;
  1846. }
  1847. hpriv->hp_flags = hp_flags;
  1848. return 0;
  1849. }
  1850. /**
  1851. * mv_init_host - Perform some early initialization of the host.
  1852. * @pdev: host PCI device
  1853. * @probe_ent: early data struct representing the host
  1854. *
  1855. * If possible, do an early global reset of the host. Then do
  1856. * our port init and clear/unmask all/relevant host interrupts.
  1857. *
  1858. * LOCKING:
  1859. * Inherited from caller.
  1860. */
  1861. static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
  1862. unsigned int board_idx)
  1863. {
  1864. int rc = 0, n_hc, port, hc;
  1865. void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
  1866. struct mv_host_priv *hpriv = probe_ent->private_data;
  1867. /* global interrupt mask */
  1868. writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
  1869. rc = mv_chip_id(pdev, hpriv, board_idx);
  1870. if (rc)
  1871. goto done;
  1872. n_hc = mv_get_hc_count(probe_ent->port_flags);
  1873. probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
  1874. for (port = 0; port < probe_ent->n_ports; port++)
  1875. hpriv->ops->read_preamp(hpriv, port, mmio);
  1876. rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
  1877. if (rc)
  1878. goto done;
  1879. hpriv->ops->reset_flash(hpriv, mmio);
  1880. hpriv->ops->reset_bus(pdev, mmio);
  1881. hpriv->ops->enable_leds(hpriv, mmio);
  1882. for (port = 0; port < probe_ent->n_ports; port++) {
  1883. if (IS_60XX(hpriv)) {
  1884. void __iomem *port_mmio = mv_port_base(mmio, port);
  1885. u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
  1886. ifctl |= (1 << 7); /* enable gen2i speed */
  1887. ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
  1888. writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
  1889. }
  1890. hpriv->ops->phy_errata(hpriv, mmio, port);
  1891. }
  1892. for (port = 0; port < probe_ent->n_ports; port++) {
  1893. void __iomem *port_mmio = mv_port_base(mmio, port);
  1894. mv_port_init(&probe_ent->port[port], port_mmio);
  1895. }
  1896. for (hc = 0; hc < n_hc; hc++) {
  1897. void __iomem *hc_mmio = mv_hc_base(mmio, hc);
  1898. VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
  1899. "(before clear)=0x%08x\n", hc,
  1900. readl(hc_mmio + HC_CFG_OFS),
  1901. readl(hc_mmio + HC_IRQ_CAUSE_OFS));
  1902. /* Clear any currently outstanding hc interrupt conditions */
  1903. writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
  1904. }
  1905. /* Clear any currently outstanding host interrupt conditions */
  1906. writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
  1907. /* and unmask interrupt generation for host regs */
  1908. writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
  1909. if (IS_50XX(hpriv))
  1910. writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
  1911. else
  1912. writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
  1913. VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
  1914. "PCI int cause/mask=0x%08x/0x%08x\n",
  1915. readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
  1916. readl(mmio + HC_MAIN_IRQ_MASK_OFS),
  1917. readl(mmio + PCI_IRQ_CAUSE_OFS),
  1918. readl(mmio + PCI_IRQ_MASK_OFS));
  1919. done:
  1920. return rc;
  1921. }
  1922. /**
  1923. * mv_print_info - Dump key info to kernel log for perusal.
  1924. * @probe_ent: early data struct representing the host
  1925. *
  1926. * FIXME: complete this.
  1927. *
  1928. * LOCKING:
  1929. * Inherited from caller.
  1930. */
  1931. static void mv_print_info(struct ata_probe_ent *probe_ent)
  1932. {
  1933. struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
  1934. struct mv_host_priv *hpriv = probe_ent->private_data;
  1935. u8 rev_id, scc;
  1936. const char *scc_s;
  1937. /* Use this to determine the HW stepping of the chip so we know
  1938. * what errata to workaround
  1939. */
  1940. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
  1941. pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
  1942. if (scc == 0)
  1943. scc_s = "SCSI";
  1944. else if (scc == 0x01)
  1945. scc_s = "RAID";
  1946. else
  1947. scc_s = "unknown";
  1948. dev_printk(KERN_INFO, &pdev->dev,
  1949. "%u slots %u ports %s mode IRQ via %s\n",
  1950. (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
  1951. scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
  1952. }
  1953. /**
  1954. * mv_init_one - handle a positive probe of a Marvell host
  1955. * @pdev: PCI device found
  1956. * @ent: PCI device ID entry for the matched host
  1957. *
  1958. * LOCKING:
  1959. * Inherited from caller.
  1960. */
  1961. static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1962. {
  1963. static int printed_version = 0;
  1964. struct device *dev = &pdev->dev;
  1965. struct ata_probe_ent *probe_ent;
  1966. struct mv_host_priv *hpriv;
  1967. unsigned int board_idx = (unsigned int)ent->driver_data;
  1968. int rc;
  1969. if (!printed_version++)
  1970. dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
  1971. rc = pcim_enable_device(pdev);
  1972. if (rc)
  1973. return rc;
  1974. pci_set_master(pdev);
  1975. rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
  1976. if (rc == -EBUSY)
  1977. pcim_pin_device(pdev);
  1978. if (rc)
  1979. return rc;
  1980. probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
  1981. if (probe_ent == NULL)
  1982. return -ENOMEM;
  1983. probe_ent->dev = pci_dev_to_dev(pdev);
  1984. INIT_LIST_HEAD(&probe_ent->node);
  1985. hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
  1986. if (!hpriv)
  1987. return -ENOMEM;
  1988. probe_ent->sht = mv_port_info[board_idx].sht;
  1989. probe_ent->port_flags = mv_port_info[board_idx].flags;
  1990. probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
  1991. probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
  1992. probe_ent->port_ops = mv_port_info[board_idx].port_ops;
  1993. probe_ent->irq = pdev->irq;
  1994. probe_ent->irq_flags = IRQF_SHARED;
  1995. probe_ent->iomap = pcim_iomap_table(pdev);
  1996. probe_ent->private_data = hpriv;
  1997. /* initialize adapter */
  1998. rc = mv_init_host(pdev, probe_ent, board_idx);
  1999. if (rc)
  2000. return rc;
  2001. /* Enable interrupts */
  2002. if (msi && pci_enable_msi(pdev))
  2003. pci_intx(pdev, 1);
  2004. mv_dump_pci_cfg(pdev, 0x68);
  2005. mv_print_info(probe_ent);
  2006. if (ata_device_add(probe_ent) == 0)
  2007. return -ENODEV;
  2008. devm_kfree(dev, probe_ent);
  2009. return 0;
  2010. }
  2011. static int __init mv_init(void)
  2012. {
  2013. return pci_register_driver(&mv_pci_driver);
  2014. }
  2015. static void __exit mv_exit(void)
  2016. {
  2017. pci_unregister_driver(&mv_pci_driver);
  2018. }
  2019. MODULE_AUTHOR("Brett Russ");
  2020. MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
  2021. MODULE_LICENSE("GPL");
  2022. MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
  2023. MODULE_VERSION(DRV_VERSION);
  2024. module_param(msi, int, 0444);
  2025. MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
  2026. module_init(mv_init);
  2027. module_exit(mv_exit);