pata_serverworks.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617
  1. /*
  2. * ata-serverworks.c - Serverworks PATA for new ATA layer
  3. * (C) 2005 Red Hat Inc
  4. * Alan Cox <alan@redhat.com>
  5. *
  6. * based upon
  7. *
  8. * serverworks.c
  9. *
  10. * Copyright (C) 1998-2000 Michel Aubry
  11. * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
  12. * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
  13. * Portions copyright (c) 2001 Sun Microsystems
  14. *
  15. *
  16. * RCC/ServerWorks IDE driver for Linux
  17. *
  18. * OSB4: `Open South Bridge' IDE Interface (fn 1)
  19. * supports UDMA mode 2 (33 MB/s)
  20. *
  21. * CSB5: `Champion South Bridge' IDE Interface (fn 1)
  22. * all revisions support UDMA mode 4 (66 MB/s)
  23. * revision A2.0 and up support UDMA mode 5 (100 MB/s)
  24. *
  25. * *** The CSB5 does not provide ANY register ***
  26. * *** to detect 80-conductor cable presence. ***
  27. *
  28. * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  29. *
  30. * Documentation:
  31. * Available under NDA only. Errata info very hard to get.
  32. */
  33. #include <linux/kernel.h>
  34. #include <linux/module.h>
  35. #include <linux/pci.h>
  36. #include <linux/init.h>
  37. #include <linux/blkdev.h>
  38. #include <linux/delay.h>
  39. #include <scsi/scsi_host.h>
  40. #include <linux/libata.h>
  41. #define DRV_NAME "pata_serverworks"
  42. #define DRV_VERSION "0.4.0"
  43. #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  44. #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  45. /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  46. * can overrun their FIFOs when used with the CSB5 */
  47. static const char *csb_bad_ata100[] = {
  48. "ST320011A",
  49. "ST340016A",
  50. "ST360021A",
  51. "ST380021A",
  52. NULL
  53. };
  54. /**
  55. * dell_cable - Dell serverworks cable detection
  56. * @ap: ATA port to do cable detect
  57. *
  58. * Dell hide the 40/80 pin select for their interfaces in the top two
  59. * bits of the subsystem ID.
  60. */
  61. static int dell_cable(struct ata_port *ap) {
  62. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  63. if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
  64. return ATA_CBL_PATA80;
  65. return ATA_CBL_PATA40;
  66. }
  67. /**
  68. * sun_cable - Sun Cobalt 'Alpine' cable detection
  69. * @ap: ATA port to do cable select
  70. *
  71. * Cobalt CSB5 IDE hides the 40/80pin in the top two bits of the
  72. * subsystem ID the same as dell. We could use one function but we may
  73. * need to extend the Dell one in future
  74. */
  75. static int sun_cable(struct ata_port *ap) {
  76. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  77. if (pdev->subsystem_device & (1 << (ap->port_no + 14)))
  78. return ATA_CBL_PATA80;
  79. return ATA_CBL_PATA40;
  80. }
  81. /**
  82. * osb4_cable - OSB4 cable detect
  83. * @ap: ATA port to check
  84. *
  85. * The OSB4 isn't UDMA66 capable so this is easy
  86. */
  87. static int osb4_cable(struct ata_port *ap) {
  88. return ATA_CBL_PATA40;
  89. }
  90. /**
  91. * csb4_cable - CSB5/6 cable detect
  92. * @ap: ATA port to check
  93. *
  94. * Serverworks default arrangement is to use the drive side detection
  95. * only.
  96. */
  97. static int csb_cable(struct ata_port *ap) {
  98. return ATA_CBL_PATA80;
  99. }
  100. struct sv_cable_table {
  101. int device;
  102. int subvendor;
  103. int (*cable_detect)(struct ata_port *ap);
  104. };
  105. /*
  106. * Note that we don't copy the old serverworks code because the old
  107. * code contains obvious mistakes
  108. */
  109. static struct sv_cable_table cable_detect[] = {
  110. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_DELL, dell_cable },
  111. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_VENDOR_ID_DELL, dell_cable },
  112. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_VENDOR_ID_SUN, sun_cable },
  113. { PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, osb4_cable },
  114. { PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, csb_cable },
  115. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, csb_cable },
  116. { PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, csb_cable },
  117. { PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, csb_cable },
  118. { }
  119. };
  120. /**
  121. * serverworks_pre_reset - cable detection
  122. * @ap: ATA port
  123. *
  124. * Perform cable detection according to the device and subvendor
  125. * identifications
  126. */
  127. static int serverworks_pre_reset(struct ata_port *ap) {
  128. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  129. struct sv_cable_table *cb = cable_detect;
  130. while(cb->device) {
  131. if (cb->device == pdev->device &&
  132. (cb->subvendor == pdev->subsystem_vendor ||
  133. cb->subvendor == PCI_ANY_ID)) {
  134. ap->cbl = cb->cable_detect(ap);
  135. return ata_std_prereset(ap);
  136. }
  137. cb++;
  138. }
  139. BUG();
  140. return -1; /* kill compiler warning */
  141. }
  142. static void serverworks_error_handler(struct ata_port *ap)
  143. {
  144. return ata_bmdma_drive_eh(ap, serverworks_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  145. }
  146. /**
  147. * serverworks_is_csb - Check for CSB or OSB
  148. * @pdev: PCI device to check
  149. *
  150. * Returns true if the device being checked is known to be a CSB
  151. * series device.
  152. */
  153. static u8 serverworks_is_csb(struct pci_dev *pdev)
  154. {
  155. switch (pdev->device) {
  156. case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  157. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  158. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  159. case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
  160. return 1;
  161. default:
  162. break;
  163. }
  164. return 0;
  165. }
  166. /**
  167. * serverworks_osb4_filter - mode selection filter
  168. * @ap: ATA interface
  169. * @adev: ATA device
  170. *
  171. * Filter the offered modes for the device to apply controller
  172. * specific rules. OSB4 requires no UDMA for disks due to a FIFO
  173. * bug we hit.
  174. */
  175. static unsigned long serverworks_osb4_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
  176. {
  177. if (adev->class == ATA_DEV_ATA)
  178. mask &= ~ATA_MASK_UDMA;
  179. return ata_pci_default_filter(ap, adev, mask);
  180. }
  181. /**
  182. * serverworks_csb_filter - mode selection filter
  183. * @ap: ATA interface
  184. * @adev: ATA device
  185. *
  186. * Check the blacklist and disable UDMA5 if matched
  187. */
  188. static unsigned long serverworks_csb_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
  189. {
  190. const char *p;
  191. char model_num[ATA_ID_PROD_LEN + 1];
  192. int i;
  193. /* Disk, UDMA */
  194. if (adev->class != ATA_DEV_ATA)
  195. return ata_pci_default_filter(ap, adev, mask);
  196. /* Actually do need to check */
  197. ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
  198. for (i = 0; (p = csb_bad_ata100[i]) != NULL; i++) {
  199. if (!strcmp(p, model_num))
  200. mask &= ~(0x1F << ATA_SHIFT_UDMA);
  201. }
  202. return ata_pci_default_filter(ap, adev, mask);
  203. }
  204. /**
  205. * serverworks_set_piomode - set initial PIO mode data
  206. * @ap: ATA interface
  207. * @adev: ATA device
  208. *
  209. * Program the OSB4/CSB5 timing registers for PIO. The PIO register
  210. * load is done as a simple lookup.
  211. */
  212. static void serverworks_set_piomode(struct ata_port *ap, struct ata_device *adev)
  213. {
  214. static const u8 pio_mode[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
  215. int offset = 1 + (2 * ap->port_no) - adev->devno;
  216. int devbits = (2 * ap->port_no + adev->devno) * 4;
  217. u16 csb5_pio;
  218. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  219. int pio = adev->pio_mode - XFER_PIO_0;
  220. pci_write_config_byte(pdev, 0x40 + offset, pio_mode[pio]);
  221. /* The OSB4 just requires the timing but the CSB series want the
  222. mode number as well */
  223. if (serverworks_is_csb(pdev)) {
  224. pci_read_config_word(pdev, 0x4A, &csb5_pio);
  225. csb5_pio &= ~(0x0F << devbits);
  226. pci_write_config_byte(pdev, 0x4A, csb5_pio | (pio << devbits));
  227. }
  228. }
  229. /**
  230. * serverworks_set_dmamode - set initial DMA mode data
  231. * @ap: ATA interface
  232. * @adev: ATA device
  233. *
  234. * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
  235. * chipset. The MWDMA mode values are pulled from a lookup table
  236. * while the chipset uses mode number for UDMA.
  237. */
  238. static void serverworks_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  239. {
  240. static const u8 dma_mode[] = { 0x77, 0x21, 0x20 };
  241. int offset = 1 + 2 * ap->port_no - adev->devno;
  242. int devbits = (2 * ap->port_no + adev->devno);
  243. u8 ultra;
  244. u8 ultra_cfg;
  245. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  246. pci_read_config_byte(pdev, 0x54, &ultra_cfg);
  247. if (adev->dma_mode >= XFER_UDMA_0) {
  248. pci_write_config_byte(pdev, 0x44 + offset, 0x20);
  249. pci_read_config_byte(pdev, 0x56 + ap->port_no, &ultra);
  250. ultra &= ~(0x0F << (ap->port_no * 4));
  251. ultra |= (adev->dma_mode - XFER_UDMA_0)
  252. << (ap->port_no * 4);
  253. pci_write_config_byte(pdev, 0x56 + ap->port_no, ultra);
  254. ultra_cfg |= (1 << devbits);
  255. } else {
  256. pci_write_config_byte(pdev, 0x44 + offset,
  257. dma_mode[adev->dma_mode - XFER_MW_DMA_0]);
  258. ultra_cfg &= ~(1 << devbits);
  259. }
  260. pci_write_config_byte(pdev, 0x54, ultra_cfg);
  261. }
  262. static struct scsi_host_template serverworks_sht = {
  263. .module = THIS_MODULE,
  264. .name = DRV_NAME,
  265. .ioctl = ata_scsi_ioctl,
  266. .queuecommand = ata_scsi_queuecmd,
  267. .can_queue = ATA_DEF_QUEUE,
  268. .this_id = ATA_SHT_THIS_ID,
  269. .sg_tablesize = LIBATA_MAX_PRD,
  270. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  271. .emulated = ATA_SHT_EMULATED,
  272. .use_clustering = ATA_SHT_USE_CLUSTERING,
  273. .proc_name = DRV_NAME,
  274. .dma_boundary = ATA_DMA_BOUNDARY,
  275. .slave_configure = ata_scsi_slave_config,
  276. .slave_destroy = ata_scsi_slave_destroy,
  277. .bios_param = ata_std_bios_param,
  278. #ifdef CONFIG_PM
  279. .resume = ata_scsi_device_resume,
  280. .suspend = ata_scsi_device_suspend,
  281. #endif
  282. };
  283. static struct ata_port_operations serverworks_osb4_port_ops = {
  284. .port_disable = ata_port_disable,
  285. .set_piomode = serverworks_set_piomode,
  286. .set_dmamode = serverworks_set_dmamode,
  287. .mode_filter = serverworks_osb4_filter,
  288. .tf_load = ata_tf_load,
  289. .tf_read = ata_tf_read,
  290. .check_status = ata_check_status,
  291. .exec_command = ata_exec_command,
  292. .dev_select = ata_std_dev_select,
  293. .freeze = ata_bmdma_freeze,
  294. .thaw = ata_bmdma_thaw,
  295. .error_handler = serverworks_error_handler,
  296. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  297. .bmdma_setup = ata_bmdma_setup,
  298. .bmdma_start = ata_bmdma_start,
  299. .bmdma_stop = ata_bmdma_stop,
  300. .bmdma_status = ata_bmdma_status,
  301. .qc_prep = ata_qc_prep,
  302. .qc_issue = ata_qc_issue_prot,
  303. .data_xfer = ata_data_xfer,
  304. .irq_handler = ata_interrupt,
  305. .irq_clear = ata_bmdma_irq_clear,
  306. .irq_on = ata_irq_on,
  307. .irq_ack = ata_irq_ack,
  308. .port_start = ata_port_start,
  309. };
  310. static struct ata_port_operations serverworks_csb_port_ops = {
  311. .port_disable = ata_port_disable,
  312. .set_piomode = serverworks_set_piomode,
  313. .set_dmamode = serverworks_set_dmamode,
  314. .mode_filter = serverworks_csb_filter,
  315. .tf_load = ata_tf_load,
  316. .tf_read = ata_tf_read,
  317. .check_status = ata_check_status,
  318. .exec_command = ata_exec_command,
  319. .dev_select = ata_std_dev_select,
  320. .freeze = ata_bmdma_freeze,
  321. .thaw = ata_bmdma_thaw,
  322. .error_handler = serverworks_error_handler,
  323. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  324. .bmdma_setup = ata_bmdma_setup,
  325. .bmdma_start = ata_bmdma_start,
  326. .bmdma_stop = ata_bmdma_stop,
  327. .bmdma_status = ata_bmdma_status,
  328. .qc_prep = ata_qc_prep,
  329. .qc_issue = ata_qc_issue_prot,
  330. .data_xfer = ata_data_xfer,
  331. .irq_handler = ata_interrupt,
  332. .irq_clear = ata_bmdma_irq_clear,
  333. .irq_on = ata_irq_on,
  334. .irq_ack = ata_irq_ack,
  335. .port_start = ata_port_start,
  336. };
  337. static int serverworks_fixup_osb4(struct pci_dev *pdev)
  338. {
  339. u32 reg;
  340. struct pci_dev *isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  341. PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
  342. if (isa_dev) {
  343. pci_read_config_dword(isa_dev, 0x64, &reg);
  344. reg &= ~0x00002000; /* disable 600ns interrupt mask */
  345. if (!(reg & 0x00004000))
  346. printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n");
  347. reg |= 0x00004000; /* enable UDMA/33 support */
  348. pci_write_config_dword(isa_dev, 0x64, reg);
  349. pci_dev_put(isa_dev);
  350. return 0;
  351. }
  352. printk(KERN_WARNING "ata_serverworks: Unable to find bridge.\n");
  353. return -ENODEV;
  354. }
  355. static int serverworks_fixup_csb(struct pci_dev *pdev)
  356. {
  357. u8 rev;
  358. u8 btr;
  359. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  360. /* Third Channel Test */
  361. if (!(PCI_FUNC(pdev->devfn) & 1)) {
  362. struct pci_dev * findev = NULL;
  363. u32 reg4c = 0;
  364. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  365. PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
  366. if (findev) {
  367. pci_read_config_dword(findev, 0x4C, &reg4c);
  368. reg4c &= ~0x000007FF;
  369. reg4c |= 0x00000040;
  370. reg4c |= 0x00000020;
  371. pci_write_config_dword(findev, 0x4C, reg4c);
  372. pci_dev_put(findev);
  373. }
  374. } else {
  375. struct pci_dev * findev = NULL;
  376. u8 reg41 = 0;
  377. findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  378. PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
  379. if (findev) {
  380. pci_read_config_byte(findev, 0x41, &reg41);
  381. reg41 &= ~0x40;
  382. pci_write_config_byte(findev, 0x41, reg41);
  383. pci_dev_put(findev);
  384. }
  385. }
  386. /* setup the UDMA Control register
  387. *
  388. * 1. clear bit 6 to enable DMA
  389. * 2. enable DMA modes with bits 0-1
  390. * 00 : legacy
  391. * 01 : udma2
  392. * 10 : udma2/udma4
  393. * 11 : udma2/udma4/udma5
  394. */
  395. pci_read_config_byte(pdev, 0x5A, &btr);
  396. btr &= ~0x40;
  397. if (!(PCI_FUNC(pdev->devfn) & 1))
  398. btr |= 0x2;
  399. else
  400. btr |= (rev >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
  401. pci_write_config_byte(pdev, 0x5A, btr);
  402. return btr;
  403. }
  404. static void serverworks_fixup_ht1000(struct pci_dev *pdev)
  405. {
  406. u8 btr;
  407. /* Setup HT1000 SouthBridge Controller - Single Channel Only */
  408. pci_read_config_byte(pdev, 0x5A, &btr);
  409. btr &= ~0x40;
  410. btr |= 0x3;
  411. pci_write_config_byte(pdev, 0x5A, btr);
  412. }
  413. static int serverworks_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  414. {
  415. int ports = 2;
  416. static struct ata_port_info info[4] = {
  417. { /* OSB4 */
  418. .sht = &serverworks_sht,
  419. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  420. .pio_mask = 0x1f,
  421. .mwdma_mask = 0x07,
  422. .udma_mask = 0x07,
  423. .port_ops = &serverworks_osb4_port_ops
  424. }, { /* OSB4 no UDMA */
  425. .sht = &serverworks_sht,
  426. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  427. .pio_mask = 0x1f,
  428. .mwdma_mask = 0x07,
  429. .udma_mask = 0x00,
  430. .port_ops = &serverworks_osb4_port_ops
  431. }, { /* CSB5 */
  432. .sht = &serverworks_sht,
  433. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  434. .pio_mask = 0x1f,
  435. .mwdma_mask = 0x07,
  436. .udma_mask = 0x1f,
  437. .port_ops = &serverworks_csb_port_ops
  438. }, { /* CSB5 - later revisions*/
  439. .sht = &serverworks_sht,
  440. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  441. .pio_mask = 0x1f,
  442. .mwdma_mask = 0x07,
  443. .udma_mask = 0x3f,
  444. .port_ops = &serverworks_csb_port_ops
  445. }
  446. };
  447. static struct ata_port_info *port_info[2];
  448. struct ata_port_info *devinfo = &info[id->driver_data];
  449. /* Force master latency timer to 64 PCI clocks */
  450. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
  451. /* OSB4 : South Bridge and IDE */
  452. if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  453. /* Select non UDMA capable OSB4 if we can't do fixups */
  454. if ( serverworks_fixup_osb4(pdev) < 0)
  455. devinfo = &info[1];
  456. }
  457. /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
  458. else if ((pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
  459. (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
  460. (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
  461. /* If the returned btr is the newer revision then
  462. select the right info block */
  463. if (serverworks_fixup_csb(pdev) == 3)
  464. devinfo = &info[3];
  465. /* Is this the 3rd channel CSB6 IDE ? */
  466. if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)
  467. ports = 1;
  468. }
  469. /* setup HT1000E */
  470. else if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  471. serverworks_fixup_ht1000(pdev);
  472. if (pdev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
  473. ata_pci_clear_simplex(pdev);
  474. port_info[0] = port_info[1] = devinfo;
  475. return ata_pci_init_one(pdev, port_info, ports);
  476. }
  477. #ifdef CONFIG_PM
  478. static int serverworks_reinit_one(struct pci_dev *pdev)
  479. {
  480. /* Force master latency timer to 64 PCI clocks */
  481. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
  482. switch (pdev->device)
  483. {
  484. case PCI_DEVICE_ID_SERVERWORKS_OSB4IDE:
  485. serverworks_fixup_osb4(pdev);
  486. break;
  487. case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
  488. ata_pci_clear_simplex(pdev);
  489. /* fall through */
  490. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
  491. case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
  492. serverworks_fixup_csb(pdev);
  493. break;
  494. case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
  495. serverworks_fixup_ht1000(pdev);
  496. break;
  497. }
  498. return ata_pci_device_resume(pdev);
  499. }
  500. #endif
  501. static const struct pci_device_id serverworks[] = {
  502. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0},
  503. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 2},
  504. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2},
  505. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 2},
  506. { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 2},
  507. { },
  508. };
  509. static struct pci_driver serverworks_pci_driver = {
  510. .name = DRV_NAME,
  511. .id_table = serverworks,
  512. .probe = serverworks_init_one,
  513. .remove = ata_pci_remove_one,
  514. #ifdef CONFIG_PM
  515. .suspend = ata_pci_device_suspend,
  516. .resume = serverworks_reinit_one,
  517. #endif
  518. };
  519. static int __init serverworks_init(void)
  520. {
  521. return pci_register_driver(&serverworks_pci_driver);
  522. }
  523. static void __exit serverworks_exit(void)
  524. {
  525. pci_unregister_driver(&serverworks_pci_driver);
  526. }
  527. MODULE_AUTHOR("Alan Cox");
  528. MODULE_DESCRIPTION("low-level driver for Serverworks OSB4/CSB5/CSB6");
  529. MODULE_LICENSE("GPL");
  530. MODULE_DEVICE_TABLE(pci, serverworks);
  531. MODULE_VERSION(DRV_VERSION);
  532. module_init(serverworks_init);
  533. module_exit(serverworks_exit);