pata_pdc202xx_old.c 11 KB

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  1. /*
  2. * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
  3. * (C) 2005 Red Hat Inc
  4. * Alan Cox <alan@redhat.com>
  5. * (C) 2007 Bartlomiej Zolnierkiewicz
  6. *
  7. * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
  8. *
  9. * First cut with LBA48/ATAPI
  10. *
  11. * TODO:
  12. * Channel interlock/reset on both required
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/init.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/delay.h>
  20. #include <scsi/scsi_host.h>
  21. #include <linux/libata.h>
  22. #define DRV_NAME "pata_pdc202xx_old"
  23. #define DRV_VERSION "0.4.0"
  24. /**
  25. * pdc2024x_pre_reset - probe begin
  26. * @ap: ATA port
  27. *
  28. * Set up cable type and use generic probe init
  29. */
  30. static int pdc2024x_pre_reset(struct ata_port *ap)
  31. {
  32. ap->cbl = ATA_CBL_PATA40;
  33. return ata_std_prereset(ap);
  34. }
  35. static void pdc2024x_error_handler(struct ata_port *ap)
  36. {
  37. ata_bmdma_drive_eh(ap, pdc2024x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  38. }
  39. static int pdc2026x_pre_reset(struct ata_port *ap)
  40. {
  41. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  42. u16 cis;
  43. pci_read_config_word(pdev, 0x50, &cis);
  44. if (cis & (1 << (10 + ap->port_no)))
  45. ap->cbl = ATA_CBL_PATA80;
  46. else
  47. ap->cbl = ATA_CBL_PATA40;
  48. return ata_std_prereset(ap);
  49. }
  50. static void pdc2026x_error_handler(struct ata_port *ap)
  51. {
  52. ata_bmdma_drive_eh(ap, pdc2026x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  53. }
  54. /**
  55. * pdc202xx_configure_piomode - set chip PIO timing
  56. * @ap: ATA interface
  57. * @adev: ATA device
  58. * @pio: PIO mode
  59. *
  60. * Called to do the PIO mode setup. Our timing registers are shared
  61. * so a configure_dmamode call will undo any work we do here and vice
  62. * versa
  63. */
  64. static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
  65. {
  66. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  67. int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
  68. static u16 pio_timing[5] = {
  69. 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
  70. };
  71. u8 r_ap, r_bp;
  72. pci_read_config_byte(pdev, port, &r_ap);
  73. pci_read_config_byte(pdev, port + 1, &r_bp);
  74. r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
  75. r_bp &= ~0x1F;
  76. r_ap |= (pio_timing[pio] >> 8);
  77. r_bp |= (pio_timing[pio] & 0xFF);
  78. if (ata_pio_need_iordy(adev))
  79. r_ap |= 0x20; /* IORDY enable */
  80. if (adev->class == ATA_DEV_ATA)
  81. r_ap |= 0x10; /* FIFO enable */
  82. pci_write_config_byte(pdev, port, r_ap);
  83. pci_write_config_byte(pdev, port + 1, r_bp);
  84. }
  85. /**
  86. * pdc202xx_set_piomode - set initial PIO mode data
  87. * @ap: ATA interface
  88. * @adev: ATA device
  89. *
  90. * Called to do the PIO mode setup. Our timing registers are shared
  91. * but we want to set the PIO timing by default.
  92. */
  93. static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
  94. {
  95. pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  96. }
  97. /**
  98. * pdc202xx_configure_dmamode - set DMA mode in chip
  99. * @ap: ATA interface
  100. * @adev: ATA device
  101. *
  102. * Load DMA cycle times into the chip ready for a DMA transfer
  103. * to occur.
  104. */
  105. static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  106. {
  107. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  108. int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
  109. static u8 udma_timing[6][2] = {
  110. { 0x60, 0x03 }, /* 33 Mhz Clock */
  111. { 0x40, 0x02 },
  112. { 0x20, 0x01 },
  113. { 0x40, 0x02 }, /* 66 Mhz Clock */
  114. { 0x20, 0x01 },
  115. { 0x20, 0x01 }
  116. };
  117. static u8 mdma_timing[3][2] = {
  118. { 0x60, 0x03 },
  119. { 0x60, 0x04 },
  120. { 0xe0, 0x0f },
  121. };
  122. u8 r_bp, r_cp;
  123. pci_read_config_byte(pdev, port + 1, &r_bp);
  124. pci_read_config_byte(pdev, port + 2, &r_cp);
  125. r_bp &= ~0xE0;
  126. r_cp &= ~0x0F;
  127. if (adev->dma_mode >= XFER_UDMA_0) {
  128. int speed = adev->dma_mode - XFER_UDMA_0;
  129. r_bp |= udma_timing[speed][0];
  130. r_cp |= udma_timing[speed][1];
  131. } else {
  132. int speed = adev->dma_mode - XFER_MW_DMA_0;
  133. r_bp |= mdma_timing[speed][0];
  134. r_cp |= mdma_timing[speed][1];
  135. }
  136. pci_write_config_byte(pdev, port + 1, r_bp);
  137. pci_write_config_byte(pdev, port + 2, r_cp);
  138. }
  139. /**
  140. * pdc2026x_bmdma_start - DMA engine begin
  141. * @qc: ATA command
  142. *
  143. * In UDMA3 or higher we have to clock switch for the duration of the
  144. * DMA transfer sequence.
  145. */
  146. static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
  147. {
  148. struct ata_port *ap = qc->ap;
  149. struct ata_device *adev = qc->dev;
  150. struct ata_taskfile *tf = &qc->tf;
  151. int sel66 = ap->port_no ? 0x08: 0x02;
  152. void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
  153. void __iomem *clock = master + 0x11;
  154. void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
  155. u32 len;
  156. /* Check we keep host level locking here */
  157. if (adev->dma_mode >= XFER_UDMA_2)
  158. iowrite8(ioread8(clock) | sel66, clock);
  159. else
  160. iowrite8(ioread8(clock) & ~sel66, clock);
  161. /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
  162. and move to qc_issue ? */
  163. pdc202xx_set_dmamode(ap, qc->dev);
  164. /* Cases the state machine will not complete correctly without help */
  165. if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATA_PROT_ATAPI_DMA)
  166. {
  167. len = qc->nbytes / 2;
  168. if (tf->flags & ATA_TFLAG_WRITE)
  169. len |= 0x06000000;
  170. else
  171. len |= 0x05000000;
  172. iowrite32(len, atapi_reg);
  173. }
  174. /* Activate DMA */
  175. ata_bmdma_start(qc);
  176. }
  177. /**
  178. * pdc2026x_bmdma_end - DMA engine stop
  179. * @qc: ATA command
  180. *
  181. * After a DMA completes we need to put the clock back to 33MHz for
  182. * PIO timings.
  183. */
  184. static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
  185. {
  186. struct ata_port *ap = qc->ap;
  187. struct ata_device *adev = qc->dev;
  188. struct ata_taskfile *tf = &qc->tf;
  189. int sel66 = ap->port_no ? 0x08: 0x02;
  190. /* The clock bits are in the same register for both channels */
  191. void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
  192. void __iomem *clock = master + 0x11;
  193. void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
  194. /* Cases the state machine will not complete correctly */
  195. if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
  196. iowrite32(0, atapi_reg);
  197. iowrite8(ioread8(clock) & ~sel66, clock);
  198. }
  199. /* Check we keep host level locking here */
  200. /* Flip back to 33Mhz for PIO */
  201. if (adev->dma_mode >= XFER_UDMA_2)
  202. iowrite8(ioread8(clock) & ~sel66, clock);
  203. ata_bmdma_stop(qc);
  204. }
  205. /**
  206. * pdc2026x_dev_config - device setup hook
  207. * @ap: ATA port
  208. * @adev: newly found device
  209. *
  210. * Perform chip specific early setup. We need to lock the transfer
  211. * sizes to 8bit to avoid making the state engine on the 2026x cards
  212. * barf.
  213. */
  214. static void pdc2026x_dev_config(struct ata_port *ap, struct ata_device *adev)
  215. {
  216. adev->max_sectors = 256;
  217. }
  218. static struct scsi_host_template pdc202xx_sht = {
  219. .module = THIS_MODULE,
  220. .name = DRV_NAME,
  221. .ioctl = ata_scsi_ioctl,
  222. .queuecommand = ata_scsi_queuecmd,
  223. .can_queue = ATA_DEF_QUEUE,
  224. .this_id = ATA_SHT_THIS_ID,
  225. .sg_tablesize = LIBATA_MAX_PRD,
  226. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  227. .emulated = ATA_SHT_EMULATED,
  228. .use_clustering = ATA_SHT_USE_CLUSTERING,
  229. .proc_name = DRV_NAME,
  230. .dma_boundary = ATA_DMA_BOUNDARY,
  231. .slave_configure = ata_scsi_slave_config,
  232. .slave_destroy = ata_scsi_slave_destroy,
  233. .bios_param = ata_std_bios_param,
  234. #ifdef CONFIG_PM
  235. .resume = ata_scsi_device_resume,
  236. .suspend = ata_scsi_device_suspend,
  237. #endif
  238. };
  239. static struct ata_port_operations pdc2024x_port_ops = {
  240. .port_disable = ata_port_disable,
  241. .set_piomode = pdc202xx_set_piomode,
  242. .set_dmamode = pdc202xx_set_dmamode,
  243. .mode_filter = ata_pci_default_filter,
  244. .tf_load = ata_tf_load,
  245. .tf_read = ata_tf_read,
  246. .check_status = ata_check_status,
  247. .exec_command = ata_exec_command,
  248. .dev_select = ata_std_dev_select,
  249. .freeze = ata_bmdma_freeze,
  250. .thaw = ata_bmdma_thaw,
  251. .error_handler = pdc2024x_error_handler,
  252. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  253. .bmdma_setup = ata_bmdma_setup,
  254. .bmdma_start = ata_bmdma_start,
  255. .bmdma_stop = ata_bmdma_stop,
  256. .bmdma_status = ata_bmdma_status,
  257. .qc_prep = ata_qc_prep,
  258. .qc_issue = ata_qc_issue_prot,
  259. .data_xfer = ata_data_xfer,
  260. .irq_handler = ata_interrupt,
  261. .irq_clear = ata_bmdma_irq_clear,
  262. .irq_on = ata_irq_on,
  263. .irq_ack = ata_irq_ack,
  264. .port_start = ata_port_start,
  265. };
  266. static struct ata_port_operations pdc2026x_port_ops = {
  267. .port_disable = ata_port_disable,
  268. .set_piomode = pdc202xx_set_piomode,
  269. .set_dmamode = pdc202xx_set_dmamode,
  270. .mode_filter = ata_pci_default_filter,
  271. .tf_load = ata_tf_load,
  272. .tf_read = ata_tf_read,
  273. .check_status = ata_check_status,
  274. .exec_command = ata_exec_command,
  275. .dev_select = ata_std_dev_select,
  276. .dev_config = pdc2026x_dev_config,
  277. .freeze = ata_bmdma_freeze,
  278. .thaw = ata_bmdma_thaw,
  279. .error_handler = pdc2026x_error_handler,
  280. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  281. .bmdma_setup = ata_bmdma_setup,
  282. .bmdma_start = pdc2026x_bmdma_start,
  283. .bmdma_stop = pdc2026x_bmdma_stop,
  284. .bmdma_status = ata_bmdma_status,
  285. .qc_prep = ata_qc_prep,
  286. .qc_issue = ata_qc_issue_prot,
  287. .data_xfer = ata_data_xfer,
  288. .irq_handler = ata_interrupt,
  289. .irq_clear = ata_bmdma_irq_clear,
  290. .irq_on = ata_irq_on,
  291. .irq_ack = ata_irq_ack,
  292. .port_start = ata_port_start,
  293. };
  294. static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  295. {
  296. static struct ata_port_info info[3] = {
  297. {
  298. .sht = &pdc202xx_sht,
  299. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  300. .pio_mask = 0x1f,
  301. .mwdma_mask = 0x07,
  302. .udma_mask = ATA_UDMA2,
  303. .port_ops = &pdc2024x_port_ops
  304. },
  305. {
  306. .sht = &pdc202xx_sht,
  307. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  308. .pio_mask = 0x1f,
  309. .mwdma_mask = 0x07,
  310. .udma_mask = ATA_UDMA4,
  311. .port_ops = &pdc2026x_port_ops
  312. },
  313. {
  314. .sht = &pdc202xx_sht,
  315. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  316. .pio_mask = 0x1f,
  317. .mwdma_mask = 0x07,
  318. .udma_mask = ATA_UDMA5,
  319. .port_ops = &pdc2026x_port_ops
  320. }
  321. };
  322. static struct ata_port_info *port_info[2];
  323. port_info[0] = port_info[1] = &info[id->driver_data];
  324. if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
  325. struct pci_dev *bridge = dev->bus->self;
  326. /* Don't grab anything behind a Promise I2O RAID */
  327. if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
  328. if( bridge->device == PCI_DEVICE_ID_INTEL_I960)
  329. return -ENODEV;
  330. if( bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
  331. return -ENODEV;
  332. }
  333. }
  334. return ata_pci_init_one(dev, port_info, 2);
  335. }
  336. static const struct pci_device_id pdc202xx[] = {
  337. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
  338. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
  339. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
  340. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
  341. { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
  342. { },
  343. };
  344. static struct pci_driver pdc202xx_pci_driver = {
  345. .name = DRV_NAME,
  346. .id_table = pdc202xx,
  347. .probe = pdc202xx_init_one,
  348. .remove = ata_pci_remove_one,
  349. #ifdef CONFIG_PM
  350. .suspend = ata_pci_device_suspend,
  351. .resume = ata_pci_device_resume,
  352. #endif
  353. };
  354. static int __init pdc202xx_init(void)
  355. {
  356. return pci_register_driver(&pdc202xx_pci_driver);
  357. }
  358. static void __exit pdc202xx_exit(void)
  359. {
  360. pci_unregister_driver(&pdc202xx_pci_driver);
  361. }
  362. MODULE_AUTHOR("Alan Cox");
  363. MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
  364. MODULE_LICENSE("GPL");
  365. MODULE_DEVICE_TABLE(pci, pdc202xx);
  366. MODULE_VERSION(DRV_VERSION);
  367. module_init(pdc202xx_init);
  368. module_exit(pdc202xx_exit);