math.c 73 KB

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  1. /*
  2. * arch/s390/math-emu/math.c
  3. *
  4. * S390 version
  5. * Copyright (C) 1999-2001 IBM Deutschland Entwicklung GmbH, IBM Corporation
  6. * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  7. *
  8. * 'math.c' emulates IEEE instructions on a S390 processor
  9. * that does not have the IEEE fpu (all processors before G5).
  10. */
  11. #include <linux/types.h>
  12. #include <linux/sched.h>
  13. #include <linux/mm.h>
  14. #include <asm/uaccess.h>
  15. #include <asm/lowcore.h>
  16. #include <asm/sfp-util.h>
  17. #include <math-emu/soft-fp.h>
  18. #include <math-emu/single.h>
  19. #include <math-emu/double.h>
  20. #include <math-emu/quad.h>
  21. /*
  22. * I miss a macro to round a floating point number to the
  23. * nearest integer in the same floating point format.
  24. */
  25. #define _FP_TO_FPINT_ROUND(fs, wc, X) \
  26. do { \
  27. switch (X##_c) \
  28. { \
  29. case FP_CLS_NORMAL: \
  30. if (X##_e > _FP_FRACBITS_##fs + _FP_EXPBIAS_##fs) \
  31. { /* floating point number has no bits after the dot. */ \
  32. } \
  33. else if (X##_e <= _FP_FRACBITS_##fs + _FP_EXPBIAS_##fs && \
  34. X##_e > _FP_EXPBIAS_##fs) \
  35. { /* some bits before the dot, some after it. */ \
  36. _FP_FRAC_SRS_##wc(X, _FP_WFRACBITS_##fs, \
  37. X##_e - _FP_EXPBIAS_##fs \
  38. + _FP_FRACBITS_##fs); \
  39. _FP_ROUND(wc, X); \
  40. _FP_FRAC_SLL_##wc(X, X##_e - _FP_EXPBIAS_##fs \
  41. + _FP_FRACBITS_##fs); \
  42. } \
  43. else \
  44. { /* all bits after the dot. */ \
  45. FP_SET_EXCEPTION(FP_EX_INEXACT); \
  46. X##_c = FP_CLS_ZERO; \
  47. } \
  48. break; \
  49. case FP_CLS_NAN: \
  50. case FP_CLS_INF: \
  51. case FP_CLS_ZERO: \
  52. break; \
  53. } \
  54. } while (0)
  55. #define FP_TO_FPINT_ROUND_S(X) _FP_TO_FPINT_ROUND(S,1,X)
  56. #define FP_TO_FPINT_ROUND_D(X) _FP_TO_FPINT_ROUND(D,2,X)
  57. #define FP_TO_FPINT_ROUND_Q(X) _FP_TO_FPINT_ROUND(Q,4,X)
  58. typedef union {
  59. long double ld;
  60. struct {
  61. __u64 high;
  62. __u64 low;
  63. } w;
  64. } mathemu_ldcv;
  65. #ifdef CONFIG_SYSCTL
  66. int sysctl_ieee_emulation_warnings=1;
  67. #endif
  68. #define mathemu_put_user(x, p) \
  69. do { \
  70. if (put_user((x),(p))) \
  71. return SIGSEGV; \
  72. } while (0)
  73. #define mathemu_get_user(x, p) \
  74. do { \
  75. if (get_user((x),(p))) \
  76. return SIGSEGV; \
  77. } while (0)
  78. #define mathemu_copy_from_user(d, s, n)\
  79. do { \
  80. if (copy_from_user((d),(s),(n)) != 0) \
  81. return SIGSEGV; \
  82. } while (0)
  83. #define mathemu_copy_to_user(d, s, n) \
  84. do { \
  85. if (copy_to_user((d),(s),(n)) != 0) \
  86. return SIGSEGV; \
  87. } while (0)
  88. static void display_emulation_not_implemented(struct pt_regs *regs, char *instr)
  89. {
  90. __u16 *location;
  91. #ifdef CONFIG_SYSCTL
  92. if(sysctl_ieee_emulation_warnings)
  93. #endif
  94. {
  95. location = (__u16 *)(regs->psw.addr-S390_lowcore.pgm_ilc);
  96. printk("%s ieee fpu instruction not emulated "
  97. "process name: %s pid: %d \n",
  98. instr, current->comm, current->pid);
  99. printk("%s's PSW: %08lx %08lx\n", instr,
  100. (unsigned long) regs->psw.mask,
  101. (unsigned long) location);
  102. }
  103. }
  104. static inline void emu_set_CC (struct pt_regs *regs, int cc)
  105. {
  106. regs->psw.mask = (regs->psw.mask & 0xFFFFCFFF) | ((cc&3) << 12);
  107. }
  108. /*
  109. * Set the condition code in the user psw.
  110. * 0 : Result is zero
  111. * 1 : Result is less than zero
  112. * 2 : Result is greater than zero
  113. * 3 : Result is NaN or INF
  114. */
  115. static inline void emu_set_CC_cs(struct pt_regs *regs, int class, int sign)
  116. {
  117. switch (class) {
  118. case FP_CLS_NORMAL:
  119. case FP_CLS_INF:
  120. emu_set_CC(regs, sign ? 1 : 2);
  121. break;
  122. case FP_CLS_ZERO:
  123. emu_set_CC(regs, 0);
  124. break;
  125. case FP_CLS_NAN:
  126. emu_set_CC(regs, 3);
  127. break;
  128. }
  129. }
  130. /* Add long double */
  131. static int emu_axbr (struct pt_regs *regs, int rx, int ry) {
  132. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  133. FP_DECL_EX;
  134. mathemu_ldcv cvt;
  135. int mode;
  136. mode = current->thread.fp_regs.fpc & 3;
  137. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  138. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  139. FP_UNPACK_QP(QA, &cvt.ld);
  140. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  141. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  142. FP_UNPACK_QP(QB, &cvt.ld);
  143. FP_ADD_Q(QR, QA, QB);
  144. FP_PACK_QP(&cvt.ld, QR);
  145. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  146. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  147. emu_set_CC_cs(regs, QR_c, QR_s);
  148. return _fex;
  149. }
  150. /* Add double */
  151. static int emu_adbr (struct pt_regs *regs, int rx, int ry) {
  152. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  153. FP_DECL_EX;
  154. int mode;
  155. mode = current->thread.fp_regs.fpc & 3;
  156. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  157. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  158. FP_ADD_D(DR, DA, DB);
  159. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  160. emu_set_CC_cs(regs, DR_c, DR_s);
  161. return _fex;
  162. }
  163. /* Add double */
  164. static int emu_adb (struct pt_regs *regs, int rx, double *val) {
  165. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  166. FP_DECL_EX;
  167. int mode;
  168. mode = current->thread.fp_regs.fpc & 3;
  169. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  170. FP_UNPACK_DP(DB, val);
  171. FP_ADD_D(DR, DA, DB);
  172. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  173. emu_set_CC_cs(regs, DR_c, DR_s);
  174. return _fex;
  175. }
  176. /* Add float */
  177. static int emu_aebr (struct pt_regs *regs, int rx, int ry) {
  178. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  179. FP_DECL_EX;
  180. int mode;
  181. mode = current->thread.fp_regs.fpc & 3;
  182. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  183. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  184. FP_ADD_S(SR, SA, SB);
  185. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  186. emu_set_CC_cs(regs, SR_c, SR_s);
  187. return _fex;
  188. }
  189. /* Add float */
  190. static int emu_aeb (struct pt_regs *regs, int rx, float *val) {
  191. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  192. FP_DECL_EX;
  193. int mode;
  194. mode = current->thread.fp_regs.fpc & 3;
  195. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  196. FP_UNPACK_SP(SB, val);
  197. FP_ADD_S(SR, SA, SB);
  198. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  199. emu_set_CC_cs(regs, SR_c, SR_s);
  200. return _fex;
  201. }
  202. /* Compare long double */
  203. static int emu_cxbr (struct pt_regs *regs, int rx, int ry) {
  204. FP_DECL_Q(QA); FP_DECL_Q(QB);
  205. mathemu_ldcv cvt;
  206. int IR;
  207. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  208. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  209. FP_UNPACK_RAW_QP(QA, &cvt.ld);
  210. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  211. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  212. FP_UNPACK_RAW_QP(QB, &cvt.ld);
  213. FP_CMP_Q(IR, QA, QB, 3);
  214. /*
  215. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  216. * IR == 1 if DA > DB and IR == 3 if unorderded
  217. */
  218. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  219. return 0;
  220. }
  221. /* Compare double */
  222. static int emu_cdbr (struct pt_regs *regs, int rx, int ry) {
  223. FP_DECL_D(DA); FP_DECL_D(DB);
  224. int IR;
  225. FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  226. FP_UNPACK_RAW_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  227. FP_CMP_D(IR, DA, DB, 3);
  228. /*
  229. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  230. * IR == 1 if DA > DB and IR == 3 if unorderded
  231. */
  232. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  233. return 0;
  234. }
  235. /* Compare double */
  236. static int emu_cdb (struct pt_regs *regs, int rx, double *val) {
  237. FP_DECL_D(DA); FP_DECL_D(DB);
  238. int IR;
  239. FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  240. FP_UNPACK_RAW_DP(DB, val);
  241. FP_CMP_D(IR, DA, DB, 3);
  242. /*
  243. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  244. * IR == 1 if DA > DB and IR == 3 if unorderded
  245. */
  246. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  247. return 0;
  248. }
  249. /* Compare float */
  250. static int emu_cebr (struct pt_regs *regs, int rx, int ry) {
  251. FP_DECL_S(SA); FP_DECL_S(SB);
  252. int IR;
  253. FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  254. FP_UNPACK_RAW_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  255. FP_CMP_S(IR, SA, SB, 3);
  256. /*
  257. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  258. * IR == 1 if DA > DB and IR == 3 if unorderded
  259. */
  260. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  261. return 0;
  262. }
  263. /* Compare float */
  264. static int emu_ceb (struct pt_regs *regs, int rx, float *val) {
  265. FP_DECL_S(SA); FP_DECL_S(SB);
  266. int IR;
  267. FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  268. FP_UNPACK_RAW_SP(SB, val);
  269. FP_CMP_S(IR, SA, SB, 3);
  270. /*
  271. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  272. * IR == 1 if DA > DB and IR == 3 if unorderded
  273. */
  274. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  275. return 0;
  276. }
  277. /* Compare and signal long double */
  278. static int emu_kxbr (struct pt_regs *regs, int rx, int ry) {
  279. FP_DECL_Q(QA); FP_DECL_Q(QB);
  280. FP_DECL_EX;
  281. mathemu_ldcv cvt;
  282. int IR;
  283. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  284. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  285. FP_UNPACK_RAW_QP(QA, &cvt.ld);
  286. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  287. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  288. FP_UNPACK_QP(QB, &cvt.ld);
  289. FP_CMP_Q(IR, QA, QB, 3);
  290. /*
  291. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  292. * IR == 1 if DA > DB and IR == 3 if unorderded
  293. */
  294. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  295. if (IR == 3)
  296. FP_SET_EXCEPTION (FP_EX_INVALID);
  297. return _fex;
  298. }
  299. /* Compare and signal double */
  300. static int emu_kdbr (struct pt_regs *regs, int rx, int ry) {
  301. FP_DECL_D(DA); FP_DECL_D(DB);
  302. FP_DECL_EX;
  303. int IR;
  304. FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  305. FP_UNPACK_RAW_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  306. FP_CMP_D(IR, DA, DB, 3);
  307. /*
  308. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  309. * IR == 1 if DA > DB and IR == 3 if unorderded
  310. */
  311. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  312. if (IR == 3)
  313. FP_SET_EXCEPTION (FP_EX_INVALID);
  314. return _fex;
  315. }
  316. /* Compare and signal double */
  317. static int emu_kdb (struct pt_regs *regs, int rx, double *val) {
  318. FP_DECL_D(DA); FP_DECL_D(DB);
  319. FP_DECL_EX;
  320. int IR;
  321. FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  322. FP_UNPACK_RAW_DP(DB, val);
  323. FP_CMP_D(IR, DA, DB, 3);
  324. /*
  325. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  326. * IR == 1 if DA > DB and IR == 3 if unorderded
  327. */
  328. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  329. if (IR == 3)
  330. FP_SET_EXCEPTION (FP_EX_INVALID);
  331. return _fex;
  332. }
  333. /* Compare and signal float */
  334. static int emu_kebr (struct pt_regs *regs, int rx, int ry) {
  335. FP_DECL_S(SA); FP_DECL_S(SB);
  336. FP_DECL_EX;
  337. int IR;
  338. FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  339. FP_UNPACK_RAW_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  340. FP_CMP_S(IR, SA, SB, 3);
  341. /*
  342. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  343. * IR == 1 if DA > DB and IR == 3 if unorderded
  344. */
  345. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  346. if (IR == 3)
  347. FP_SET_EXCEPTION (FP_EX_INVALID);
  348. return _fex;
  349. }
  350. /* Compare and signal float */
  351. static int emu_keb (struct pt_regs *regs, int rx, float *val) {
  352. FP_DECL_S(SA); FP_DECL_S(SB);
  353. FP_DECL_EX;
  354. int IR;
  355. FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  356. FP_UNPACK_RAW_SP(SB, val);
  357. FP_CMP_S(IR, SA, SB, 3);
  358. /*
  359. * IR == -1 if DA < DB, IR == 0 if DA == DB,
  360. * IR == 1 if DA > DB and IR == 3 if unorderded
  361. */
  362. emu_set_CC(regs, (IR == -1) ? 1 : (IR == 1) ? 2 : IR);
  363. if (IR == 3)
  364. FP_SET_EXCEPTION (FP_EX_INVALID);
  365. return _fex;
  366. }
  367. /* Convert from fixed long double */
  368. static int emu_cxfbr (struct pt_regs *regs, int rx, int ry) {
  369. FP_DECL_Q(QR);
  370. FP_DECL_EX;
  371. mathemu_ldcv cvt;
  372. __s32 si;
  373. int mode;
  374. mode = current->thread.fp_regs.fpc & 3;
  375. si = regs->gprs[ry];
  376. FP_FROM_INT_Q(QR, si, 32, int);
  377. FP_PACK_QP(&cvt.ld, QR);
  378. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  379. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  380. return _fex;
  381. }
  382. /* Convert from fixed double */
  383. static int emu_cdfbr (struct pt_regs *regs, int rx, int ry) {
  384. FP_DECL_D(DR);
  385. FP_DECL_EX;
  386. __s32 si;
  387. int mode;
  388. mode = current->thread.fp_regs.fpc & 3;
  389. si = regs->gprs[ry];
  390. FP_FROM_INT_D(DR, si, 32, int);
  391. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  392. return _fex;
  393. }
  394. /* Convert from fixed float */
  395. static int emu_cefbr (struct pt_regs *regs, int rx, int ry) {
  396. FP_DECL_S(SR);
  397. FP_DECL_EX;
  398. __s32 si;
  399. int mode;
  400. mode = current->thread.fp_regs.fpc & 3;
  401. si = regs->gprs[ry];
  402. FP_FROM_INT_S(SR, si, 32, int);
  403. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  404. return _fex;
  405. }
  406. /* Convert to fixed long double */
  407. static int emu_cfxbr (struct pt_regs *regs, int rx, int ry, int mask) {
  408. FP_DECL_Q(QA);
  409. FP_DECL_EX;
  410. mathemu_ldcv cvt;
  411. __s32 si;
  412. int mode;
  413. if (mask == 0)
  414. mode = current->thread.fp_regs.fpc & 3;
  415. else if (mask == 1)
  416. mode = FP_RND_NEAREST;
  417. else
  418. mode = mask - 4;
  419. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  420. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  421. FP_UNPACK_QP(QA, &cvt.ld);
  422. FP_TO_INT_ROUND_Q(si, QA, 32, 1);
  423. regs->gprs[rx] = si;
  424. emu_set_CC_cs(regs, QA_c, QA_s);
  425. return _fex;
  426. }
  427. /* Convert to fixed double */
  428. static int emu_cfdbr (struct pt_regs *regs, int rx, int ry, int mask) {
  429. FP_DECL_D(DA);
  430. FP_DECL_EX;
  431. __s32 si;
  432. int mode;
  433. if (mask == 0)
  434. mode = current->thread.fp_regs.fpc & 3;
  435. else if (mask == 1)
  436. mode = FP_RND_NEAREST;
  437. else
  438. mode = mask - 4;
  439. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  440. FP_TO_INT_ROUND_D(si, DA, 32, 1);
  441. regs->gprs[rx] = si;
  442. emu_set_CC_cs(regs, DA_c, DA_s);
  443. return _fex;
  444. }
  445. /* Convert to fixed float */
  446. static int emu_cfebr (struct pt_regs *regs, int rx, int ry, int mask) {
  447. FP_DECL_S(SA);
  448. FP_DECL_EX;
  449. __s32 si;
  450. int mode;
  451. if (mask == 0)
  452. mode = current->thread.fp_regs.fpc & 3;
  453. else if (mask == 1)
  454. mode = FP_RND_NEAREST;
  455. else
  456. mode = mask - 4;
  457. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  458. FP_TO_INT_ROUND_S(si, SA, 32, 1);
  459. regs->gprs[rx] = si;
  460. emu_set_CC_cs(regs, SA_c, SA_s);
  461. return _fex;
  462. }
  463. /* Divide long double */
  464. static int emu_dxbr (struct pt_regs *regs, int rx, int ry) {
  465. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  466. FP_DECL_EX;
  467. mathemu_ldcv cvt;
  468. int mode;
  469. mode = current->thread.fp_regs.fpc & 3;
  470. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  471. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  472. FP_UNPACK_QP(QA, &cvt.ld);
  473. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  474. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  475. FP_UNPACK_QP(QB, &cvt.ld);
  476. FP_DIV_Q(QR, QA, QB);
  477. FP_PACK_QP(&cvt.ld, QR);
  478. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  479. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  480. return _fex;
  481. }
  482. /* Divide double */
  483. static int emu_ddbr (struct pt_regs *regs, int rx, int ry) {
  484. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  485. FP_DECL_EX;
  486. int mode;
  487. mode = current->thread.fp_regs.fpc & 3;
  488. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  489. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  490. FP_DIV_D(DR, DA, DB);
  491. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  492. return _fex;
  493. }
  494. /* Divide double */
  495. static int emu_ddb (struct pt_regs *regs, int rx, double *val) {
  496. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  497. FP_DECL_EX;
  498. int mode;
  499. mode = current->thread.fp_regs.fpc & 3;
  500. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  501. FP_UNPACK_DP(DB, val);
  502. FP_DIV_D(DR, DA, DB);
  503. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  504. return _fex;
  505. }
  506. /* Divide float */
  507. static int emu_debr (struct pt_regs *regs, int rx, int ry) {
  508. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  509. FP_DECL_EX;
  510. int mode;
  511. mode = current->thread.fp_regs.fpc & 3;
  512. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  513. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  514. FP_DIV_S(SR, SA, SB);
  515. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  516. return _fex;
  517. }
  518. /* Divide float */
  519. static int emu_deb (struct pt_regs *regs, int rx, float *val) {
  520. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  521. FP_DECL_EX;
  522. int mode;
  523. mode = current->thread.fp_regs.fpc & 3;
  524. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  525. FP_UNPACK_SP(SB, val);
  526. FP_DIV_S(SR, SA, SB);
  527. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  528. return _fex;
  529. }
  530. /* Divide to integer double */
  531. static int emu_didbr (struct pt_regs *regs, int rx, int ry, int mask) {
  532. display_emulation_not_implemented(regs, "didbr");
  533. return 0;
  534. }
  535. /* Divide to integer float */
  536. static int emu_diebr (struct pt_regs *regs, int rx, int ry, int mask) {
  537. display_emulation_not_implemented(regs, "diebr");
  538. return 0;
  539. }
  540. /* Extract fpc */
  541. static int emu_efpc (struct pt_regs *regs, int rx, int ry) {
  542. regs->gprs[rx] = current->thread.fp_regs.fpc;
  543. return 0;
  544. }
  545. /* Load and test long double */
  546. static int emu_ltxbr (struct pt_regs *regs, int rx, int ry) {
  547. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  548. mathemu_ldcv cvt;
  549. FP_DECL_Q(QA);
  550. FP_DECL_EX;
  551. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  552. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  553. FP_UNPACK_QP(QA, &cvt.ld);
  554. fp_regs->fprs[rx].ui = fp_regs->fprs[ry].ui;
  555. fp_regs->fprs[rx+2].ui = fp_regs->fprs[ry+2].ui;
  556. emu_set_CC_cs(regs, QA_c, QA_s);
  557. return _fex;
  558. }
  559. /* Load and test double */
  560. static int emu_ltdbr (struct pt_regs *regs, int rx, int ry) {
  561. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  562. FP_DECL_D(DA);
  563. FP_DECL_EX;
  564. FP_UNPACK_DP(DA, &fp_regs->fprs[ry].d);
  565. fp_regs->fprs[rx].ui = fp_regs->fprs[ry].ui;
  566. emu_set_CC_cs(regs, DA_c, DA_s);
  567. return _fex;
  568. }
  569. /* Load and test double */
  570. static int emu_ltebr (struct pt_regs *regs, int rx, int ry) {
  571. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  572. FP_DECL_S(SA);
  573. FP_DECL_EX;
  574. FP_UNPACK_SP(SA, &fp_regs->fprs[ry].f);
  575. fp_regs->fprs[rx].ui = fp_regs->fprs[ry].ui;
  576. emu_set_CC_cs(regs, SA_c, SA_s);
  577. return _fex;
  578. }
  579. /* Load complement long double */
  580. static int emu_lcxbr (struct pt_regs *regs, int rx, int ry) {
  581. FP_DECL_Q(QA); FP_DECL_Q(QR);
  582. FP_DECL_EX;
  583. mathemu_ldcv cvt;
  584. int mode;
  585. mode = current->thread.fp_regs.fpc & 3;
  586. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  587. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  588. FP_UNPACK_QP(QA, &cvt.ld);
  589. FP_NEG_Q(QR, QA);
  590. FP_PACK_QP(&cvt.ld, QR);
  591. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  592. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  593. emu_set_CC_cs(regs, QR_c, QR_s);
  594. return _fex;
  595. }
  596. /* Load complement double */
  597. static int emu_lcdbr (struct pt_regs *regs, int rx, int ry) {
  598. FP_DECL_D(DA); FP_DECL_D(DR);
  599. FP_DECL_EX;
  600. int mode;
  601. mode = current->thread.fp_regs.fpc & 3;
  602. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  603. FP_NEG_D(DR, DA);
  604. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  605. emu_set_CC_cs(regs, DR_c, DR_s);
  606. return _fex;
  607. }
  608. /* Load complement float */
  609. static int emu_lcebr (struct pt_regs *regs, int rx, int ry) {
  610. FP_DECL_S(SA); FP_DECL_S(SR);
  611. FP_DECL_EX;
  612. int mode;
  613. mode = current->thread.fp_regs.fpc & 3;
  614. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  615. FP_NEG_S(SR, SA);
  616. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  617. emu_set_CC_cs(regs, SR_c, SR_s);
  618. return _fex;
  619. }
  620. /* Load floating point integer long double */
  621. static int emu_fixbr (struct pt_regs *regs, int rx, int ry, int mask) {
  622. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  623. FP_DECL_Q(QA);
  624. FP_DECL_EX;
  625. mathemu_ldcv cvt;
  626. __s32 si;
  627. int mode;
  628. if (mask == 0)
  629. mode = fp_regs->fpc & 3;
  630. else if (mask == 1)
  631. mode = FP_RND_NEAREST;
  632. else
  633. mode = mask - 4;
  634. cvt.w.high = fp_regs->fprs[ry].ui;
  635. cvt.w.low = fp_regs->fprs[ry+2].ui;
  636. FP_UNPACK_QP(QA, &cvt.ld);
  637. FP_TO_FPINT_ROUND_Q(QA);
  638. FP_PACK_QP(&cvt.ld, QA);
  639. fp_regs->fprs[rx].ui = cvt.w.high;
  640. fp_regs->fprs[rx+2].ui = cvt.w.low;
  641. return _fex;
  642. }
  643. /* Load floating point integer double */
  644. static int emu_fidbr (struct pt_regs *regs, int rx, int ry, int mask) {
  645. /* FIXME: rounding mode !! */
  646. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  647. FP_DECL_D(DA);
  648. FP_DECL_EX;
  649. __s32 si;
  650. int mode;
  651. if (mask == 0)
  652. mode = fp_regs->fpc & 3;
  653. else if (mask == 1)
  654. mode = FP_RND_NEAREST;
  655. else
  656. mode = mask - 4;
  657. FP_UNPACK_DP(DA, &fp_regs->fprs[ry].d);
  658. FP_TO_FPINT_ROUND_D(DA);
  659. FP_PACK_DP(&fp_regs->fprs[rx].d, DA);
  660. return _fex;
  661. }
  662. /* Load floating point integer float */
  663. static int emu_fiebr (struct pt_regs *regs, int rx, int ry, int mask) {
  664. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  665. FP_DECL_S(SA);
  666. FP_DECL_EX;
  667. __s32 si;
  668. int mode;
  669. if (mask == 0)
  670. mode = fp_regs->fpc & 3;
  671. else if (mask == 1)
  672. mode = FP_RND_NEAREST;
  673. else
  674. mode = mask - 4;
  675. FP_UNPACK_SP(SA, &fp_regs->fprs[ry].f);
  676. FP_TO_FPINT_ROUND_S(SA);
  677. FP_PACK_SP(&fp_regs->fprs[rx].f, SA);
  678. return _fex;
  679. }
  680. /* Load lengthened double to long double */
  681. static int emu_lxdbr (struct pt_regs *regs, int rx, int ry) {
  682. FP_DECL_D(DA); FP_DECL_Q(QR);
  683. FP_DECL_EX;
  684. mathemu_ldcv cvt;
  685. int mode;
  686. mode = current->thread.fp_regs.fpc & 3;
  687. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  688. FP_CONV (Q, D, 4, 2, QR, DA);
  689. FP_PACK_QP(&cvt.ld, QR);
  690. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  691. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  692. return _fex;
  693. }
  694. /* Load lengthened double to long double */
  695. static int emu_lxdb (struct pt_regs *regs, int rx, double *val) {
  696. FP_DECL_D(DA); FP_DECL_Q(QR);
  697. FP_DECL_EX;
  698. mathemu_ldcv cvt;
  699. int mode;
  700. mode = current->thread.fp_regs.fpc & 3;
  701. FP_UNPACK_DP(DA, val);
  702. FP_CONV (Q, D, 4, 2, QR, DA);
  703. FP_PACK_QP(&cvt.ld, QR);
  704. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  705. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  706. return _fex;
  707. }
  708. /* Load lengthened float to long double */
  709. static int emu_lxebr (struct pt_regs *regs, int rx, int ry) {
  710. FP_DECL_S(SA); FP_DECL_Q(QR);
  711. FP_DECL_EX;
  712. mathemu_ldcv cvt;
  713. int mode;
  714. mode = current->thread.fp_regs.fpc & 3;
  715. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  716. FP_CONV (Q, S, 4, 1, QR, SA);
  717. FP_PACK_QP(&cvt.ld, QR);
  718. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  719. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  720. return _fex;
  721. }
  722. /* Load lengthened float to long double */
  723. static int emu_lxeb (struct pt_regs *regs, int rx, float *val) {
  724. FP_DECL_S(SA); FP_DECL_Q(QR);
  725. FP_DECL_EX;
  726. mathemu_ldcv cvt;
  727. int mode;
  728. mode = current->thread.fp_regs.fpc & 3;
  729. FP_UNPACK_SP(SA, val);
  730. FP_CONV (Q, S, 4, 1, QR, SA);
  731. FP_PACK_QP(&cvt.ld, QR);
  732. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  733. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  734. return _fex;
  735. }
  736. /* Load lengthened float to double */
  737. static int emu_ldebr (struct pt_regs *regs, int rx, int ry) {
  738. FP_DECL_S(SA); FP_DECL_D(DR);
  739. FP_DECL_EX;
  740. int mode;
  741. mode = current->thread.fp_regs.fpc & 3;
  742. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  743. FP_CONV (D, S, 2, 1, DR, SA);
  744. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  745. return _fex;
  746. }
  747. /* Load lengthened float to double */
  748. static int emu_ldeb (struct pt_regs *regs, int rx, float *val) {
  749. FP_DECL_S(SA); FP_DECL_D(DR);
  750. FP_DECL_EX;
  751. int mode;
  752. mode = current->thread.fp_regs.fpc & 3;
  753. FP_UNPACK_SP(SA, val);
  754. FP_CONV (D, S, 2, 1, DR, SA);
  755. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  756. return _fex;
  757. }
  758. /* Load negative long double */
  759. static int emu_lnxbr (struct pt_regs *regs, int rx, int ry) {
  760. FP_DECL_Q(QA); FP_DECL_Q(QR);
  761. FP_DECL_EX;
  762. mathemu_ldcv cvt;
  763. int mode;
  764. mode = current->thread.fp_regs.fpc & 3;
  765. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  766. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  767. FP_UNPACK_QP(QA, &cvt.ld);
  768. if (QA_s == 0) {
  769. FP_NEG_Q(QR, QA);
  770. FP_PACK_QP(&cvt.ld, QR);
  771. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  772. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  773. } else {
  774. current->thread.fp_regs.fprs[rx].ui =
  775. current->thread.fp_regs.fprs[ry].ui;
  776. current->thread.fp_regs.fprs[rx+2].ui =
  777. current->thread.fp_regs.fprs[ry+2].ui;
  778. }
  779. emu_set_CC_cs(regs, QR_c, QR_s);
  780. return _fex;
  781. }
  782. /* Load negative double */
  783. static int emu_lndbr (struct pt_regs *regs, int rx, int ry) {
  784. FP_DECL_D(DA); FP_DECL_D(DR);
  785. FP_DECL_EX;
  786. int mode;
  787. mode = current->thread.fp_regs.fpc & 3;
  788. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  789. if (DA_s == 0) {
  790. FP_NEG_D(DR, DA);
  791. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  792. } else
  793. current->thread.fp_regs.fprs[rx].ui =
  794. current->thread.fp_regs.fprs[ry].ui;
  795. emu_set_CC_cs(regs, DR_c, DR_s);
  796. return _fex;
  797. }
  798. /* Load negative float */
  799. static int emu_lnebr (struct pt_regs *regs, int rx, int ry) {
  800. FP_DECL_S(SA); FP_DECL_S(SR);
  801. FP_DECL_EX;
  802. int mode;
  803. mode = current->thread.fp_regs.fpc & 3;
  804. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  805. if (SA_s == 0) {
  806. FP_NEG_S(SR, SA);
  807. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  808. } else
  809. current->thread.fp_regs.fprs[rx].ui =
  810. current->thread.fp_regs.fprs[ry].ui;
  811. emu_set_CC_cs(regs, SR_c, SR_s);
  812. return _fex;
  813. }
  814. /* Load positive long double */
  815. static int emu_lpxbr (struct pt_regs *regs, int rx, int ry) {
  816. FP_DECL_Q(QA); FP_DECL_Q(QR);
  817. FP_DECL_EX;
  818. mathemu_ldcv cvt;
  819. int mode;
  820. mode = current->thread.fp_regs.fpc & 3;
  821. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  822. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  823. FP_UNPACK_QP(QA, &cvt.ld);
  824. if (QA_s != 0) {
  825. FP_NEG_Q(QR, QA);
  826. FP_PACK_QP(&cvt.ld, QR);
  827. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  828. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  829. } else{
  830. current->thread.fp_regs.fprs[rx].ui =
  831. current->thread.fp_regs.fprs[ry].ui;
  832. current->thread.fp_regs.fprs[rx+2].ui =
  833. current->thread.fp_regs.fprs[ry+2].ui;
  834. }
  835. emu_set_CC_cs(regs, QR_c, QR_s);
  836. return _fex;
  837. }
  838. /* Load positive double */
  839. static int emu_lpdbr (struct pt_regs *regs, int rx, int ry) {
  840. FP_DECL_D(DA); FP_DECL_D(DR);
  841. FP_DECL_EX;
  842. int mode;
  843. mode = current->thread.fp_regs.fpc & 3;
  844. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  845. if (DA_s != 0) {
  846. FP_NEG_D(DR, DA);
  847. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  848. } else
  849. current->thread.fp_regs.fprs[rx].ui =
  850. current->thread.fp_regs.fprs[ry].ui;
  851. emu_set_CC_cs(regs, DR_c, DR_s);
  852. return _fex;
  853. }
  854. /* Load positive float */
  855. static int emu_lpebr (struct pt_regs *regs, int rx, int ry) {
  856. FP_DECL_S(SA); FP_DECL_S(SR);
  857. FP_DECL_EX;
  858. int mode;
  859. mode = current->thread.fp_regs.fpc & 3;
  860. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  861. if (SA_s != 0) {
  862. FP_NEG_S(SR, SA);
  863. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  864. } else
  865. current->thread.fp_regs.fprs[rx].ui =
  866. current->thread.fp_regs.fprs[ry].ui;
  867. emu_set_CC_cs(regs, SR_c, SR_s);
  868. return _fex;
  869. }
  870. /* Load rounded long double to double */
  871. static int emu_ldxbr (struct pt_regs *regs, int rx, int ry) {
  872. FP_DECL_Q(QA); FP_DECL_D(DR);
  873. FP_DECL_EX;
  874. mathemu_ldcv cvt;
  875. int mode;
  876. mode = current->thread.fp_regs.fpc & 3;
  877. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  878. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  879. FP_UNPACK_QP(QA, &cvt.ld);
  880. FP_CONV (D, Q, 2, 4, DR, QA);
  881. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].f, DR);
  882. return _fex;
  883. }
  884. /* Load rounded long double to float */
  885. static int emu_lexbr (struct pt_regs *regs, int rx, int ry) {
  886. FP_DECL_Q(QA); FP_DECL_S(SR);
  887. FP_DECL_EX;
  888. mathemu_ldcv cvt;
  889. int mode;
  890. mode = current->thread.fp_regs.fpc & 3;
  891. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  892. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  893. FP_UNPACK_QP(QA, &cvt.ld);
  894. FP_CONV (S, Q, 1, 4, SR, QA);
  895. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  896. return _fex;
  897. }
  898. /* Load rounded double to float */
  899. static int emu_ledbr (struct pt_regs *regs, int rx, int ry) {
  900. FP_DECL_D(DA); FP_DECL_S(SR);
  901. FP_DECL_EX;
  902. int mode;
  903. mode = current->thread.fp_regs.fpc & 3;
  904. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  905. FP_CONV (S, D, 1, 2, SR, DA);
  906. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  907. return _fex;
  908. }
  909. /* Multiply long double */
  910. static int emu_mxbr (struct pt_regs *regs, int rx, int ry) {
  911. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  912. FP_DECL_EX;
  913. mathemu_ldcv cvt;
  914. int mode;
  915. mode = current->thread.fp_regs.fpc & 3;
  916. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  917. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  918. FP_UNPACK_QP(QA, &cvt.ld);
  919. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  920. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  921. FP_UNPACK_QP(QB, &cvt.ld);
  922. FP_MUL_Q(QR, QA, QB);
  923. FP_PACK_QP(&cvt.ld, QR);
  924. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  925. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  926. return _fex;
  927. }
  928. /* Multiply double */
  929. static int emu_mdbr (struct pt_regs *regs, int rx, int ry) {
  930. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  931. FP_DECL_EX;
  932. int mode;
  933. mode = current->thread.fp_regs.fpc & 3;
  934. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  935. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  936. FP_MUL_D(DR, DA, DB);
  937. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  938. return _fex;
  939. }
  940. /* Multiply double */
  941. static int emu_mdb (struct pt_regs *regs, int rx, double *val) {
  942. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  943. FP_DECL_EX;
  944. int mode;
  945. mode = current->thread.fp_regs.fpc & 3;
  946. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  947. FP_UNPACK_DP(DB, val);
  948. FP_MUL_D(DR, DA, DB);
  949. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  950. return _fex;
  951. }
  952. /* Multiply double to long double */
  953. static int emu_mxdbr (struct pt_regs *regs, int rx, int ry) {
  954. FP_DECL_D(DA); FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  955. FP_DECL_EX;
  956. mathemu_ldcv cvt;
  957. int mode;
  958. mode = current->thread.fp_regs.fpc & 3;
  959. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  960. FP_CONV (Q, D, 4, 2, QA, DA);
  961. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  962. FP_CONV (Q, D, 4, 2, QB, DA);
  963. FP_MUL_Q(QR, QA, QB);
  964. FP_PACK_QP(&cvt.ld, QR);
  965. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  966. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  967. return _fex;
  968. }
  969. /* Multiply double to long double */
  970. static int emu_mxdb (struct pt_regs *regs, int rx, long double *val) {
  971. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  972. FP_DECL_EX;
  973. mathemu_ldcv cvt;
  974. int mode;
  975. mode = current->thread.fp_regs.fpc & 3;
  976. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  977. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  978. FP_UNPACK_QP(QA, &cvt.ld);
  979. FP_UNPACK_QP(QB, val);
  980. FP_MUL_Q(QR, QA, QB);
  981. FP_PACK_QP(&cvt.ld, QR);
  982. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  983. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  984. return _fex;
  985. }
  986. /* Multiply float */
  987. static int emu_meebr (struct pt_regs *regs, int rx, int ry) {
  988. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  989. FP_DECL_EX;
  990. int mode;
  991. mode = current->thread.fp_regs.fpc & 3;
  992. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  993. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  994. FP_MUL_S(SR, SA, SB);
  995. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  996. return _fex;
  997. }
  998. /* Multiply float */
  999. static int emu_meeb (struct pt_regs *regs, int rx, float *val) {
  1000. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  1001. FP_DECL_EX;
  1002. int mode;
  1003. mode = current->thread.fp_regs.fpc & 3;
  1004. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1005. FP_UNPACK_SP(SB, val);
  1006. FP_MUL_S(SR, SA, SB);
  1007. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  1008. return _fex;
  1009. }
  1010. /* Multiply float to double */
  1011. static int emu_mdebr (struct pt_regs *regs, int rx, int ry) {
  1012. FP_DECL_S(SA); FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  1013. FP_DECL_EX;
  1014. int mode;
  1015. mode = current->thread.fp_regs.fpc & 3;
  1016. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1017. FP_CONV (D, S, 2, 1, DA, SA);
  1018. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  1019. FP_CONV (D, S, 2, 1, DB, SA);
  1020. FP_MUL_D(DR, DA, DB);
  1021. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1022. return _fex;
  1023. }
  1024. /* Multiply float to double */
  1025. static int emu_mdeb (struct pt_regs *regs, int rx, float *val) {
  1026. FP_DECL_S(SA); FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  1027. FP_DECL_EX;
  1028. int mode;
  1029. mode = current->thread.fp_regs.fpc & 3;
  1030. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1031. FP_CONV (D, S, 2, 1, DA, SA);
  1032. FP_UNPACK_SP(SA, val);
  1033. FP_CONV (D, S, 2, 1, DB, SA);
  1034. FP_MUL_D(DR, DA, DB);
  1035. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1036. return _fex;
  1037. }
  1038. /* Multiply and add double */
  1039. static int emu_madbr (struct pt_regs *regs, int rx, int ry, int rz) {
  1040. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);
  1041. FP_DECL_EX;
  1042. int mode;
  1043. mode = current->thread.fp_regs.fpc & 3;
  1044. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1045. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  1046. FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);
  1047. FP_MUL_D(DR, DA, DB);
  1048. FP_ADD_D(DR, DR, DC);
  1049. FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);
  1050. return _fex;
  1051. }
  1052. /* Multiply and add double */
  1053. static int emu_madb (struct pt_regs *regs, int rx, double *val, int rz) {
  1054. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);
  1055. FP_DECL_EX;
  1056. int mode;
  1057. mode = current->thread.fp_regs.fpc & 3;
  1058. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1059. FP_UNPACK_DP(DB, val);
  1060. FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);
  1061. FP_MUL_D(DR, DA, DB);
  1062. FP_ADD_D(DR, DR, DC);
  1063. FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);
  1064. return _fex;
  1065. }
  1066. /* Multiply and add float */
  1067. static int emu_maebr (struct pt_regs *regs, int rx, int ry, int rz) {
  1068. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);
  1069. FP_DECL_EX;
  1070. int mode;
  1071. mode = current->thread.fp_regs.fpc & 3;
  1072. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1073. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  1074. FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);
  1075. FP_MUL_S(SR, SA, SB);
  1076. FP_ADD_S(SR, SR, SC);
  1077. FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);
  1078. return _fex;
  1079. }
  1080. /* Multiply and add float */
  1081. static int emu_maeb (struct pt_regs *regs, int rx, float *val, int rz) {
  1082. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);
  1083. FP_DECL_EX;
  1084. int mode;
  1085. mode = current->thread.fp_regs.fpc & 3;
  1086. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1087. FP_UNPACK_SP(SB, val);
  1088. FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);
  1089. FP_MUL_S(SR, SA, SB);
  1090. FP_ADD_S(SR, SR, SC);
  1091. FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);
  1092. return _fex;
  1093. }
  1094. /* Multiply and subtract double */
  1095. static int emu_msdbr (struct pt_regs *regs, int rx, int ry, int rz) {
  1096. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);
  1097. FP_DECL_EX;
  1098. int mode;
  1099. mode = current->thread.fp_regs.fpc & 3;
  1100. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1101. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  1102. FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);
  1103. FP_MUL_D(DR, DA, DB);
  1104. FP_SUB_D(DR, DR, DC);
  1105. FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);
  1106. return _fex;
  1107. }
  1108. /* Multiply and subtract double */
  1109. static int emu_msdb (struct pt_regs *regs, int rx, double *val, int rz) {
  1110. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DC); FP_DECL_D(DR);
  1111. FP_DECL_EX;
  1112. int mode;
  1113. mode = current->thread.fp_regs.fpc & 3;
  1114. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1115. FP_UNPACK_DP(DB, val);
  1116. FP_UNPACK_DP(DC, &current->thread.fp_regs.fprs[rz].d);
  1117. FP_MUL_D(DR, DA, DB);
  1118. FP_SUB_D(DR, DR, DC);
  1119. FP_PACK_DP(&current->thread.fp_regs.fprs[rz].d, DR);
  1120. return _fex;
  1121. }
  1122. /* Multiply and subtract float */
  1123. static int emu_msebr (struct pt_regs *regs, int rx, int ry, int rz) {
  1124. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);
  1125. FP_DECL_EX;
  1126. int mode;
  1127. mode = current->thread.fp_regs.fpc & 3;
  1128. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1129. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  1130. FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);
  1131. FP_MUL_S(SR, SA, SB);
  1132. FP_SUB_S(SR, SR, SC);
  1133. FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);
  1134. return _fex;
  1135. }
  1136. /* Multiply and subtract float */
  1137. static int emu_mseb (struct pt_regs *regs, int rx, float *val, int rz) {
  1138. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SC); FP_DECL_S(SR);
  1139. FP_DECL_EX;
  1140. int mode;
  1141. mode = current->thread.fp_regs.fpc & 3;
  1142. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1143. FP_UNPACK_SP(SB, val);
  1144. FP_UNPACK_SP(SC, &current->thread.fp_regs.fprs[rz].f);
  1145. FP_MUL_S(SR, SA, SB);
  1146. FP_SUB_S(SR, SR, SC);
  1147. FP_PACK_SP(&current->thread.fp_regs.fprs[rz].f, SR);
  1148. return _fex;
  1149. }
  1150. /* Set floating point control word */
  1151. static int emu_sfpc (struct pt_regs *regs, int rx, int ry) {
  1152. __u32 temp;
  1153. temp = regs->gprs[rx];
  1154. if ((temp & ~FPC_VALID_MASK) != 0)
  1155. return SIGILL;
  1156. current->thread.fp_regs.fpc = temp;
  1157. return 0;
  1158. }
  1159. /* Square root long double */
  1160. static int emu_sqxbr (struct pt_regs *regs, int rx, int ry) {
  1161. FP_DECL_Q(QA); FP_DECL_Q(QR);
  1162. FP_DECL_EX;
  1163. mathemu_ldcv cvt;
  1164. int mode;
  1165. mode = current->thread.fp_regs.fpc & 3;
  1166. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  1167. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  1168. FP_UNPACK_QP(QA, &cvt.ld);
  1169. FP_SQRT_Q(QR, QA);
  1170. FP_PACK_QP(&cvt.ld, QR);
  1171. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  1172. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  1173. emu_set_CC_cs(regs, QR_c, QR_s);
  1174. return _fex;
  1175. }
  1176. /* Square root double */
  1177. static int emu_sqdbr (struct pt_regs *regs, int rx, int ry) {
  1178. FP_DECL_D(DA); FP_DECL_D(DR);
  1179. FP_DECL_EX;
  1180. int mode;
  1181. mode = current->thread.fp_regs.fpc & 3;
  1182. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[ry].d);
  1183. FP_SQRT_D(DR, DA);
  1184. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1185. emu_set_CC_cs(regs, DR_c, DR_s);
  1186. return _fex;
  1187. }
  1188. /* Square root double */
  1189. static int emu_sqdb (struct pt_regs *regs, int rx, double *val) {
  1190. FP_DECL_D(DA); FP_DECL_D(DR);
  1191. FP_DECL_EX;
  1192. int mode;
  1193. mode = current->thread.fp_regs.fpc & 3;
  1194. FP_UNPACK_DP(DA, val);
  1195. FP_SQRT_D(DR, DA);
  1196. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1197. emu_set_CC_cs(regs, DR_c, DR_s);
  1198. return _fex;
  1199. }
  1200. /* Square root float */
  1201. static int emu_sqebr (struct pt_regs *regs, int rx, int ry) {
  1202. FP_DECL_S(SA); FP_DECL_S(SR);
  1203. FP_DECL_EX;
  1204. int mode;
  1205. mode = current->thread.fp_regs.fpc & 3;
  1206. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[ry].f);
  1207. FP_SQRT_S(SR, SA);
  1208. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  1209. emu_set_CC_cs(regs, SR_c, SR_s);
  1210. return _fex;
  1211. }
  1212. /* Square root float */
  1213. static int emu_sqeb (struct pt_regs *regs, int rx, float *val) {
  1214. FP_DECL_S(SA); FP_DECL_S(SR);
  1215. FP_DECL_EX;
  1216. int mode;
  1217. mode = current->thread.fp_regs.fpc & 3;
  1218. FP_UNPACK_SP(SA, val);
  1219. FP_SQRT_S(SR, SA);
  1220. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  1221. emu_set_CC_cs(regs, SR_c, SR_s);
  1222. return _fex;
  1223. }
  1224. /* Subtract long double */
  1225. static int emu_sxbr (struct pt_regs *regs, int rx, int ry) {
  1226. FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
  1227. FP_DECL_EX;
  1228. mathemu_ldcv cvt;
  1229. int mode;
  1230. mode = current->thread.fp_regs.fpc & 3;
  1231. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  1232. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  1233. FP_UNPACK_QP(QA, &cvt.ld);
  1234. cvt.w.high = current->thread.fp_regs.fprs[ry].ui;
  1235. cvt.w.low = current->thread.fp_regs.fprs[ry+2].ui;
  1236. FP_UNPACK_QP(QB, &cvt.ld);
  1237. FP_SUB_Q(QR, QA, QB);
  1238. FP_PACK_QP(&cvt.ld, QR);
  1239. current->thread.fp_regs.fprs[rx].ui = cvt.w.high;
  1240. current->thread.fp_regs.fprs[rx+2].ui = cvt.w.low;
  1241. emu_set_CC_cs(regs, QR_c, QR_s);
  1242. return _fex;
  1243. }
  1244. /* Subtract double */
  1245. static int emu_sdbr (struct pt_regs *regs, int rx, int ry) {
  1246. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  1247. FP_DECL_EX;
  1248. int mode;
  1249. mode = current->thread.fp_regs.fpc & 3;
  1250. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1251. FP_UNPACK_DP(DB, &current->thread.fp_regs.fprs[ry].d);
  1252. FP_SUB_D(DR, DA, DB);
  1253. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1254. emu_set_CC_cs(regs, DR_c, DR_s);
  1255. return _fex;
  1256. }
  1257. /* Subtract double */
  1258. static int emu_sdb (struct pt_regs *regs, int rx, double *val) {
  1259. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  1260. FP_DECL_EX;
  1261. int mode;
  1262. mode = current->thread.fp_regs.fpc & 3;
  1263. FP_UNPACK_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1264. FP_UNPACK_DP(DB, val);
  1265. FP_SUB_D(DR, DA, DB);
  1266. FP_PACK_DP(&current->thread.fp_regs.fprs[rx].d, DR);
  1267. emu_set_CC_cs(regs, DR_c, DR_s);
  1268. return _fex;
  1269. }
  1270. /* Subtract float */
  1271. static int emu_sebr (struct pt_regs *regs, int rx, int ry) {
  1272. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  1273. FP_DECL_EX;
  1274. int mode;
  1275. mode = current->thread.fp_regs.fpc & 3;
  1276. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1277. FP_UNPACK_SP(SB, &current->thread.fp_regs.fprs[ry].f);
  1278. FP_SUB_S(SR, SA, SB);
  1279. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  1280. emu_set_CC_cs(regs, SR_c, SR_s);
  1281. return _fex;
  1282. }
  1283. /* Subtract float */
  1284. static int emu_seb (struct pt_regs *regs, int rx, float *val) {
  1285. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  1286. FP_DECL_EX;
  1287. int mode;
  1288. mode = current->thread.fp_regs.fpc & 3;
  1289. FP_UNPACK_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1290. FP_UNPACK_SP(SB, val);
  1291. FP_SUB_S(SR, SA, SB);
  1292. FP_PACK_SP(&current->thread.fp_regs.fprs[rx].f, SR);
  1293. emu_set_CC_cs(regs, SR_c, SR_s);
  1294. return _fex;
  1295. }
  1296. /* Test data class long double */
  1297. static int emu_tcxb (struct pt_regs *regs, int rx, long val) {
  1298. FP_DECL_Q(QA);
  1299. mathemu_ldcv cvt;
  1300. int bit;
  1301. cvt.w.high = current->thread.fp_regs.fprs[rx].ui;
  1302. cvt.w.low = current->thread.fp_regs.fprs[rx+2].ui;
  1303. FP_UNPACK_RAW_QP(QA, &cvt.ld);
  1304. switch (QA_e) {
  1305. default:
  1306. bit = 8; /* normalized number */
  1307. break;
  1308. case 0:
  1309. if (_FP_FRAC_ZEROP_4(QA))
  1310. bit = 10; /* zero */
  1311. else
  1312. bit = 6; /* denormalized number */
  1313. break;
  1314. case _FP_EXPMAX_Q:
  1315. if (_FP_FRAC_ZEROP_4(QA))
  1316. bit = 4; /* infinity */
  1317. else if (_FP_FRAC_HIGH_RAW_Q(QA) & _FP_QNANBIT_Q)
  1318. bit = 2; /* quiet NAN */
  1319. else
  1320. bit = 0; /* signaling NAN */
  1321. break;
  1322. }
  1323. if (!QA_s)
  1324. bit++;
  1325. emu_set_CC(regs, ((__u32) val >> bit) & 1);
  1326. return 0;
  1327. }
  1328. /* Test data class double */
  1329. static int emu_tcdb (struct pt_regs *regs, int rx, long val) {
  1330. FP_DECL_D(DA);
  1331. int bit;
  1332. FP_UNPACK_RAW_DP(DA, &current->thread.fp_regs.fprs[rx].d);
  1333. switch (DA_e) {
  1334. default:
  1335. bit = 8; /* normalized number */
  1336. break;
  1337. case 0:
  1338. if (_FP_FRAC_ZEROP_2(DA))
  1339. bit = 10; /* zero */
  1340. else
  1341. bit = 6; /* denormalized number */
  1342. break;
  1343. case _FP_EXPMAX_D:
  1344. if (_FP_FRAC_ZEROP_2(DA))
  1345. bit = 4; /* infinity */
  1346. else if (_FP_FRAC_HIGH_RAW_D(DA) & _FP_QNANBIT_D)
  1347. bit = 2; /* quiet NAN */
  1348. else
  1349. bit = 0; /* signaling NAN */
  1350. break;
  1351. }
  1352. if (!DA_s)
  1353. bit++;
  1354. emu_set_CC(regs, ((__u32) val >> bit) & 1);
  1355. return 0;
  1356. }
  1357. /* Test data class float */
  1358. static int emu_tceb (struct pt_regs *regs, int rx, long val) {
  1359. FP_DECL_S(SA);
  1360. int bit;
  1361. FP_UNPACK_RAW_SP(SA, &current->thread.fp_regs.fprs[rx].f);
  1362. switch (SA_e) {
  1363. default:
  1364. bit = 8; /* normalized number */
  1365. break;
  1366. case 0:
  1367. if (_FP_FRAC_ZEROP_1(SA))
  1368. bit = 10; /* zero */
  1369. else
  1370. bit = 6; /* denormalized number */
  1371. break;
  1372. case _FP_EXPMAX_S:
  1373. if (_FP_FRAC_ZEROP_1(SA))
  1374. bit = 4; /* infinity */
  1375. else if (_FP_FRAC_HIGH_RAW_S(SA) & _FP_QNANBIT_S)
  1376. bit = 2; /* quiet NAN */
  1377. else
  1378. bit = 0; /* signaling NAN */
  1379. break;
  1380. }
  1381. if (!SA_s)
  1382. bit++;
  1383. emu_set_CC(regs, ((__u32) val >> bit) & 1);
  1384. return 0;
  1385. }
  1386. static inline void emu_load_regd(int reg) {
  1387. if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
  1388. return;
  1389. asm volatile( /* load reg from fp_regs.fprs[reg] */
  1390. " bras 1,0f\n"
  1391. " ld 0,0(%1)\n"
  1392. "0: ex %0,0(1)"
  1393. : /* no output */
  1394. : "a" (reg<<4),"a" (&current->thread.fp_regs.fprs[reg].d)
  1395. : "1");
  1396. }
  1397. static inline void emu_load_rege(int reg) {
  1398. if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
  1399. return;
  1400. asm volatile( /* load reg from fp_regs.fprs[reg] */
  1401. " bras 1,0f\n"
  1402. " le 0,0(%1)\n"
  1403. "0: ex %0,0(1)"
  1404. : /* no output */
  1405. : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
  1406. : "1");
  1407. }
  1408. static inline void emu_store_regd(int reg) {
  1409. if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
  1410. return;
  1411. asm volatile( /* store reg to fp_regs.fprs[reg] */
  1412. " bras 1,0f\n"
  1413. " std 0,0(%1)\n"
  1414. "0: ex %0,0(1)"
  1415. : /* no output */
  1416. : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].d)
  1417. : "1");
  1418. }
  1419. static inline void emu_store_rege(int reg) {
  1420. if ((reg&9) != 0) /* test if reg in {0,2,4,6} */
  1421. return;
  1422. asm volatile( /* store reg to fp_regs.fprs[reg] */
  1423. " bras 1,0f\n"
  1424. " ste 0,0(%1)\n"
  1425. "0: ex %0,0(1)"
  1426. : /* no output */
  1427. : "a" (reg<<4), "a" (&current->thread.fp_regs.fprs[reg].f)
  1428. : "1");
  1429. }
  1430. int math_emu_b3(__u8 *opcode, struct pt_regs * regs) {
  1431. int _fex = 0;
  1432. static const __u8 format_table[256] = {
  1433. [0x00] = 0x03,[0x01] = 0x03,[0x02] = 0x03,[0x03] = 0x03,
  1434. [0x04] = 0x0f,[0x05] = 0x0d,[0x06] = 0x0e,[0x07] = 0x0d,
  1435. [0x08] = 0x03,[0x09] = 0x03,[0x0a] = 0x03,[0x0b] = 0x03,
  1436. [0x0c] = 0x0f,[0x0d] = 0x03,[0x0e] = 0x06,[0x0f] = 0x06,
  1437. [0x10] = 0x02,[0x11] = 0x02,[0x12] = 0x02,[0x13] = 0x02,
  1438. [0x14] = 0x03,[0x15] = 0x02,[0x16] = 0x01,[0x17] = 0x03,
  1439. [0x18] = 0x02,[0x19] = 0x02,[0x1a] = 0x02,[0x1b] = 0x02,
  1440. [0x1c] = 0x02,[0x1d] = 0x02,[0x1e] = 0x05,[0x1f] = 0x05,
  1441. [0x40] = 0x01,[0x41] = 0x01,[0x42] = 0x01,[0x43] = 0x01,
  1442. [0x44] = 0x12,[0x45] = 0x0d,[0x46] = 0x11,[0x47] = 0x04,
  1443. [0x48] = 0x01,[0x49] = 0x01,[0x4a] = 0x01,[0x4b] = 0x01,
  1444. [0x4c] = 0x01,[0x4d] = 0x01,[0x53] = 0x06,[0x57] = 0x06,
  1445. [0x5b] = 0x05,[0x5f] = 0x05,[0x84] = 0x13,[0x8c] = 0x13,
  1446. [0x94] = 0x09,[0x95] = 0x08,[0x96] = 0x07,[0x98] = 0x0c,
  1447. [0x99] = 0x0b,[0x9a] = 0x0a
  1448. };
  1449. static const void *jump_table[256]= {
  1450. [0x00] = emu_lpebr,[0x01] = emu_lnebr,[0x02] = emu_ltebr,
  1451. [0x03] = emu_lcebr,[0x04] = emu_ldebr,[0x05] = emu_lxdbr,
  1452. [0x06] = emu_lxebr,[0x07] = emu_mxdbr,[0x08] = emu_kebr,
  1453. [0x09] = emu_cebr, [0x0a] = emu_aebr, [0x0b] = emu_sebr,
  1454. [0x0c] = emu_mdebr,[0x0d] = emu_debr, [0x0e] = emu_maebr,
  1455. [0x0f] = emu_msebr,[0x10] = emu_lpdbr,[0x11] = emu_lndbr,
  1456. [0x12] = emu_ltdbr,[0x13] = emu_lcdbr,[0x14] = emu_sqebr,
  1457. [0x15] = emu_sqdbr,[0x16] = emu_sqxbr,[0x17] = emu_meebr,
  1458. [0x18] = emu_kdbr, [0x19] = emu_cdbr, [0x1a] = emu_adbr,
  1459. [0x1b] = emu_sdbr, [0x1c] = emu_mdbr, [0x1d] = emu_ddbr,
  1460. [0x1e] = emu_madbr,[0x1f] = emu_msdbr,[0x40] = emu_lpxbr,
  1461. [0x41] = emu_lnxbr,[0x42] = emu_ltxbr,[0x43] = emu_lcxbr,
  1462. [0x44] = emu_ledbr,[0x45] = emu_ldxbr,[0x46] = emu_lexbr,
  1463. [0x47] = emu_fixbr,[0x48] = emu_kxbr, [0x49] = emu_cxbr,
  1464. [0x4a] = emu_axbr, [0x4b] = emu_sxbr, [0x4c] = emu_mxbr,
  1465. [0x4d] = emu_dxbr, [0x53] = emu_diebr,[0x57] = emu_fiebr,
  1466. [0x5b] = emu_didbr,[0x5f] = emu_fidbr,[0x84] = emu_sfpc,
  1467. [0x8c] = emu_efpc, [0x94] = emu_cefbr,[0x95] = emu_cdfbr,
  1468. [0x96] = emu_cxfbr,[0x98] = emu_cfebr,[0x99] = emu_cfdbr,
  1469. [0x9a] = emu_cfxbr
  1470. };
  1471. switch (format_table[opcode[1]]) {
  1472. case 1: /* RRE format, long double operation */
  1473. if (opcode[3] & 0x22)
  1474. return SIGILL;
  1475. emu_store_regd((opcode[3] >> 4) & 15);
  1476. emu_store_regd(((opcode[3] >> 4) & 15) + 2);
  1477. emu_store_regd(opcode[3] & 15);
  1478. emu_store_regd((opcode[3] & 15) + 2);
  1479. /* call the emulation function */
  1480. _fex = ((int (*)(struct pt_regs *,int, int))
  1481. jump_table[opcode[1]])
  1482. (regs, opcode[3] >> 4, opcode[3] & 15);
  1483. emu_load_regd((opcode[3] >> 4) & 15);
  1484. emu_load_regd(((opcode[3] >> 4) & 15) + 2);
  1485. emu_load_regd(opcode[3] & 15);
  1486. emu_load_regd((opcode[3] & 15) + 2);
  1487. break;
  1488. case 2: /* RRE format, double operation */
  1489. emu_store_regd((opcode[3] >> 4) & 15);
  1490. emu_store_regd(opcode[3] & 15);
  1491. /* call the emulation function */
  1492. _fex = ((int (*)(struct pt_regs *, int, int))
  1493. jump_table[opcode[1]])
  1494. (regs, opcode[3] >> 4, opcode[3] & 15);
  1495. emu_load_regd((opcode[3] >> 4) & 15);
  1496. emu_load_regd(opcode[3] & 15);
  1497. break;
  1498. case 3: /* RRE format, float operation */
  1499. emu_store_rege((opcode[3] >> 4) & 15);
  1500. emu_store_rege(opcode[3] & 15);
  1501. /* call the emulation function */
  1502. _fex = ((int (*)(struct pt_regs *, int, int))
  1503. jump_table[opcode[1]])
  1504. (regs, opcode[3] >> 4, opcode[3] & 15);
  1505. emu_load_rege((opcode[3] >> 4) & 15);
  1506. emu_load_rege(opcode[3] & 15);
  1507. break;
  1508. case 4: /* RRF format, long double operation */
  1509. if (opcode[3] & 0x22)
  1510. return SIGILL;
  1511. emu_store_regd((opcode[3] >> 4) & 15);
  1512. emu_store_regd(((opcode[3] >> 4) & 15) + 2);
  1513. emu_store_regd(opcode[3] & 15);
  1514. emu_store_regd((opcode[3] & 15) + 2);
  1515. /* call the emulation function */
  1516. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1517. jump_table[opcode[1]])
  1518. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1519. emu_load_regd((opcode[3] >> 4) & 15);
  1520. emu_load_regd(((opcode[3] >> 4) & 15) + 2);
  1521. emu_load_regd(opcode[3] & 15);
  1522. emu_load_regd((opcode[3] & 15) + 2);
  1523. break;
  1524. case 5: /* RRF format, double operation */
  1525. emu_store_regd((opcode[2] >> 4) & 15);
  1526. emu_store_regd((opcode[3] >> 4) & 15);
  1527. emu_store_regd(opcode[3] & 15);
  1528. /* call the emulation function */
  1529. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1530. jump_table[opcode[1]])
  1531. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1532. emu_load_regd((opcode[2] >> 4) & 15);
  1533. emu_load_regd((opcode[3] >> 4) & 15);
  1534. emu_load_regd(opcode[3] & 15);
  1535. break;
  1536. case 6: /* RRF format, float operation */
  1537. emu_store_rege((opcode[2] >> 4) & 15);
  1538. emu_store_rege((opcode[3] >> 4) & 15);
  1539. emu_store_rege(opcode[3] & 15);
  1540. /* call the emulation function */
  1541. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1542. jump_table[opcode[1]])
  1543. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1544. emu_load_rege((opcode[2] >> 4) & 15);
  1545. emu_load_rege((opcode[3] >> 4) & 15);
  1546. emu_load_rege(opcode[3] & 15);
  1547. break;
  1548. case 7: /* RRE format, cxfbr instruction */
  1549. /* call the emulation function */
  1550. if (opcode[3] & 0x20)
  1551. return SIGILL;
  1552. _fex = ((int (*)(struct pt_regs *, int, int))
  1553. jump_table[opcode[1]])
  1554. (regs, opcode[3] >> 4, opcode[3] & 15);
  1555. emu_load_regd((opcode[3] >> 4) & 15);
  1556. emu_load_regd(((opcode[3] >> 4) & 15) + 2);
  1557. break;
  1558. case 8: /* RRE format, cdfbr instruction */
  1559. /* call the emulation function */
  1560. _fex = ((int (*)(struct pt_regs *, int, int))
  1561. jump_table[opcode[1]])
  1562. (regs, opcode[3] >> 4, opcode[3] & 15);
  1563. emu_load_regd((opcode[3] >> 4) & 15);
  1564. break;
  1565. case 9: /* RRE format, cefbr instruction */
  1566. /* call the emulation function */
  1567. _fex = ((int (*)(struct pt_regs *, int, int))
  1568. jump_table[opcode[1]])
  1569. (regs, opcode[3] >> 4, opcode[3] & 15);
  1570. emu_load_rege((opcode[3] >> 4) & 15);
  1571. break;
  1572. case 10: /* RRF format, cfxbr instruction */
  1573. if ((opcode[2] & 128) == 128 || (opcode[2] & 96) == 32)
  1574. /* mask of { 2,3,8-15 } is invalid */
  1575. return SIGILL;
  1576. if (opcode[3] & 2)
  1577. return SIGILL;
  1578. emu_store_regd(opcode[3] & 15);
  1579. emu_store_regd((opcode[3] & 15) + 2);
  1580. /* call the emulation function */
  1581. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1582. jump_table[opcode[1]])
  1583. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1584. break;
  1585. case 11: /* RRF format, cfdbr instruction */
  1586. if ((opcode[2] & 128) == 128 || (opcode[2] & 96) == 32)
  1587. /* mask of { 2,3,8-15 } is invalid */
  1588. return SIGILL;
  1589. emu_store_regd(opcode[3] & 15);
  1590. /* call the emulation function */
  1591. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1592. jump_table[opcode[1]])
  1593. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1594. break;
  1595. case 12: /* RRF format, cfebr instruction */
  1596. if ((opcode[2] & 128) == 128 || (opcode[2] & 96) == 32)
  1597. /* mask of { 2,3,8-15 } is invalid */
  1598. return SIGILL;
  1599. emu_store_rege(opcode[3] & 15);
  1600. /* call the emulation function */
  1601. _fex = ((int (*)(struct pt_regs *, int, int, int))
  1602. jump_table[opcode[1]])
  1603. (regs, opcode[3] >> 4, opcode[3] & 15, opcode[2] >> 4);
  1604. break;
  1605. case 13: /* RRE format, ldxbr & mdxbr instruction */
  1606. /* double store but long double load */
  1607. if (opcode[3] & 0x20)
  1608. return SIGILL;
  1609. emu_store_regd((opcode[3] >> 4) & 15);
  1610. emu_store_regd(opcode[3] & 15);
  1611. /* call the emulation function */
  1612. _fex = ((int (*)(struct pt_regs *, int, int))
  1613. jump_table[opcode[1]])
  1614. (regs, opcode[3] >> 4, opcode[3] & 15);
  1615. emu_load_regd((opcode[3] >> 4) & 15);
  1616. emu_load_regd(((opcode[3] >> 4) & 15) + 2);
  1617. break;
  1618. case 14: /* RRE format, ldxbr & mdxbr instruction */
  1619. /* float store but long double load */
  1620. if (opcode[3] & 0x20)
  1621. return SIGILL;
  1622. emu_store_rege((opcode[3] >> 4) & 15);
  1623. emu_store_rege(opcode[3] & 15);
  1624. /* call the emulation function */
  1625. _fex = ((int (*)(struct pt_regs *, int, int))
  1626. jump_table[opcode[1]])
  1627. (regs, opcode[3] >> 4, opcode[3] & 15);
  1628. emu_load_regd((opcode[3] >> 4) & 15);
  1629. emu_load_regd(((opcode[3] >> 4) & 15) + 2);
  1630. break;
  1631. case 15: /* RRE format, ldebr & mdebr instruction */
  1632. /* float store but double load */
  1633. emu_store_rege((opcode[3] >> 4) & 15);
  1634. emu_store_rege(opcode[3] & 15);
  1635. /* call the emulation function */
  1636. _fex = ((int (*)(struct pt_regs *, int, int))
  1637. jump_table[opcode[1]])
  1638. (regs, opcode[3] >> 4, opcode[3] & 15);
  1639. emu_load_regd((opcode[3] >> 4) & 15);
  1640. break;
  1641. case 16: /* RRE format, ldxbr instruction */
  1642. /* long double store but double load */
  1643. if (opcode[3] & 2)
  1644. return SIGILL;
  1645. emu_store_regd(opcode[3] & 15);
  1646. emu_store_regd((opcode[3] & 15) + 2);
  1647. /* call the emulation function */
  1648. _fex = ((int (*)(struct pt_regs *, int, int))
  1649. jump_table[opcode[1]])
  1650. (regs, opcode[3] >> 4, opcode[3] & 15);
  1651. emu_load_regd((opcode[3] >> 4) & 15);
  1652. break;
  1653. case 17: /* RRE format, ldxbr instruction */
  1654. /* long double store but float load */
  1655. if (opcode[3] & 2)
  1656. return SIGILL;
  1657. emu_store_regd(opcode[3] & 15);
  1658. emu_store_regd((opcode[3] & 15) + 2);
  1659. /* call the emulation function */
  1660. _fex = ((int (*)(struct pt_regs *, int, int))
  1661. jump_table[opcode[1]])
  1662. (regs, opcode[3] >> 4, opcode[3] & 15);
  1663. emu_load_rege((opcode[3] >> 4) & 15);
  1664. break;
  1665. case 18: /* RRE format, ledbr instruction */
  1666. /* double store but float load */
  1667. emu_store_regd(opcode[3] & 15);
  1668. /* call the emulation function */
  1669. _fex = ((int (*)(struct pt_regs *, int, int))
  1670. jump_table[opcode[1]])
  1671. (regs, opcode[3] >> 4, opcode[3] & 15);
  1672. emu_load_rege((opcode[3] >> 4) & 15);
  1673. break;
  1674. case 19: /* RRE format, efpc & sfpc instruction */
  1675. /* call the emulation function */
  1676. _fex = ((int (*)(struct pt_regs *, int, int))
  1677. jump_table[opcode[1]])
  1678. (regs, opcode[3] >> 4, opcode[3] & 15);
  1679. break;
  1680. default: /* invalid operation */
  1681. return SIGILL;
  1682. }
  1683. if (_fex != 0) {
  1684. current->thread.fp_regs.fpc |= _fex;
  1685. if (current->thread.fp_regs.fpc & (_fex << 8))
  1686. return SIGFPE;
  1687. }
  1688. return 0;
  1689. }
  1690. static void* calc_addr(struct pt_regs *regs, int rx, int rb, int disp)
  1691. {
  1692. addr_t addr;
  1693. rx &= 15;
  1694. rb &= 15;
  1695. addr = disp & 0xfff;
  1696. addr += (rx != 0) ? regs->gprs[rx] : 0; /* + index */
  1697. addr += (rb != 0) ? regs->gprs[rb] : 0; /* + base */
  1698. return (void*) addr;
  1699. }
  1700. int math_emu_ed(__u8 *opcode, struct pt_regs * regs) {
  1701. int _fex = 0;
  1702. static const __u8 format_table[256] = {
  1703. [0x04] = 0x06,[0x05] = 0x05,[0x06] = 0x07,[0x07] = 0x05,
  1704. [0x08] = 0x02,[0x09] = 0x02,[0x0a] = 0x02,[0x0b] = 0x02,
  1705. [0x0c] = 0x06,[0x0d] = 0x02,[0x0e] = 0x04,[0x0f] = 0x04,
  1706. [0x10] = 0x08,[0x11] = 0x09,[0x12] = 0x0a,[0x14] = 0x02,
  1707. [0x15] = 0x01,[0x17] = 0x02,[0x18] = 0x01,[0x19] = 0x01,
  1708. [0x1a] = 0x01,[0x1b] = 0x01,[0x1c] = 0x01,[0x1d] = 0x01,
  1709. [0x1e] = 0x03,[0x1f] = 0x03,
  1710. };
  1711. static const void *jump_table[]= {
  1712. [0x04] = emu_ldeb,[0x05] = emu_lxdb,[0x06] = emu_lxeb,
  1713. [0x07] = emu_mxdb,[0x08] = emu_keb, [0x09] = emu_ceb,
  1714. [0x0a] = emu_aeb, [0x0b] = emu_seb, [0x0c] = emu_mdeb,
  1715. [0x0d] = emu_deb, [0x0e] = emu_maeb,[0x0f] = emu_mseb,
  1716. [0x10] = emu_tceb,[0x11] = emu_tcdb,[0x12] = emu_tcxb,
  1717. [0x14] = emu_sqeb,[0x15] = emu_sqdb,[0x17] = emu_meeb,
  1718. [0x18] = emu_kdb, [0x19] = emu_cdb, [0x1a] = emu_adb,
  1719. [0x1b] = emu_sdb, [0x1c] = emu_mdb, [0x1d] = emu_ddb,
  1720. [0x1e] = emu_madb,[0x1f] = emu_msdb
  1721. };
  1722. switch (format_table[opcode[5]]) {
  1723. case 1: /* RXE format, double constant */ {
  1724. __u64 *dxb, temp;
  1725. __u32 opc;
  1726. emu_store_regd((opcode[1] >> 4) & 15);
  1727. opc = *((__u32 *) opcode);
  1728. dxb = (__u64 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1729. mathemu_copy_from_user(&temp, dxb, 8);
  1730. /* call the emulation function */
  1731. _fex = ((int (*)(struct pt_regs *, int, double *))
  1732. jump_table[opcode[5]])
  1733. (regs, opcode[1] >> 4, (double *) &temp);
  1734. emu_load_regd((opcode[1] >> 4) & 15);
  1735. break;
  1736. }
  1737. case 2: /* RXE format, float constant */ {
  1738. __u32 *dxb, temp;
  1739. __u32 opc;
  1740. emu_store_rege((opcode[1] >> 4) & 15);
  1741. opc = *((__u32 *) opcode);
  1742. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1743. mathemu_get_user(temp, dxb);
  1744. /* call the emulation function */
  1745. _fex = ((int (*)(struct pt_regs *, int, float *))
  1746. jump_table[opcode[5]])
  1747. (regs, opcode[1] >> 4, (float *) &temp);
  1748. emu_load_rege((opcode[1] >> 4) & 15);
  1749. break;
  1750. }
  1751. case 3: /* RXF format, double constant */ {
  1752. __u64 *dxb, temp;
  1753. __u32 opc;
  1754. emu_store_regd((opcode[1] >> 4) & 15);
  1755. emu_store_regd((opcode[4] >> 4) & 15);
  1756. opc = *((__u32 *) opcode);
  1757. dxb = (__u64 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1758. mathemu_copy_from_user(&temp, dxb, 8);
  1759. /* call the emulation function */
  1760. _fex = ((int (*)(struct pt_regs *, int, double *, int))
  1761. jump_table[opcode[5]])
  1762. (regs, opcode[1] >> 4, (double *) &temp, opcode[4] >> 4);
  1763. emu_load_regd((opcode[1] >> 4) & 15);
  1764. break;
  1765. }
  1766. case 4: /* RXF format, float constant */ {
  1767. __u32 *dxb, temp;
  1768. __u32 opc;
  1769. emu_store_rege((opcode[1] >> 4) & 15);
  1770. emu_store_rege((opcode[4] >> 4) & 15);
  1771. opc = *((__u32 *) opcode);
  1772. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1773. mathemu_get_user(temp, dxb);
  1774. /* call the emulation function */
  1775. _fex = ((int (*)(struct pt_regs *, int, float *, int))
  1776. jump_table[opcode[5]])
  1777. (regs, opcode[1] >> 4, (float *) &temp, opcode[4] >> 4);
  1778. emu_load_rege((opcode[4] >> 4) & 15);
  1779. break;
  1780. }
  1781. case 5: /* RXE format, double constant */
  1782. /* store double and load long double */
  1783. {
  1784. __u64 *dxb, temp;
  1785. __u32 opc;
  1786. if ((opcode[1] >> 4) & 0x20)
  1787. return SIGILL;
  1788. emu_store_regd((opcode[1] >> 4) & 15);
  1789. opc = *((__u32 *) opcode);
  1790. dxb = (__u64 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1791. mathemu_copy_from_user(&temp, dxb, 8);
  1792. /* call the emulation function */
  1793. _fex = ((int (*)(struct pt_regs *, int, double *))
  1794. jump_table[opcode[5]])
  1795. (regs, opcode[1] >> 4, (double *) &temp);
  1796. emu_load_regd((opcode[1] >> 4) & 15);
  1797. emu_load_regd(((opcode[1] >> 4) & 15) + 2);
  1798. break;
  1799. }
  1800. case 6: /* RXE format, float constant */
  1801. /* store float and load double */
  1802. {
  1803. __u32 *dxb, temp;
  1804. __u32 opc;
  1805. emu_store_rege((opcode[1] >> 4) & 15);
  1806. opc = *((__u32 *) opcode);
  1807. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1808. mathemu_get_user(temp, dxb);
  1809. /* call the emulation function */
  1810. _fex = ((int (*)(struct pt_regs *, int, float *))
  1811. jump_table[opcode[5]])
  1812. (regs, opcode[1] >> 4, (float *) &temp);
  1813. emu_load_regd((opcode[1] >> 4) & 15);
  1814. break;
  1815. }
  1816. case 7: /* RXE format, float constant */
  1817. /* store float and load long double */
  1818. {
  1819. __u32 *dxb, temp;
  1820. __u32 opc;
  1821. if ((opcode[1] >> 4) & 0x20)
  1822. return SIGILL;
  1823. emu_store_rege((opcode[1] >> 4) & 15);
  1824. opc = *((__u32 *) opcode);
  1825. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1826. mathemu_get_user(temp, dxb);
  1827. /* call the emulation function */
  1828. _fex = ((int (*)(struct pt_regs *, int, float *))
  1829. jump_table[opcode[5]])
  1830. (regs, opcode[1] >> 4, (float *) &temp);
  1831. emu_load_regd((opcode[1] >> 4) & 15);
  1832. emu_load_regd(((opcode[1] >> 4) & 15) + 2);
  1833. break;
  1834. }
  1835. case 8: /* RXE format, RX address used as int value */ {
  1836. __u64 dxb;
  1837. __u32 opc;
  1838. emu_store_rege((opcode[1] >> 4) & 15);
  1839. opc = *((__u32 *) opcode);
  1840. dxb = (__u64) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1841. /* call the emulation function */
  1842. _fex = ((int (*)(struct pt_regs *, int, long))
  1843. jump_table[opcode[5]])
  1844. (regs, opcode[1] >> 4, dxb);
  1845. break;
  1846. }
  1847. case 9: /* RXE format, RX address used as int value */ {
  1848. __u64 dxb;
  1849. __u32 opc;
  1850. emu_store_regd((opcode[1] >> 4) & 15);
  1851. opc = *((__u32 *) opcode);
  1852. dxb = (__u64) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1853. /* call the emulation function */
  1854. _fex = ((int (*)(struct pt_regs *, int, long))
  1855. jump_table[opcode[5]])
  1856. (regs, opcode[1] >> 4, dxb);
  1857. break;
  1858. }
  1859. case 10: /* RXE format, RX address used as int value */ {
  1860. __u64 dxb;
  1861. __u32 opc;
  1862. if ((opcode[1] >> 4) & 2)
  1863. return SIGILL;
  1864. emu_store_regd((opcode[1] >> 4) & 15);
  1865. emu_store_regd(((opcode[1] >> 4) & 15) + 2);
  1866. opc = *((__u32 *) opcode);
  1867. dxb = (__u64) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1868. /* call the emulation function */
  1869. _fex = ((int (*)(struct pt_regs *, int, long))
  1870. jump_table[opcode[5]])
  1871. (regs, opcode[1] >> 4, dxb);
  1872. break;
  1873. }
  1874. default: /* invalid operation */
  1875. return SIGILL;
  1876. }
  1877. if (_fex != 0) {
  1878. current->thread.fp_regs.fpc |= _fex;
  1879. if (current->thread.fp_regs.fpc & (_fex << 8))
  1880. return SIGFPE;
  1881. }
  1882. return 0;
  1883. }
  1884. /*
  1885. * Emulate LDR Rx,Ry with Rx or Ry not in {0, 2, 4, 6}
  1886. */
  1887. int math_emu_ldr(__u8 *opcode) {
  1888. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1889. __u16 opc = *((__u16 *) opcode);
  1890. if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
  1891. /* we got an exception therfore ry can't be in {0,2,4,6} */
  1892. asm volatile( /* load rx from fp_regs.fprs[ry] */
  1893. " bras 1,0f\n"
  1894. " ld 0,0(%1)\n"
  1895. "0: ex %0,0(1)"
  1896. : /* no output */
  1897. : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].d)
  1898. : "1");
  1899. } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
  1900. asm volatile ( /* store ry to fp_regs.fprs[rx] */
  1901. " bras 1,0f\n"
  1902. " std 0,0(%1)\n"
  1903. "0: ex %0,0(1)"
  1904. : /* no output */
  1905. : "a" ((opc & 0xf) << 4),
  1906. "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
  1907. : "1");
  1908. } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
  1909. fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
  1910. return 0;
  1911. }
  1912. /*
  1913. * Emulate LER Rx,Ry with Rx or Ry not in {0, 2, 4, 6}
  1914. */
  1915. int math_emu_ler(__u8 *opcode) {
  1916. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1917. __u16 opc = *((__u16 *) opcode);
  1918. if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
  1919. /* we got an exception therfore ry can't be in {0,2,4,6} */
  1920. asm volatile( /* load rx from fp_regs.fprs[ry] */
  1921. " bras 1,0f\n"
  1922. " le 0,0(%1)\n"
  1923. "0: ex %0,0(1)"
  1924. : /* no output */
  1925. : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].f)
  1926. : "1");
  1927. } else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
  1928. asm volatile( /* store ry to fp_regs.fprs[rx] */
  1929. " bras 1,0f\n"
  1930. " ste 0,0(%1)\n"
  1931. "0: ex %0,0(1)"
  1932. : /* no output */
  1933. : "a" ((opc & 0xf) << 4),
  1934. "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
  1935. : "1");
  1936. } else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
  1937. fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
  1938. return 0;
  1939. }
  1940. /*
  1941. * Emulate LD R,D(X,B) with R not in {0, 2, 4, 6}
  1942. */
  1943. int math_emu_ld(__u8 *opcode, struct pt_regs * regs) {
  1944. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1945. __u32 opc = *((__u32 *) opcode);
  1946. __u64 *dxb;
  1947. dxb = (__u64 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1948. mathemu_copy_from_user(&fp_regs->fprs[(opc >> 20) & 0xf].d, dxb, 8);
  1949. return 0;
  1950. }
  1951. /*
  1952. * Emulate LE R,D(X,B) with R not in {0, 2, 4, 6}
  1953. */
  1954. int math_emu_le(__u8 *opcode, struct pt_regs * regs) {
  1955. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1956. __u32 opc = *((__u32 *) opcode);
  1957. __u32 *mem, *dxb;
  1958. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1959. mem = (__u32 *) (&fp_regs->fprs[(opc >> 20) & 0xf].f);
  1960. mathemu_get_user(mem[0], dxb);
  1961. return 0;
  1962. }
  1963. /*
  1964. * Emulate STD R,D(X,B) with R not in {0, 2, 4, 6}
  1965. */
  1966. int math_emu_std(__u8 *opcode, struct pt_regs * regs) {
  1967. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1968. __u32 opc = *((__u32 *) opcode);
  1969. __u64 *dxb;
  1970. dxb = (__u64 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1971. mathemu_copy_to_user(dxb, &fp_regs->fprs[(opc >> 20) & 0xf].d, 8);
  1972. return 0;
  1973. }
  1974. /*
  1975. * Emulate STE R,D(X,B) with R not in {0, 2, 4, 6}
  1976. */
  1977. int math_emu_ste(__u8 *opcode, struct pt_regs * regs) {
  1978. s390_fp_regs *fp_regs = &current->thread.fp_regs;
  1979. __u32 opc = *((__u32 *) opcode);
  1980. __u32 *mem, *dxb;
  1981. dxb = (__u32 *) calc_addr(regs, opc >> 16, opc >> 12, opc);
  1982. mem = (__u32 *) (&fp_regs->fprs[(opc >> 20) & 0xf].f);
  1983. mathemu_put_user(mem[0], dxb);
  1984. return 0;
  1985. }
  1986. /*
  1987. * Emulate LFPC D(B)
  1988. */
  1989. int math_emu_lfpc(__u8 *opcode, struct pt_regs *regs) {
  1990. __u32 opc = *((__u32 *) opcode);
  1991. __u32 *dxb, temp;
  1992. dxb= (__u32 *) calc_addr(regs, 0, opc>>12, opc);
  1993. mathemu_get_user(temp, dxb);
  1994. if ((temp & ~FPC_VALID_MASK) != 0)
  1995. return SIGILL;
  1996. current->thread.fp_regs.fpc = temp;
  1997. return 0;
  1998. }
  1999. /*
  2000. * Emulate STFPC D(B)
  2001. */
  2002. int math_emu_stfpc(__u8 *opcode, struct pt_regs *regs) {
  2003. __u32 opc = *((__u32 *) opcode);
  2004. __u32 *dxb;
  2005. dxb= (__u32 *) calc_addr(regs, 0, opc>>12, opc);
  2006. mathemu_put_user(current->thread.fp_regs.fpc, dxb);
  2007. return 0;
  2008. }
  2009. /*
  2010. * Emulate SRNM D(B)
  2011. */
  2012. int math_emu_srnm(__u8 *opcode, struct pt_regs *regs) {
  2013. __u32 opc = *((__u32 *) opcode);
  2014. __u32 temp;
  2015. temp = calc_addr(regs, 0, opc>>12, opc);
  2016. current->thread.fp_regs.fpc &= ~3;
  2017. current->thread.fp_regs.fpc |= (temp & 3);
  2018. return 0;
  2019. }
  2020. /* broken compiler ... */
  2021. long long
  2022. __negdi2 (long long u)
  2023. {
  2024. union lll {
  2025. long long ll;
  2026. long s[2];
  2027. };
  2028. union lll w,uu;
  2029. uu.ll = u;
  2030. w.s[1] = -uu.s[1];
  2031. w.s[0] = -uu.s[0] - ((int) w.s[1] != 0);
  2032. return w.ll;
  2033. }