vfpmodule.c 8.4 KB

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  1. /*
  2. * linux/arch/arm/vfp/vfpmodule.c
  3. *
  4. * Copyright (C) 2004 ARM Limited.
  5. * Written by Deep Blue Solutions Limited.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/types.h>
  13. #include <linux/kernel.h>
  14. #include <linux/signal.h>
  15. #include <linux/sched.h>
  16. #include <linux/init.h>
  17. #include <asm/thread_notify.h>
  18. #include <asm/vfp.h>
  19. #include "vfpinstr.h"
  20. #include "vfp.h"
  21. /*
  22. * Our undef handlers (in entry.S)
  23. */
  24. void vfp_testing_entry(void);
  25. void vfp_support_entry(void);
  26. void (*vfp_vector)(void) = vfp_testing_entry;
  27. union vfp_state *last_VFP_context[NR_CPUS];
  28. /*
  29. * Dual-use variable.
  30. * Used in startup: set to non-zero if VFP checks fail
  31. * After startup, holds VFP architecture
  32. */
  33. unsigned int VFP_arch;
  34. static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v)
  35. {
  36. struct thread_info *thread = v;
  37. union vfp_state *vfp;
  38. __u32 cpu = thread->cpu;
  39. if (likely(cmd == THREAD_NOTIFY_SWITCH)) {
  40. u32 fpexc = fmrx(FPEXC);
  41. #ifdef CONFIG_SMP
  42. /*
  43. * On SMP, if VFP is enabled, save the old state in
  44. * case the thread migrates to a different CPU. The
  45. * restoring is done lazily.
  46. */
  47. if ((fpexc & FPEXC_ENABLE) && last_VFP_context[cpu]) {
  48. vfp_save_state(last_VFP_context[cpu], fpexc);
  49. last_VFP_context[cpu]->hard.cpu = cpu;
  50. }
  51. /*
  52. * Thread migration, just force the reloading of the
  53. * state on the new CPU in case the VFP registers
  54. * contain stale data.
  55. */
  56. if (thread->vfpstate.hard.cpu != cpu)
  57. last_VFP_context[cpu] = NULL;
  58. #endif
  59. /*
  60. * Always disable VFP so we can lazily save/restore the
  61. * old state.
  62. */
  63. fmxr(FPEXC, fpexc & ~FPEXC_ENABLE);
  64. return NOTIFY_DONE;
  65. }
  66. vfp = &thread->vfpstate;
  67. if (cmd == THREAD_NOTIFY_FLUSH) {
  68. /*
  69. * Per-thread VFP initialisation.
  70. */
  71. memset(vfp, 0, sizeof(union vfp_state));
  72. vfp->hard.fpexc = FPEXC_ENABLE;
  73. vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
  74. /*
  75. * Disable VFP to ensure we initialise it first.
  76. */
  77. fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
  78. }
  79. /* flush and release case: Per-thread VFP cleanup. */
  80. if (last_VFP_context[cpu] == vfp)
  81. last_VFP_context[cpu] = NULL;
  82. return NOTIFY_DONE;
  83. }
  84. static struct notifier_block vfp_notifier_block = {
  85. .notifier_call = vfp_notifier,
  86. };
  87. /*
  88. * Raise a SIGFPE for the current process.
  89. * sicode describes the signal being raised.
  90. */
  91. void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
  92. {
  93. siginfo_t info;
  94. memset(&info, 0, sizeof(info));
  95. info.si_signo = SIGFPE;
  96. info.si_code = sicode;
  97. info.si_addr = (void __user *)(instruction_pointer(regs) - 4);
  98. /*
  99. * This is the same as NWFPE, because it's not clear what
  100. * this is used for
  101. */
  102. current->thread.error_code = 0;
  103. current->thread.trap_no = 6;
  104. send_sig_info(SIGFPE, &info, current);
  105. }
  106. static void vfp_panic(char *reason)
  107. {
  108. int i;
  109. printk(KERN_ERR "VFP: Error: %s\n", reason);
  110. printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
  111. fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
  112. for (i = 0; i < 32; i += 2)
  113. printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
  114. i, vfp_get_float(i), i+1, vfp_get_float(i+1));
  115. }
  116. /*
  117. * Process bitmask of exception conditions.
  118. */
  119. static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
  120. {
  121. int si_code = 0;
  122. pr_debug("VFP: raising exceptions %08x\n", exceptions);
  123. if (exceptions == VFP_EXCEPTION_ERROR) {
  124. vfp_panic("unhandled bounce");
  125. vfp_raise_sigfpe(0, regs);
  126. return;
  127. }
  128. /*
  129. * If any of the status flags are set, update the FPSCR.
  130. * Comparison instructions always return at least one of
  131. * these flags set.
  132. */
  133. if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
  134. fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
  135. fpscr |= exceptions;
  136. fmxr(FPSCR, fpscr);
  137. #define RAISE(stat,en,sig) \
  138. if (exceptions & stat && fpscr & en) \
  139. si_code = sig;
  140. /*
  141. * These are arranged in priority order, least to highest.
  142. */
  143. RAISE(FPSCR_DZC, FPSCR_DZE, FPE_FLTDIV);
  144. RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
  145. RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
  146. RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
  147. RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);
  148. if (si_code)
  149. vfp_raise_sigfpe(si_code, regs);
  150. }
  151. /*
  152. * Emulate a VFP instruction.
  153. */
  154. static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
  155. {
  156. u32 exceptions = VFP_EXCEPTION_ERROR;
  157. pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
  158. if (INST_CPRTDO(inst)) {
  159. if (!INST_CPRT(inst)) {
  160. /*
  161. * CPDO
  162. */
  163. if (vfp_single(inst)) {
  164. exceptions = vfp_single_cpdo(inst, fpscr);
  165. } else {
  166. exceptions = vfp_double_cpdo(inst, fpscr);
  167. }
  168. } else {
  169. /*
  170. * A CPRT instruction can not appear in FPINST2, nor
  171. * can it cause an exception. Therefore, we do not
  172. * have to emulate it.
  173. */
  174. }
  175. } else {
  176. /*
  177. * A CPDT instruction can not appear in FPINST2, nor can
  178. * it cause an exception. Therefore, we do not have to
  179. * emulate it.
  180. */
  181. }
  182. return exceptions & ~VFP_NAN_FLAG;
  183. }
  184. /*
  185. * Package up a bounce condition.
  186. */
  187. void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
  188. {
  189. u32 fpscr, orig_fpscr, exceptions, inst;
  190. pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
  191. /*
  192. * Enable access to the VFP so we can handle the bounce.
  193. */
  194. fmxr(FPEXC, fpexc & ~(FPEXC_EXCEPTION|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
  195. orig_fpscr = fpscr = fmrx(FPSCR);
  196. /*
  197. * If we are running with inexact exceptions enabled, we need to
  198. * emulate the trigger instruction. Note that as we're emulating
  199. * the trigger instruction, we need to increment PC.
  200. */
  201. if (fpscr & FPSCR_IXE) {
  202. regs->ARM_pc += 4;
  203. goto emulate;
  204. }
  205. barrier();
  206. /*
  207. * Modify fpscr to indicate the number of iterations remaining
  208. */
  209. if (fpexc & FPEXC_EXCEPTION) {
  210. u32 len;
  211. len = fpexc + (1 << FPEXC_LENGTH_BIT);
  212. fpscr &= ~FPSCR_LENGTH_MASK;
  213. fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
  214. }
  215. /*
  216. * Handle the first FP instruction. We used to take note of the
  217. * FPEXC bounce reason, but this appears to be unreliable.
  218. * Emulate the bounced instruction instead.
  219. */
  220. inst = fmrx(FPINST);
  221. exceptions = vfp_emulate_instruction(inst, fpscr, regs);
  222. if (exceptions)
  223. vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);
  224. /*
  225. * If there isn't a second FP instruction, exit now.
  226. */
  227. if (!(fpexc & FPEXC_FPV2))
  228. return;
  229. /*
  230. * The barrier() here prevents fpinst2 being read
  231. * before the condition above.
  232. */
  233. barrier();
  234. trigger = fmrx(FPINST2);
  235. orig_fpscr = fpscr = fmrx(FPSCR);
  236. emulate:
  237. exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
  238. if (exceptions)
  239. vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
  240. }
  241. static void vfp_enable(void *unused)
  242. {
  243. u32 access = get_copro_access();
  244. /*
  245. * Enable full access to VFP (cp10 and cp11)
  246. */
  247. set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
  248. }
  249. #include <linux/smp.h>
  250. /*
  251. * VFP support code initialisation.
  252. */
  253. static int __init vfp_init(void)
  254. {
  255. unsigned int vfpsid;
  256. unsigned int cpu_arch = cpu_architecture();
  257. u32 access = 0;
  258. if (cpu_arch >= CPU_ARCH_ARMv6) {
  259. access = get_copro_access();
  260. /*
  261. * Enable full access to VFP (cp10 and cp11)
  262. */
  263. set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
  264. }
  265. /*
  266. * First check that there is a VFP that we can use.
  267. * The handler is already setup to just log calls, so
  268. * we just need to read the VFPSID register.
  269. */
  270. vfpsid = fmrx(FPSID);
  271. barrier();
  272. printk(KERN_INFO "VFP support v0.3: ");
  273. if (VFP_arch) {
  274. printk("not present\n");
  275. /*
  276. * Restore the copro access register.
  277. */
  278. if (cpu_arch >= CPU_ARCH_ARMv6)
  279. set_copro_access(access);
  280. } else if (vfpsid & FPSID_NODOUBLE) {
  281. printk("no double precision support\n");
  282. } else {
  283. smp_call_function(vfp_enable, NULL, 1, 1);
  284. VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
  285. printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
  286. (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
  287. (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
  288. (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
  289. (vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
  290. (vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
  291. vfp_vector = vfp_support_entry;
  292. thread_register_notifier(&vfp_notifier_block);
  293. /*
  294. * We detected VFP, and the support code is
  295. * in place; report VFP support to userspace.
  296. */
  297. elf_hwcap |= HWCAP_VFP;
  298. }
  299. return 0;
  300. }
  301. late_initcall(vfp_init);