pci.c 6.2 KB

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  1. /*
  2. * arch/arm/plat-iop/pci.c
  3. *
  4. * PCI support for the Intel IOP32X and IOP33X processors
  5. *
  6. * Author: Rory Bolt <rorybolt@pacbell.net>
  7. * Copyright (C) 2002 Rory Bolt
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/pci.h>
  15. #include <linux/slab.h>
  16. #include <linux/mm.h>
  17. #include <linux/init.h>
  18. #include <linux/ioport.h>
  19. #include <asm/io.h>
  20. #include <asm/irq.h>
  21. #include <asm/system.h>
  22. #include <asm/hardware.h>
  23. #include <asm/mach/pci.h>
  24. #include <asm/hardware/iop3xx.h>
  25. // #define DEBUG
  26. #ifdef DEBUG
  27. #define DBG(x...) printk(x)
  28. #else
  29. #define DBG(x...) do { } while (0)
  30. #endif
  31. /*
  32. * This routine builds either a type0 or type1 configuration command. If the
  33. * bus is on the 803xx then a type0 made, else a type1 is created.
  34. */
  35. static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
  36. {
  37. struct pci_sys_data *sys = bus->sysdata;
  38. u32 addr;
  39. if (sys->busnr == bus->number)
  40. addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
  41. else
  42. addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
  43. addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
  44. return addr;
  45. }
  46. /*
  47. * This routine checks the status of the last configuration cycle. If an error
  48. * was detected it returns a 1, else it returns a 0. The errors being checked
  49. * are parity, master abort, target abort (master and target). These types of
  50. * errors occure during a config cycle where there is no device, like during
  51. * the discovery stage.
  52. */
  53. static int iop3xx_pci_status(void)
  54. {
  55. unsigned int status;
  56. int ret = 0;
  57. /*
  58. * Check the status registers.
  59. */
  60. status = *IOP3XX_ATUSR;
  61. if (status & 0xf900) {
  62. DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
  63. *IOP3XX_ATUSR = status & 0xf900;
  64. ret = 1;
  65. }
  66. status = *IOP3XX_ATUISR;
  67. if (status & 0x679f) {
  68. DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
  69. *IOP3XX_ATUISR = status & 0x679f;
  70. ret = 1;
  71. }
  72. return ret;
  73. }
  74. /*
  75. * Simply write the address register and read the configuration
  76. * data. Note that the 4 nop's ensure that we are able to handle
  77. * a delayed abort (in theory.)
  78. */
  79. static inline u32 iop3xx_read(unsigned long addr)
  80. {
  81. u32 val;
  82. __asm__ __volatile__(
  83. "str %1, [%2]\n\t"
  84. "ldr %0, [%3]\n\t"
  85. "nop\n\t"
  86. "nop\n\t"
  87. "nop\n\t"
  88. "nop\n\t"
  89. : "=r" (val)
  90. : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
  91. return val;
  92. }
  93. /*
  94. * The read routines must check the error status of the last configuration
  95. * cycle. If there was an error, the routine returns all hex f's.
  96. */
  97. static int
  98. iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  99. int size, u32 *value)
  100. {
  101. unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
  102. u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
  103. if (iop3xx_pci_status())
  104. val = 0xffffffff;
  105. *value = val;
  106. return PCIBIOS_SUCCESSFUL;
  107. }
  108. static int
  109. iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
  110. int size, u32 value)
  111. {
  112. unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
  113. u32 val;
  114. if (size != 4) {
  115. val = iop3xx_read(addr);
  116. if (iop3xx_pci_status())
  117. return PCIBIOS_SUCCESSFUL;
  118. where = (where & 3) * 8;
  119. if (size == 1)
  120. val &= ~(0xff << where);
  121. else
  122. val &= ~(0xffff << where);
  123. *IOP3XX_OCCDR = val | value << where;
  124. } else {
  125. asm volatile(
  126. "str %1, [%2]\n\t"
  127. "str %0, [%3]\n\t"
  128. "nop\n\t"
  129. "nop\n\t"
  130. "nop\n\t"
  131. "nop\n\t"
  132. :
  133. : "r" (value), "r" (addr),
  134. "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
  135. }
  136. return PCIBIOS_SUCCESSFUL;
  137. }
  138. static struct pci_ops iop3xx_ops = {
  139. .read = iop3xx_read_config,
  140. .write = iop3xx_write_config,
  141. };
  142. /*
  143. * When a PCI device does not exist during config cycles, the 80200 gets a
  144. * bus error instead of returning 0xffffffff. This handler simply returns.
  145. */
  146. static int
  147. iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
  148. {
  149. DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
  150. addr, fsr, regs->ARM_pc, regs->ARM_lr);
  151. /*
  152. * If it was an imprecise abort, then we need to correct the
  153. * return address to be _after_ the instruction.
  154. */
  155. if (fsr & (1 << 10))
  156. regs->ARM_pc += 4;
  157. return 0;
  158. }
  159. int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
  160. {
  161. struct resource *res;
  162. if (nr != 0)
  163. return 0;
  164. res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
  165. if (!res)
  166. panic("PCI: unable to alloc resources");
  167. res[0].start = IOP3XX_PCI_LOWER_IO_PA;
  168. res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
  169. res[0].name = "IOP3XX PCI I/O Space";
  170. res[0].flags = IORESOURCE_IO;
  171. request_resource(&ioport_resource, &res[0]);
  172. res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
  173. res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
  174. res[1].name = "IOP3XX PCI Memory Space";
  175. res[1].flags = IORESOURCE_MEM;
  176. request_resource(&iomem_resource, &res[1]);
  177. sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
  178. sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - IOP3XX_PCI_LOWER_IO_BA;
  179. sys->resource[0] = &res[0];
  180. sys->resource[1] = &res[1];
  181. sys->resource[2] = NULL;
  182. return 1;
  183. }
  184. struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
  185. {
  186. return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
  187. }
  188. void iop3xx_pci_preinit(void)
  189. {
  190. DBG("PCI: Intel 803xx PCI init code.\n");
  191. DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
  192. DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
  193. *IOP3XX_OMWTVR0,
  194. *IOP3XX_OIOWTVR);
  195. DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
  196. DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
  197. *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
  198. DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
  199. DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
  200. *IOP3XX_IABAR1, *IOP3XX_IALR1);
  201. DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
  202. *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
  203. DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
  204. *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
  205. DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
  206. *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
  207. hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
  208. }