op_model_mpcore.h 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061
  1. /**
  2. * @file op_model_mpcore.c
  3. * MPCORE Event Monitor Driver
  4. * @remark Copyright 2004 ARM SMP Development Team
  5. * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
  6. * @remark Copyright 2000-2004 MontaVista Software Inc
  7. * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
  8. * @remark Copyright 2004 Intel Corporation
  9. * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
  10. * @remark Copyright 2004 Oprofile Authors
  11. *
  12. * @remark Read the file COPYING
  13. *
  14. * @author Zwane Mwaikambo
  15. */
  16. #ifndef OP_MODEL_MPCORE_H
  17. #define OP_MODEL_MPCORE_H
  18. struct eventmonitor {
  19. unsigned long PMCR;
  20. unsigned char MCEB[8];
  21. unsigned long MC[8];
  22. };
  23. /*
  24. * List of userspace counter numbers: note that the structure is important.
  25. * The code relies on CPUn's counters being CPU0's counters + 3n
  26. * and on CPU0's counters starting at 0
  27. */
  28. #define COUNTER_CPU0_PMN0 0
  29. #define COUNTER_CPU0_PMN1 1
  30. #define COUNTER_CPU0_CCNT 2
  31. #define COUNTER_CPU1_PMN0 3
  32. #define COUNTER_CPU1_PMN1 4
  33. #define COUNTER_CPU1_CCNT 5
  34. #define COUNTER_CPU2_PMN0 6
  35. #define COUNTER_CPU2_PMN1 7
  36. #define COUNTER_CPU2_CCNT 8
  37. #define COUNTER_CPU3_PMN0 9
  38. #define COUNTER_CPU3_PMN1 10
  39. #define COUNTER_CPU3_CCNT 11
  40. #define COUNTER_SCU_MN0 12
  41. #define COUNTER_SCU_MN1 13
  42. #define COUNTER_SCU_MN2 14
  43. #define COUNTER_SCU_MN3 15
  44. #define COUNTER_SCU_MN4 16
  45. #define COUNTER_SCU_MN5 17
  46. #define COUNTER_SCU_MN6 18
  47. #define COUNTER_SCU_MN7 19
  48. #define NUM_SCU_COUNTERS 8
  49. #define SCU_COUNTER(number) ((number) + COUNTER_SCU_MN0)
  50. #define MPCORE_NUM_COUNTERS SCU_COUNTER(NUM_SCU_COUNTERS)
  51. #endif