op_model_mpcore.c 6.5 KB

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  1. /**
  2. * @file op_model_mpcore.c
  3. * MPCORE Event Monitor Driver
  4. * @remark Copyright 2004 ARM SMP Development Team
  5. * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
  6. * @remark Copyright 2000-2004 MontaVista Software Inc
  7. * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
  8. * @remark Copyright 2004 Intel Corporation
  9. * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
  10. * @remark Copyright 2004 Oprofile Authors
  11. *
  12. * @remark Read the file COPYING
  13. *
  14. * @author Zwane Mwaikambo
  15. *
  16. * Counters:
  17. * 0: PMN0 on CPU0, per-cpu configurable event counter
  18. * 1: PMN1 on CPU0, per-cpu configurable event counter
  19. * 2: CCNT on CPU0
  20. * 3: PMN0 on CPU1
  21. * 4: PMN1 on CPU1
  22. * 5: CCNT on CPU1
  23. * 6: PMN0 on CPU1
  24. * 7: PMN1 on CPU1
  25. * 8: CCNT on CPU1
  26. * 9: PMN0 on CPU1
  27. * 10: PMN1 on CPU1
  28. * 11: CCNT on CPU1
  29. * 12-19: configurable SCU event counters
  30. */
  31. /* #define DEBUG */
  32. #include <linux/types.h>
  33. #include <linux/errno.h>
  34. #include <linux/sched.h>
  35. #include <linux/oprofile.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/smp.h>
  38. #include <asm/io.h>
  39. #include <asm/irq.h>
  40. #include <asm/mach/irq.h>
  41. #include <asm/hardware.h>
  42. #include <asm/system.h>
  43. #include "op_counter.h"
  44. #include "op_arm_model.h"
  45. #include "op_model_arm11_core.h"
  46. #include "op_model_mpcore.h"
  47. /*
  48. * MPCore SCU event monitor support
  49. */
  50. #define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_MPCORE_SCU_BASE + 0x10)
  51. /*
  52. * Bitmask of used SCU counters
  53. */
  54. static unsigned int scu_em_used;
  55. /*
  56. * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number)
  57. */
  58. static inline void scu_reset_counter(struct eventmonitor __iomem *emc, unsigned int n)
  59. {
  60. writel(-(u32)counter_config[SCU_COUNTER(n)].count, &emc->MC[n]);
  61. }
  62. static inline void scu_set_event(struct eventmonitor __iomem *emc, unsigned int n, u32 event)
  63. {
  64. event &= 0xff;
  65. writeb(event, &emc->MCEB[n]);
  66. }
  67. /*
  68. * SCU counters' IRQ handler (one IRQ per counter => 2 IRQs per CPU)
  69. */
  70. static irqreturn_t scu_em_interrupt(int irq, void *arg)
  71. {
  72. struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
  73. unsigned int cnt;
  74. cnt = irq - IRQ_PMU_SCU0;
  75. oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt));
  76. scu_reset_counter(emc, cnt);
  77. /* Clear overflow flag for this counter */
  78. writel(1 << (cnt + 16), &emc->PMCR);
  79. return IRQ_HANDLED;
  80. }
  81. /* Configure just the SCU counters that the user has requested */
  82. static void scu_setup(void)
  83. {
  84. struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
  85. unsigned int i;
  86. scu_em_used = 0;
  87. for (i = 0; i < NUM_SCU_COUNTERS; i++) {
  88. if (counter_config[SCU_COUNTER(i)].enabled &&
  89. counter_config[SCU_COUNTER(i)].event) {
  90. scu_set_event(emc, i, 0); /* disable counter for now */
  91. scu_em_used |= 1 << i;
  92. }
  93. }
  94. }
  95. static int scu_start(void)
  96. {
  97. struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
  98. unsigned int temp, i;
  99. unsigned long event;
  100. int ret = 0;
  101. /*
  102. * request the SCU counter interrupts that we need
  103. */
  104. for (i = 0; i < NUM_SCU_COUNTERS; i++) {
  105. if (scu_em_used & (1 << i)) {
  106. ret = request_irq(IRQ_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL);
  107. if (ret) {
  108. printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n",
  109. IRQ_PMU_SCU0 + i);
  110. goto err_free_scu;
  111. }
  112. }
  113. }
  114. /*
  115. * clear overflow and enable interrupt for all used counters
  116. */
  117. temp = readl(&emc->PMCR);
  118. for (i = 0; i < NUM_SCU_COUNTERS; i++) {
  119. if (scu_em_used & (1 << i)) {
  120. scu_reset_counter(emc, i);
  121. event = counter_config[SCU_COUNTER(i)].event;
  122. scu_set_event(emc, i, event);
  123. /* clear overflow/interrupt */
  124. temp |= 1 << (i + 16);
  125. /* enable interrupt*/
  126. temp |= 1 << (i + 8);
  127. }
  128. }
  129. /* Enable all 8 counters */
  130. temp |= PMCR_E;
  131. writel(temp, &emc->PMCR);
  132. return 0;
  133. err_free_scu:
  134. while (i--)
  135. free_irq(IRQ_PMU_SCU0 + i, NULL);
  136. return ret;
  137. }
  138. static void scu_stop(void)
  139. {
  140. struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
  141. unsigned int temp, i;
  142. /* Disable counter interrupts */
  143. /* Don't disable all 8 counters (with the E bit) as they may be in use */
  144. temp = readl(&emc->PMCR);
  145. for (i = 0; i < NUM_SCU_COUNTERS; i++) {
  146. if (scu_em_used & (1 << i))
  147. temp &= ~(1 << (i + 8));
  148. }
  149. writel(temp, &emc->PMCR);
  150. /* Free counter interrupts and reset counters */
  151. for (i = 0; i < NUM_SCU_COUNTERS; i++) {
  152. if (scu_em_used & (1 << i)) {
  153. scu_reset_counter(emc, i);
  154. free_irq(IRQ_PMU_SCU0 + i, NULL);
  155. }
  156. }
  157. }
  158. struct em_function_data {
  159. int (*fn)(void);
  160. int ret;
  161. };
  162. static void em_func(void *data)
  163. {
  164. struct em_function_data *d = data;
  165. int ret = d->fn();
  166. if (ret)
  167. d->ret = ret;
  168. }
  169. static int em_call_function(int (*fn)(void))
  170. {
  171. struct em_function_data data;
  172. data.fn = fn;
  173. data.ret = 0;
  174. smp_call_function(em_func, &data, 1, 1);
  175. em_func(&data);
  176. return data.ret;
  177. }
  178. /*
  179. * Glue to stick the individual ARM11 PMUs and the SCU
  180. * into the oprofile framework.
  181. */
  182. static int em_setup_ctrs(void)
  183. {
  184. int ret;
  185. /* Configure CPU counters by cross-calling to the other CPUs */
  186. ret = em_call_function(arm11_setup_pmu);
  187. if (ret == 0)
  188. scu_setup();
  189. return 0;
  190. }
  191. static int arm11_irqs[] = {
  192. [0] = IRQ_PMU_CPU0,
  193. [1] = IRQ_PMU_CPU1,
  194. [2] = IRQ_PMU_CPU2,
  195. [3] = IRQ_PMU_CPU3
  196. };
  197. static int em_start(void)
  198. {
  199. int ret;
  200. ret = arm11_request_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
  201. if (ret == 0) {
  202. em_call_function(arm11_start_pmu);
  203. ret = scu_start();
  204. if (ret)
  205. arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
  206. }
  207. return ret;
  208. }
  209. static void em_stop(void)
  210. {
  211. em_call_function(arm11_stop_pmu);
  212. arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
  213. scu_stop();
  214. }
  215. /*
  216. * Why isn't there a function to route an IRQ to a specific CPU in
  217. * genirq?
  218. */
  219. static void em_route_irq(int irq, unsigned int cpu)
  220. {
  221. irq_desc[irq].affinity = cpumask_of_cpu(cpu);
  222. irq_desc[irq].chip->set_affinity(irq, cpumask_of_cpu(cpu));
  223. }
  224. static int em_setup(void)
  225. {
  226. /*
  227. * Send SCU PMU interrupts to the "owner" CPU.
  228. */
  229. em_route_irq(IRQ_PMU_SCU0, 0);
  230. em_route_irq(IRQ_PMU_SCU1, 0);
  231. em_route_irq(IRQ_PMU_SCU2, 1);
  232. em_route_irq(IRQ_PMU_SCU3, 1);
  233. em_route_irq(IRQ_PMU_SCU4, 2);
  234. em_route_irq(IRQ_PMU_SCU5, 2);
  235. em_route_irq(IRQ_PMU_SCU6, 3);
  236. em_route_irq(IRQ_PMU_SCU7, 3);
  237. /*
  238. * Send CP15 PMU interrupts to the owner CPU.
  239. */
  240. em_route_irq(IRQ_PMU_CPU0, 0);
  241. em_route_irq(IRQ_PMU_CPU1, 1);
  242. em_route_irq(IRQ_PMU_CPU2, 2);
  243. em_route_irq(IRQ_PMU_CPU3, 3);
  244. return 0;
  245. }
  246. struct op_arm_model_spec op_mpcore_spec = {
  247. .init = em_setup,
  248. .num_counters = MPCORE_NUM_COUNTERS,
  249. .setup_ctrs = em_setup_ctrs,
  250. .start = em_start,
  251. .stop = em_stop,
  252. .name = "arm/mpcore",
  253. };