fpsr.h 3.8 KB

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  1. /*
  2. NetWinder Floating Point Emulator
  3. (c) Rebel.com, 1998-1999
  4. Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #ifndef __FPSR_H__
  18. #define __FPSR_H__
  19. /*
  20. The FPSR is a 32 bit register consisting of 4 parts, each exactly
  21. one byte.
  22. SYSTEM ID
  23. EXCEPTION TRAP ENABLE BYTE
  24. SYSTEM CONTROL BYTE
  25. CUMULATIVE EXCEPTION FLAGS BYTE
  26. The FPCR is a 32 bit register consisting of bit flags.
  27. */
  28. /* SYSTEM ID
  29. ------------
  30. Note: the system id byte is read only */
  31. typedef unsigned int FPSR; /* type for floating point status register */
  32. typedef unsigned int FPCR; /* type for floating point control register */
  33. #define MASK_SYSID 0xff000000
  34. #define BIT_HARDWARE 0x80000000
  35. #define FP_EMULATOR 0x01000000 /* System ID for emulator */
  36. #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */
  37. /* EXCEPTION TRAP ENABLE BYTE
  38. ----------------------------- */
  39. #define MASK_TRAP_ENABLE 0x00ff0000
  40. #define MASK_TRAP_ENABLE_STRICT 0x001f0000
  41. #define BIT_IXE 0x00100000 /* inexact exception enable */
  42. #define BIT_UFE 0x00080000 /* underflow exception enable */
  43. #define BIT_OFE 0x00040000 /* overflow exception enable */
  44. #define BIT_DZE 0x00020000 /* divide by zero exception enable */
  45. #define BIT_IOE 0x00010000 /* invalid operation exception enable */
  46. /* SYSTEM CONTROL BYTE
  47. ---------------------- */
  48. #define MASK_SYSTEM_CONTROL 0x0000ff00
  49. #define MASK_TRAP_STRICT 0x00001f00
  50. #define BIT_AC 0x00001000 /* use alternative C-flag definition
  51. for compares */
  52. #define BIT_EP 0x00000800 /* use expanded packed decimal format */
  53. #define BIT_SO 0x00000400 /* select synchronous operation of FPA */
  54. #define BIT_NE 0x00000200 /* NaN exception bit */
  55. #define BIT_ND 0x00000100 /* no denormalized numbers bit */
  56. /* CUMULATIVE EXCEPTION FLAGS BYTE
  57. ---------------------------------- */
  58. #define MASK_EXCEPTION_FLAGS 0x000000ff
  59. #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f
  60. #define BIT_IXC 0x00000010 /* inexact exception flag */
  61. #define BIT_UFC 0x00000008 /* underflow exception flag */
  62. #define BIT_OFC 0x00000004 /* overfloat exception flag */
  63. #define BIT_DZC 0x00000002 /* divide by zero exception flag */
  64. #define BIT_IOC 0x00000001 /* invalid operation exception flag */
  65. /* Floating Point Control Register
  66. ----------------------------------*/
  67. #define BIT_RU 0x80000000 /* rounded up bit */
  68. #define BIT_IE 0x10000000 /* inexact bit */
  69. #define BIT_MO 0x08000000 /* mantissa overflow bit */
  70. #define BIT_EO 0x04000000 /* exponent overflow bit */
  71. #define BIT_SB 0x00000800 /* store bounce */
  72. #define BIT_AB 0x00000400 /* arithmetic bounce */
  73. #define BIT_RE 0x00000200 /* rounding exception */
  74. #define BIT_DA 0x00000100 /* disable FPA */
  75. #define MASK_OP 0x00f08010 /* AU operation code */
  76. #define MASK_PR 0x00080080 /* AU precision */
  77. #define MASK_S1 0x00070000 /* AU source register 1 */
  78. #define MASK_S2 0x00000007 /* AU source register 2 */
  79. #define MASK_DS 0x00007000 /* AU destination register */
  80. #define MASK_RM 0x00000060 /* AU rounding mode */
  81. #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */
  82. #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */
  83. #define MASK_WFC MASK_RESET
  84. #define MASK_RFC ~MASK_RESET
  85. #endif