fpopcode.h 15 KB

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  1. /*
  2. NetWinder Floating Point Emulator
  3. (c) Rebel.COM, 1998,1999
  4. (c) Philip Blundell, 2001
  5. Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; if not, write to the Free Software
  16. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #ifndef __FPOPCODE_H__
  19. #define __FPOPCODE_H__
  20. /*
  21. ARM Floating Point Instruction Classes
  22. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  23. |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
  24. |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
  25. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  26. |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
  27. |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
  28. |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
  29. | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
  30. CPDT data transfer instructions
  31. LDF, STF, LFM (copro 2), SFM (copro 2)
  32. CPDO dyadic arithmetic instructions
  33. ADF, MUF, SUF, RSF, DVF, RDF,
  34. POW, RPW, RMF, FML, FDV, FRD, POL
  35. CPDO monadic arithmetic instructions
  36. MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
  37. SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
  38. CPRT joint arithmetic/data transfer instructions
  39. FIX (arithmetic followed by load/store)
  40. FLT (load/store followed by arithmetic)
  41. CMF, CNF CMFE, CNFE (comparisons)
  42. WFS, RFS (write/read floating point status register)
  43. WFC, RFC (write/read floating point control register)
  44. cond condition codes
  45. P pre/post index bit: 0 = postindex, 1 = preindex
  46. U up/down bit: 0 = stack grows down, 1 = stack grows up
  47. W write back bit: 1 = update base register (Rn)
  48. L load/store bit: 0 = store, 1 = load
  49. Rn base register
  50. Rd destination/source register
  51. Fd floating point destination register
  52. Fn floating point source register
  53. Fm floating point source register or floating point constant
  54. uv transfer length (TABLE 1)
  55. wx register count (TABLE 2)
  56. abcd arithmetic opcode (TABLES 3 & 4)
  57. ef destination size (rounding precision) (TABLE 5)
  58. gh rounding mode (TABLE 6)
  59. j dyadic/monadic bit: 0 = dyadic, 1 = monadic
  60. i constant bit: 1 = constant (TABLE 6)
  61. */
  62. /*
  63. TABLE 1
  64. +-------------------------+---+---+---------+---------+
  65. | Precision | u | v | FPSR.EP | length |
  66. +-------------------------+---+---+---------+---------+
  67. | Single | 0 ü 0 | x | 1 words |
  68. | Double | 1 ü 1 | x | 2 words |
  69. | Extended | 1 ü 1 | x | 3 words |
  70. | Packed decimal | 1 ü 1 | 0 | 3 words |
  71. | Expanded packed decimal | 1 ü 1 | 1 | 4 words |
  72. +-------------------------+---+---+---------+---------+
  73. Note: x = don't care
  74. */
  75. /*
  76. TABLE 2
  77. +---+---+---------------------------------+
  78. | w | x | Number of registers to transfer |
  79. +---+---+---------------------------------+
  80. | 0 ü 1 | 1 |
  81. | 1 ü 0 | 2 |
  82. | 1 ü 1 | 3 |
  83. | 0 ü 0 | 4 |
  84. +---+---+---------------------------------+
  85. */
  86. /*
  87. TABLE 3: Dyadic Floating Point Opcodes
  88. +---+---+---+---+----------+-----------------------+-----------------------+
  89. | a | b | c | d | Mnemonic | Description | Operation |
  90. +---+---+---+---+----------+-----------------------+-----------------------+
  91. | 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
  92. | 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
  93. | 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
  94. | 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
  95. | 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
  96. | 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
  97. | 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
  98. | 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
  99. | 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
  100. | 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
  101. | 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
  102. | 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
  103. | 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
  104. | 1 | 1 | 0 | 1 | | undefined instruction | trap |
  105. | 1 | 1 | 1 | 0 | | undefined instruction | trap |
  106. | 1 | 1 | 1 | 1 | | undefined instruction | trap |
  107. +---+---+---+---+----------+-----------------------+-----------------------+
  108. Note: POW, RPW, POL are deprecated, and are available for backwards
  109. compatibility only.
  110. */
  111. /*
  112. TABLE 4: Monadic Floating Point Opcodes
  113. +---+---+---+---+----------+-----------------------+-----------------------+
  114. | a | b | c | d | Mnemonic | Description | Operation |
  115. +---+---+---+---+----------+-----------------------+-----------------------+
  116. | 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
  117. | 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
  118. | 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
  119. | 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
  120. | 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
  121. | 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
  122. | 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
  123. | 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
  124. | 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
  125. | 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
  126. | 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
  127. | 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
  128. | 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
  129. | 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
  130. | 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
  131. | 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
  132. +---+---+---+---+----------+-----------------------+-----------------------+
  133. Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
  134. available for backwards compatibility only.
  135. */
  136. /*
  137. TABLE 5
  138. +-------------------------+---+---+
  139. | Rounding Precision | e | f |
  140. +-------------------------+---+---+
  141. | IEEE Single precision | 0 ü 0 |
  142. | IEEE Double precision | 0 ü 1 |
  143. | IEEE Extended precision | 1 ü 0 |
  144. | undefined (trap) | 1 ü 1 |
  145. +-------------------------+---+---+
  146. */
  147. /*
  148. TABLE 5
  149. +---------------------------------+---+---+
  150. | Rounding Mode | g | h |
  151. +---------------------------------+---+---+
  152. | Round to nearest (default) | 0 ü 0 |
  153. | Round toward plus infinity | 0 ü 1 |
  154. | Round toward negative infinity | 1 ü 0 |
  155. | Round toward zero | 1 ü 1 |
  156. +---------------------------------+---+---+
  157. */
  158. /*
  159. ===
  160. === Definitions for load and store instructions
  161. ===
  162. */
  163. /* bit masks */
  164. #define BIT_PREINDEX 0x01000000
  165. #define BIT_UP 0x00800000
  166. #define BIT_WRITE_BACK 0x00200000
  167. #define BIT_LOAD 0x00100000
  168. /* masks for load/store */
  169. #define MASK_CPDT 0x0c000000 /* data processing opcode */
  170. #define MASK_OFFSET 0x000000ff
  171. #define MASK_TRANSFER_LENGTH 0x00408000
  172. #define MASK_REGISTER_COUNT MASK_TRANSFER_LENGTH
  173. #define MASK_COPROCESSOR 0x00000f00
  174. /* Tests for transfer length */
  175. #define TRANSFER_SINGLE 0x00000000
  176. #define TRANSFER_DOUBLE 0x00008000
  177. #define TRANSFER_EXTENDED 0x00400000
  178. #define TRANSFER_PACKED MASK_TRANSFER_LENGTH
  179. /* Get the coprocessor number from the opcode. */
  180. #define getCoprocessorNumber(opcode) ((opcode & MASK_COPROCESSOR) >> 8)
  181. /* Get the offset from the opcode. */
  182. #define getOffset(opcode) (opcode & MASK_OFFSET)
  183. /* Tests for specific data transfer load/store opcodes. */
  184. #define TEST_OPCODE(opcode,mask) (((opcode) & (mask)) == (mask))
  185. #define LOAD_OP(opcode) TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
  186. #define STORE_OP(opcode) ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
  187. #define LDF_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
  188. #define LFM_OP(opcode) (LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
  189. #define STF_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
  190. #define SFM_OP(opcode) (STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
  191. #define PREINDEXED(opcode) ((opcode & BIT_PREINDEX) != 0)
  192. #define POSTINDEXED(opcode) ((opcode & BIT_PREINDEX) == 0)
  193. #define BIT_UP_SET(opcode) ((opcode & BIT_UP) != 0)
  194. #define BIT_UP_CLEAR(opcode) ((opcode & BIT_DOWN) == 0)
  195. #define WRITE_BACK(opcode) ((opcode & BIT_WRITE_BACK) != 0)
  196. #define LOAD(opcode) ((opcode & BIT_LOAD) != 0)
  197. #define STORE(opcode) ((opcode & BIT_LOAD) == 0)
  198. /*
  199. ===
  200. === Definitions for arithmetic instructions
  201. ===
  202. */
  203. /* bit masks */
  204. #define BIT_MONADIC 0x00008000
  205. #define BIT_CONSTANT 0x00000008
  206. #define CONSTANT_FM(opcode) ((opcode & BIT_CONSTANT) != 0)
  207. #define MONADIC_INSTRUCTION(opcode) ((opcode & BIT_MONADIC) != 0)
  208. /* instruction identification masks */
  209. #define MASK_CPDO 0x0e000000 /* arithmetic opcode */
  210. #define MASK_ARITHMETIC_OPCODE 0x00f08000
  211. #define MASK_DESTINATION_SIZE 0x00080080
  212. /* dyadic arithmetic opcodes. */
  213. #define ADF_CODE 0x00000000
  214. #define MUF_CODE 0x00100000
  215. #define SUF_CODE 0x00200000
  216. #define RSF_CODE 0x00300000
  217. #define DVF_CODE 0x00400000
  218. #define RDF_CODE 0x00500000
  219. #define POW_CODE 0x00600000
  220. #define RPW_CODE 0x00700000
  221. #define RMF_CODE 0x00800000
  222. #define FML_CODE 0x00900000
  223. #define FDV_CODE 0x00a00000
  224. #define FRD_CODE 0x00b00000
  225. #define POL_CODE 0x00c00000
  226. /* 0x00d00000 is an invalid dyadic arithmetic opcode */
  227. /* 0x00e00000 is an invalid dyadic arithmetic opcode */
  228. /* 0x00f00000 is an invalid dyadic arithmetic opcode */
  229. /* monadic arithmetic opcodes. */
  230. #define MVF_CODE 0x00008000
  231. #define MNF_CODE 0x00108000
  232. #define ABS_CODE 0x00208000
  233. #define RND_CODE 0x00308000
  234. #define SQT_CODE 0x00408000
  235. #define LOG_CODE 0x00508000
  236. #define LGN_CODE 0x00608000
  237. #define EXP_CODE 0x00708000
  238. #define SIN_CODE 0x00808000
  239. #define COS_CODE 0x00908000
  240. #define TAN_CODE 0x00a08000
  241. #define ASN_CODE 0x00b08000
  242. #define ACS_CODE 0x00c08000
  243. #define ATN_CODE 0x00d08000
  244. #define URD_CODE 0x00e08000
  245. #define NRM_CODE 0x00f08000
  246. /*
  247. ===
  248. === Definitions for register transfer and comparison instructions
  249. ===
  250. */
  251. #define MASK_CPRT 0x0e000010 /* register transfer opcode */
  252. #define MASK_CPRT_CODE 0x00f00000
  253. #define FLT_CODE 0x00000000
  254. #define FIX_CODE 0x00100000
  255. #define WFS_CODE 0x00200000
  256. #define RFS_CODE 0x00300000
  257. #define WFC_CODE 0x00400000
  258. #define RFC_CODE 0x00500000
  259. #define CMF_CODE 0x00900000
  260. #define CNF_CODE 0x00b00000
  261. #define CMFE_CODE 0x00d00000
  262. #define CNFE_CODE 0x00f00000
  263. /*
  264. ===
  265. === Common definitions
  266. ===
  267. */
  268. /* register masks */
  269. #define MASK_Rd 0x0000f000
  270. #define MASK_Rn 0x000f0000
  271. #define MASK_Fd 0x00007000
  272. #define MASK_Fm 0x00000007
  273. #define MASK_Fn 0x00070000
  274. /* condition code masks */
  275. #define CC_MASK 0xf0000000
  276. #define CC_NEGATIVE 0x80000000
  277. #define CC_ZERO 0x40000000
  278. #define CC_CARRY 0x20000000
  279. #define CC_OVERFLOW 0x10000000
  280. #define CC_EQ 0x00000000
  281. #define CC_NE 0x10000000
  282. #define CC_CS 0x20000000
  283. #define CC_HS CC_CS
  284. #define CC_CC 0x30000000
  285. #define CC_LO CC_CC
  286. #define CC_MI 0x40000000
  287. #define CC_PL 0x50000000
  288. #define CC_VS 0x60000000
  289. #define CC_VC 0x70000000
  290. #define CC_HI 0x80000000
  291. #define CC_LS 0x90000000
  292. #define CC_GE 0xa0000000
  293. #define CC_LT 0xb0000000
  294. #define CC_GT 0xc0000000
  295. #define CC_LE 0xd0000000
  296. #define CC_AL 0xe0000000
  297. #define CC_NV 0xf0000000
  298. /* rounding masks/values */
  299. #define MASK_ROUNDING_MODE 0x00000060
  300. #define ROUND_TO_NEAREST 0x00000000
  301. #define ROUND_TO_PLUS_INFINITY 0x00000020
  302. #define ROUND_TO_MINUS_INFINITY 0x00000040
  303. #define ROUND_TO_ZERO 0x00000060
  304. #define MASK_ROUNDING_PRECISION 0x00080080
  305. #define ROUND_SINGLE 0x00000000
  306. #define ROUND_DOUBLE 0x00000080
  307. #define ROUND_EXTENDED 0x00080000
  308. /* Get the condition code from the opcode. */
  309. #define getCondition(opcode) (opcode >> 28)
  310. /* Get the source register from the opcode. */
  311. #define getRn(opcode) ((opcode & MASK_Rn) >> 16)
  312. /* Get the destination floating point register from the opcode. */
  313. #define getFd(opcode) ((opcode & MASK_Fd) >> 12)
  314. /* Get the first source floating point register from the opcode. */
  315. #define getFn(opcode) ((opcode & MASK_Fn) >> 16)
  316. /* Get the second source floating point register from the opcode. */
  317. #define getFm(opcode) (opcode & MASK_Fm)
  318. /* Get the destination register from the opcode. */
  319. #define getRd(opcode) ((opcode & MASK_Rd) >> 12)
  320. /* Get the rounding mode from the opcode. */
  321. #define getRoundingMode(opcode) ((opcode & MASK_ROUNDING_MODE) >> 5)
  322. #ifdef CONFIG_FPE_NWFPE_XP
  323. static inline __attribute_pure__ floatx80 getExtendedConstant(const unsigned int nIndex)
  324. {
  325. extern const floatx80 floatx80Constant[];
  326. return floatx80Constant[nIndex];
  327. }
  328. #endif
  329. static inline __attribute_pure__ float64 getDoubleConstant(const unsigned int nIndex)
  330. {
  331. extern const float64 float64Constant[];
  332. return float64Constant[nIndex];
  333. }
  334. static inline __attribute_pure__ float32 getSingleConstant(const unsigned int nIndex)
  335. {
  336. extern const float32 float32Constant[];
  337. return float32Constant[nIndex];
  338. }
  339. static inline unsigned int getTransferLength(const unsigned int opcode)
  340. {
  341. unsigned int nRc;
  342. switch (opcode & MASK_TRANSFER_LENGTH) {
  343. case 0x00000000:
  344. nRc = 1;
  345. break; /* single precision */
  346. case 0x00008000:
  347. nRc = 2;
  348. break; /* double precision */
  349. case 0x00400000:
  350. nRc = 3;
  351. break; /* extended precision */
  352. default:
  353. nRc = 0;
  354. }
  355. return (nRc);
  356. }
  357. static inline unsigned int getRegisterCount(const unsigned int opcode)
  358. {
  359. unsigned int nRc;
  360. switch (opcode & MASK_REGISTER_COUNT) {
  361. case 0x00000000:
  362. nRc = 4;
  363. break;
  364. case 0x00008000:
  365. nRc = 1;
  366. break;
  367. case 0x00400000:
  368. nRc = 2;
  369. break;
  370. case 0x00408000:
  371. nRc = 3;
  372. break;
  373. default:
  374. nRc = 0;
  375. }
  376. return (nRc);
  377. }
  378. static inline unsigned int getRoundingPrecision(const unsigned int opcode)
  379. {
  380. unsigned int nRc;
  381. switch (opcode & MASK_ROUNDING_PRECISION) {
  382. case 0x00000000:
  383. nRc = 1;
  384. break;
  385. case 0x00000080:
  386. nRc = 2;
  387. break;
  388. case 0x00080000:
  389. nRc = 3;
  390. break;
  391. default:
  392. nRc = 0;
  393. }
  394. return (nRc);
  395. }
  396. static inline unsigned int getDestinationSize(const unsigned int opcode)
  397. {
  398. unsigned int nRc;
  399. switch (opcode & MASK_DESTINATION_SIZE) {
  400. case 0x00000000:
  401. nRc = typeSingle;
  402. break;
  403. case 0x00000080:
  404. nRc = typeDouble;
  405. break;
  406. case 0x00080000:
  407. nRc = typeExtended;
  408. break;
  409. default:
  410. nRc = typeNone;
  411. }
  412. return (nRc);
  413. }
  414. extern unsigned int checkCondition(const unsigned int opcode,
  415. const unsigned int ccodes);
  416. extern const float64 float64Constant[];
  417. extern const float32 float32Constant[];
  418. #endif