proc-xscale.S 24 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-xscale.S
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: November 2000
  6. * Copyright: (C) 2000, 2001 MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * MMU functions for the Intel XScale CPUs
  13. *
  14. * 2001 Aug 21:
  15. * some contributions by Brett Gaines <brett.w.gaines@intel.com>
  16. * Copyright 2001 by Intel Corp.
  17. *
  18. * 2001 Sep 08:
  19. * Completely revisited, many important fixes
  20. * Nicolas Pitre <nico@cam.org>
  21. */
  22. #include <linux/linkage.h>
  23. #include <linux/init.h>
  24. #include <asm/assembler.h>
  25. #include <asm/elf.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/pgtable-hwdef.h>
  28. #include <asm/page.h>
  29. #include <asm/ptrace.h>
  30. #include "proc-macros.S"
  31. /*
  32. * This is the maximum size of an area which will be flushed. If the area
  33. * is larger than this, then we flush the whole cache
  34. */
  35. #define MAX_AREA_SIZE 32768
  36. /*
  37. * the cache line size of the I and D cache
  38. */
  39. #define CACHELINESIZE 32
  40. /*
  41. * the size of the data cache
  42. */
  43. #define CACHESIZE 32768
  44. /*
  45. * Virtual address used to allocate the cache when flushed
  46. *
  47. * This must be an address range which is _never_ used. It should
  48. * apparently have a mapping in the corresponding page table for
  49. * compatibility with future CPUs that _could_ require it. For instance we
  50. * don't care.
  51. *
  52. * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
  53. * the 2 areas in alternance each time the clean_d_cache macro is used.
  54. * Without this the XScale core exhibits cache eviction problems and no one
  55. * knows why.
  56. *
  57. * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
  58. */
  59. #define CLEAN_ADDR 0xfffe0000
  60. /*
  61. * This macro is used to wait for a CP15 write and is needed
  62. * when we have to ensure that the last operation to the co-pro
  63. * was completed before continuing with operation.
  64. */
  65. .macro cpwait, rd
  66. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  67. mov \rd, \rd @ wait for completion
  68. sub pc, pc, #4 @ flush instruction pipeline
  69. .endm
  70. .macro cpwait_ret, lr, rd
  71. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  72. sub pc, \lr, \rd, LSR #32 @ wait for completion and
  73. @ flush instruction pipeline
  74. .endm
  75. /*
  76. * This macro cleans the entire dcache using line allocate.
  77. * The main loop has been unrolled to reduce loop overhead.
  78. * rd and rs are two scratch registers.
  79. */
  80. .macro clean_d_cache, rd, rs
  81. ldr \rs, =clean_addr
  82. ldr \rd, [\rs]
  83. eor \rd, \rd, #CACHESIZE
  84. str \rd, [\rs]
  85. add \rs, \rd, #CACHESIZE
  86. 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  87. add \rd, \rd, #CACHELINESIZE
  88. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  89. add \rd, \rd, #CACHELINESIZE
  90. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  91. add \rd, \rd, #CACHELINESIZE
  92. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  93. add \rd, \rd, #CACHELINESIZE
  94. teq \rd, \rs
  95. bne 1b
  96. .endm
  97. .data
  98. clean_addr: .word CLEAN_ADDR
  99. .text
  100. /*
  101. * cpu_xscale_proc_init()
  102. *
  103. * Nothing too exciting at the moment
  104. */
  105. ENTRY(cpu_xscale_proc_init)
  106. mov pc, lr
  107. /*
  108. * cpu_xscale_proc_fin()
  109. */
  110. ENTRY(cpu_xscale_proc_fin)
  111. str lr, [sp, #-4]!
  112. mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  113. msr cpsr_c, r0
  114. bl xscale_flush_kern_cache_all @ clean caches
  115. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  116. bic r0, r0, #0x1800 @ ...IZ...........
  117. bic r0, r0, #0x0006 @ .............CA.
  118. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  119. ldr pc, [sp], #4
  120. /*
  121. * cpu_xscale_reset(loc)
  122. *
  123. * Perform a soft reset of the system. Put the CPU into the
  124. * same state as it would be if it had been reset, and branch
  125. * to what would be the reset vector.
  126. *
  127. * loc: location to jump to for soft reset
  128. *
  129. * Beware PXA270 erratum E7.
  130. */
  131. .align 5
  132. ENTRY(cpu_xscale_reset)
  133. mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  134. msr cpsr_c, r1 @ reset CPSR
  135. mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
  136. mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
  137. mrc p15, 0, r1, c1, c0, 0 @ ctrl register
  138. bic r1, r1, #0x0086 @ ........B....CA.
  139. bic r1, r1, #0x3900 @ ..VIZ..S........
  140. sub pc, pc, #4 @ flush pipeline
  141. @ *** cache line aligned ***
  142. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  143. bic r1, r1, #0x0001 @ ...............M
  144. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
  145. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  146. @ CAUTION: MMU turned off from this point. We count on the pipeline
  147. @ already containing those two last instructions to survive.
  148. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  149. mov pc, r0
  150. /*
  151. * cpu_xscale_do_idle()
  152. *
  153. * Cause the processor to idle
  154. *
  155. * For now we do nothing but go to idle mode for every case
  156. *
  157. * XScale supports clock switching, but using idle mode support
  158. * allows external hardware to react to system state changes.
  159. */
  160. .align 5
  161. ENTRY(cpu_xscale_do_idle)
  162. mov r0, #1
  163. mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
  164. mov pc, lr
  165. /* ================================= CACHE ================================ */
  166. /*
  167. * flush_user_cache_all()
  168. *
  169. * Invalidate all cache entries in a particular address
  170. * space.
  171. */
  172. ENTRY(xscale_flush_user_cache_all)
  173. /* FALLTHROUGH */
  174. /*
  175. * flush_kern_cache_all()
  176. *
  177. * Clean and invalidate the entire cache.
  178. */
  179. ENTRY(xscale_flush_kern_cache_all)
  180. mov r2, #VM_EXEC
  181. mov ip, #0
  182. __flush_whole_cache:
  183. clean_d_cache r0, r1
  184. tst r2, #VM_EXEC
  185. mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  186. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  187. mov pc, lr
  188. /*
  189. * flush_user_cache_range(start, end, vm_flags)
  190. *
  191. * Invalidate a range of cache entries in the specified
  192. * address space.
  193. *
  194. * - start - start address (may not be aligned)
  195. * - end - end address (exclusive, may not be aligned)
  196. * - vma - vma_area_struct describing address space
  197. */
  198. .align 5
  199. ENTRY(xscale_flush_user_cache_range)
  200. mov ip, #0
  201. sub r3, r1, r0 @ calculate total size
  202. cmp r3, #MAX_AREA_SIZE
  203. bhs __flush_whole_cache
  204. 1: tst r2, #VM_EXEC
  205. mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
  206. mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
  207. mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
  208. add r0, r0, #CACHELINESIZE
  209. cmp r0, r1
  210. blo 1b
  211. tst r2, #VM_EXEC
  212. mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
  213. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  214. mov pc, lr
  215. /*
  216. * coherent_kern_range(start, end)
  217. *
  218. * Ensure coherency between the Icache and the Dcache in the
  219. * region described by start. If you have non-snooping
  220. * Harvard caches, you need to implement this function.
  221. *
  222. * - start - virtual start address
  223. * - end - virtual end address
  224. *
  225. * Note: single I-cache line invalidation isn't used here since
  226. * it also trashes the mini I-cache used by JTAG debuggers.
  227. */
  228. ENTRY(xscale_coherent_kern_range)
  229. bic r0, r0, #CACHELINESIZE - 1
  230. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  231. add r0, r0, #CACHELINESIZE
  232. cmp r0, r1
  233. blo 1b
  234. mov r0, #0
  235. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  236. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  237. mov pc, lr
  238. /*
  239. * coherent_user_range(start, end)
  240. *
  241. * Ensure coherency between the Icache and the Dcache in the
  242. * region described by start. If you have non-snooping
  243. * Harvard caches, you need to implement this function.
  244. *
  245. * - start - virtual start address
  246. * - end - virtual end address
  247. */
  248. ENTRY(xscale_coherent_user_range)
  249. bic r0, r0, #CACHELINESIZE - 1
  250. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  251. mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
  252. add r0, r0, #CACHELINESIZE
  253. cmp r0, r1
  254. blo 1b
  255. mov r0, #0
  256. mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
  257. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  258. mov pc, lr
  259. /*
  260. * flush_kern_dcache_page(void *page)
  261. *
  262. * Ensure no D cache aliasing occurs, either with itself or
  263. * the I cache
  264. *
  265. * - addr - page aligned address
  266. */
  267. ENTRY(xscale_flush_kern_dcache_page)
  268. add r1, r0, #PAGE_SZ
  269. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  270. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  271. add r0, r0, #CACHELINESIZE
  272. cmp r0, r1
  273. blo 1b
  274. mov r0, #0
  275. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  276. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  277. mov pc, lr
  278. /*
  279. * dma_inv_range(start, end)
  280. *
  281. * Invalidate (discard) the specified virtual address range.
  282. * May not write back any entries. If 'start' or 'end'
  283. * are not cache line aligned, those lines must be written
  284. * back.
  285. *
  286. * - start - virtual start address
  287. * - end - virtual end address
  288. */
  289. ENTRY(xscale_dma_inv_range)
  290. tst r0, #CACHELINESIZE - 1
  291. bic r0, r0, #CACHELINESIZE - 1
  292. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  293. tst r1, #CACHELINESIZE - 1
  294. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  295. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  296. add r0, r0, #CACHELINESIZE
  297. cmp r0, r1
  298. blo 1b
  299. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  300. mov pc, lr
  301. /*
  302. * dma_clean_range(start, end)
  303. *
  304. * Clean the specified virtual address range.
  305. *
  306. * - start - virtual start address
  307. * - end - virtual end address
  308. */
  309. ENTRY(xscale_dma_clean_range)
  310. bic r0, r0, #CACHELINESIZE - 1
  311. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  312. add r0, r0, #CACHELINESIZE
  313. cmp r0, r1
  314. blo 1b
  315. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  316. mov pc, lr
  317. /*
  318. * dma_flush_range(start, end)
  319. *
  320. * Clean and invalidate the specified virtual address range.
  321. *
  322. * - start - virtual start address
  323. * - end - virtual end address
  324. */
  325. ENTRY(xscale_dma_flush_range)
  326. bic r0, r0, #CACHELINESIZE - 1
  327. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  328. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  329. add r0, r0, #CACHELINESIZE
  330. cmp r0, r1
  331. blo 1b
  332. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  333. mov pc, lr
  334. ENTRY(xscale_cache_fns)
  335. .long xscale_flush_kern_cache_all
  336. .long xscale_flush_user_cache_all
  337. .long xscale_flush_user_cache_range
  338. .long xscale_coherent_kern_range
  339. .long xscale_coherent_user_range
  340. .long xscale_flush_kern_dcache_page
  341. .long xscale_dma_inv_range
  342. .long xscale_dma_clean_range
  343. .long xscale_dma_flush_range
  344. /*
  345. * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
  346. * clear the dirty bits, which means that if we invalidate a dirty line,
  347. * the dirty data can still be written back to external memory later on.
  348. *
  349. * The recommended workaround is to always do a clean D-cache line before
  350. * doing an invalidate D-cache line, so on the affected processors,
  351. * dma_inv_range() is implemented as dma_flush_range().
  352. *
  353. * See erratum #25 of "Intel 80200 Processor Specification Update",
  354. * revision January 22, 2003, available at:
  355. * http://www.intel.com/design/iio/specupdt/273415.htm
  356. */
  357. ENTRY(xscale_80200_A0_A1_cache_fns)
  358. .long xscale_flush_kern_cache_all
  359. .long xscale_flush_user_cache_all
  360. .long xscale_flush_user_cache_range
  361. .long xscale_coherent_kern_range
  362. .long xscale_coherent_user_range
  363. .long xscale_flush_kern_dcache_page
  364. .long xscale_dma_flush_range
  365. .long xscale_dma_clean_range
  366. .long xscale_dma_flush_range
  367. ENTRY(cpu_xscale_dcache_clean_area)
  368. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  369. add r0, r0, #CACHELINESIZE
  370. subs r1, r1, #CACHELINESIZE
  371. bhi 1b
  372. mov pc, lr
  373. /* =============================== PageTable ============================== */
  374. #define PTE_CACHE_WRITE_ALLOCATE 0
  375. /*
  376. * cpu_xscale_switch_mm(pgd)
  377. *
  378. * Set the translation base pointer to be as described by pgd.
  379. *
  380. * pgd: new page tables
  381. */
  382. .align 5
  383. ENTRY(cpu_xscale_switch_mm)
  384. clean_d_cache r1, r2
  385. mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  386. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  387. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  388. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  389. cpwait_ret lr, ip
  390. /*
  391. * cpu_xscale_set_pte_ext(ptep, pte, ext)
  392. *
  393. * Set a PTE and flush it out
  394. *
  395. * Errata 40: must set memory to write-through for user read-only pages.
  396. */
  397. .align 5
  398. ENTRY(cpu_xscale_set_pte_ext)
  399. str r1, [r0], #-2048 @ linux version
  400. bic r2, r1, #0xff0
  401. orr r2, r2, #PTE_TYPE_EXT @ extended page
  402. eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  403. tst r3, #L_PTE_USER @ User?
  404. orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
  405. tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  406. orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
  407. @ combined with user -> user r/w
  408. @
  409. @ Handle the X bit. We want to set this bit for the minicache
  410. @ (U = E = B = W = 0, C = 1) or when write allocate is enabled,
  411. @ and we have a writeable, cacheable region. If we ignore the
  412. @ U and E bits, we can allow user space to use the minicache as
  413. @ well.
  414. @
  415. @ X = (C & ~W & ~B) | (C & W & B & write_allocate)
  416. @
  417. eor ip, r1, #L_PTE_CACHEABLE
  418. tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  419. #if PTE_CACHE_WRITE_ALLOCATE
  420. eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  421. tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE
  422. #endif
  423. orreq r2, r2, #PTE_EXT_TEX(1)
  424. @
  425. @ Erratum 40: The B bit must be cleared for a user read-only
  426. @ cacheable page.
  427. @
  428. @ B = B & ~(U & C & ~W)
  429. @
  430. and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE
  431. teq ip, #L_PTE_USER | L_PTE_CACHEABLE
  432. biceq r2, r2, #PTE_BUFFERABLE
  433. tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  434. movne r2, #0 @ no -> fault
  435. str r2, [r0] @ hardware version
  436. mov ip, #0
  437. mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
  438. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  439. mov pc, lr
  440. .ltorg
  441. .align
  442. __INIT
  443. .type __xscale_setup, #function
  444. __xscale_setup:
  445. mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
  446. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  447. mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
  448. mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
  449. orr r0, r0, #1 << 13 @ Its undefined whether this
  450. mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
  451. adr r5, xscale_crval
  452. ldmia r5, {r5, r6}
  453. mrc p15, 0, r0, c1, c0, 0 @ get control register
  454. bic r0, r0, r5
  455. orr r0, r0, r6
  456. mov pc, lr
  457. .size __xscale_setup, . - __xscale_setup
  458. /*
  459. * R
  460. * .RVI ZFRS BLDP WCAM
  461. * ..11 1.01 .... .101
  462. *
  463. */
  464. .type xscale_crval, #object
  465. xscale_crval:
  466. crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
  467. __INITDATA
  468. /*
  469. * Purpose : Function pointers used to access above functions - all calls
  470. * come through these
  471. */
  472. .type xscale_processor_functions, #object
  473. ENTRY(xscale_processor_functions)
  474. .word v5t_early_abort
  475. .word cpu_xscale_proc_init
  476. .word cpu_xscale_proc_fin
  477. .word cpu_xscale_reset
  478. .word cpu_xscale_do_idle
  479. .word cpu_xscale_dcache_clean_area
  480. .word cpu_xscale_switch_mm
  481. .word cpu_xscale_set_pte_ext
  482. .size xscale_processor_functions, . - xscale_processor_functions
  483. .section ".rodata"
  484. .type cpu_arch_name, #object
  485. cpu_arch_name:
  486. .asciz "armv5te"
  487. .size cpu_arch_name, . - cpu_arch_name
  488. .type cpu_elf_name, #object
  489. cpu_elf_name:
  490. .asciz "v5"
  491. .size cpu_elf_name, . - cpu_elf_name
  492. .type cpu_80200_A0_A1_name, #object
  493. cpu_80200_A0_A1_name:
  494. .asciz "XScale-80200 A0/A1"
  495. .size cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
  496. .type cpu_80200_name, #object
  497. cpu_80200_name:
  498. .asciz "XScale-80200"
  499. .size cpu_80200_name, . - cpu_80200_name
  500. .type cpu_80219_name, #object
  501. cpu_80219_name:
  502. .asciz "XScale-80219"
  503. .size cpu_80219_name, . - cpu_80219_name
  504. .type cpu_8032x_name, #object
  505. cpu_8032x_name:
  506. .asciz "XScale-IOP8032x Family"
  507. .size cpu_8032x_name, . - cpu_8032x_name
  508. .type cpu_8033x_name, #object
  509. cpu_8033x_name:
  510. .asciz "XScale-IOP8033x Family"
  511. .size cpu_8033x_name, . - cpu_8033x_name
  512. .type cpu_pxa250_name, #object
  513. cpu_pxa250_name:
  514. .asciz "XScale-PXA250"
  515. .size cpu_pxa250_name, . - cpu_pxa250_name
  516. .type cpu_pxa210_name, #object
  517. cpu_pxa210_name:
  518. .asciz "XScale-PXA210"
  519. .size cpu_pxa210_name, . - cpu_pxa210_name
  520. .type cpu_ixp42x_name, #object
  521. cpu_ixp42x_name:
  522. .asciz "XScale-IXP42x Family"
  523. .size cpu_ixp42x_name, . - cpu_ixp42x_name
  524. .type cpu_ixp46x_name, #object
  525. cpu_ixp46x_name:
  526. .asciz "XScale-IXP46x Family"
  527. .size cpu_ixp46x_name, . - cpu_ixp46x_name
  528. .type cpu_ixp2400_name, #object
  529. cpu_ixp2400_name:
  530. .asciz "XScale-IXP2400"
  531. .size cpu_ixp2400_name, . - cpu_ixp2400_name
  532. .type cpu_ixp2800_name, #object
  533. cpu_ixp2800_name:
  534. .asciz "XScale-IXP2800"
  535. .size cpu_ixp2800_name, . - cpu_ixp2800_name
  536. .type cpu_pxa255_name, #object
  537. cpu_pxa255_name:
  538. .asciz "XScale-PXA255"
  539. .size cpu_pxa255_name, . - cpu_pxa255_name
  540. .type cpu_pxa270_name, #object
  541. cpu_pxa270_name:
  542. .asciz "XScale-PXA270"
  543. .size cpu_pxa270_name, . - cpu_pxa270_name
  544. .align
  545. .section ".proc.info.init", #alloc, #execinstr
  546. .type __80200_A0_A1_proc_info,#object
  547. __80200_A0_A1_proc_info:
  548. .long 0x69052000
  549. .long 0xfffffffe
  550. .long PMD_TYPE_SECT | \
  551. PMD_SECT_BUFFERABLE | \
  552. PMD_SECT_CACHEABLE | \
  553. PMD_SECT_AP_WRITE | \
  554. PMD_SECT_AP_READ
  555. .long PMD_TYPE_SECT | \
  556. PMD_SECT_AP_WRITE | \
  557. PMD_SECT_AP_READ
  558. b __xscale_setup
  559. .long cpu_arch_name
  560. .long cpu_elf_name
  561. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  562. .long cpu_80200_name
  563. .long xscale_processor_functions
  564. .long v4wbi_tlb_fns
  565. .long xscale_mc_user_fns
  566. .long xscale_80200_A0_A1_cache_fns
  567. .size __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
  568. .type __80200_proc_info,#object
  569. __80200_proc_info:
  570. .long 0x69052000
  571. .long 0xfffffff0
  572. .long PMD_TYPE_SECT | \
  573. PMD_SECT_BUFFERABLE | \
  574. PMD_SECT_CACHEABLE | \
  575. PMD_SECT_AP_WRITE | \
  576. PMD_SECT_AP_READ
  577. .long PMD_TYPE_SECT | \
  578. PMD_SECT_AP_WRITE | \
  579. PMD_SECT_AP_READ
  580. b __xscale_setup
  581. .long cpu_arch_name
  582. .long cpu_elf_name
  583. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  584. .long cpu_80200_name
  585. .long xscale_processor_functions
  586. .long v4wbi_tlb_fns
  587. .long xscale_mc_user_fns
  588. .long xscale_cache_fns
  589. .size __80200_proc_info, . - __80200_proc_info
  590. .type __80219_proc_info,#object
  591. __80219_proc_info:
  592. .long 0x69052e20
  593. .long 0xffffffe0
  594. .long PMD_TYPE_SECT | \
  595. PMD_SECT_BUFFERABLE | \
  596. PMD_SECT_CACHEABLE | \
  597. PMD_SECT_AP_WRITE | \
  598. PMD_SECT_AP_READ
  599. .long PMD_TYPE_SECT | \
  600. PMD_SECT_AP_WRITE | \
  601. PMD_SECT_AP_READ
  602. b __xscale_setup
  603. .long cpu_arch_name
  604. .long cpu_elf_name
  605. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  606. .long cpu_80219_name
  607. .long xscale_processor_functions
  608. .long v4wbi_tlb_fns
  609. .long xscale_mc_user_fns
  610. .long xscale_cache_fns
  611. .size __80219_proc_info, . - __80219_proc_info
  612. .type __8032x_proc_info,#object
  613. __8032x_proc_info:
  614. .long 0x69052420
  615. .long 0xfffff7e0
  616. .long PMD_TYPE_SECT | \
  617. PMD_SECT_BUFFERABLE | \
  618. PMD_SECT_CACHEABLE | \
  619. PMD_SECT_AP_WRITE | \
  620. PMD_SECT_AP_READ
  621. .long PMD_TYPE_SECT | \
  622. PMD_SECT_AP_WRITE | \
  623. PMD_SECT_AP_READ
  624. b __xscale_setup
  625. .long cpu_arch_name
  626. .long cpu_elf_name
  627. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  628. .long cpu_8032x_name
  629. .long xscale_processor_functions
  630. .long v4wbi_tlb_fns
  631. .long xscale_mc_user_fns
  632. .long xscale_cache_fns
  633. .size __8032x_proc_info, . - __8032x_proc_info
  634. .type __8033x_proc_info,#object
  635. __8033x_proc_info:
  636. .long 0x69054010
  637. .long 0xfffffd30
  638. .long PMD_TYPE_SECT | \
  639. PMD_SECT_BUFFERABLE | \
  640. PMD_SECT_CACHEABLE | \
  641. PMD_SECT_AP_WRITE | \
  642. PMD_SECT_AP_READ
  643. .long PMD_TYPE_SECT | \
  644. PMD_SECT_AP_WRITE | \
  645. PMD_SECT_AP_READ
  646. b __xscale_setup
  647. .long cpu_arch_name
  648. .long cpu_elf_name
  649. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  650. .long cpu_8033x_name
  651. .long xscale_processor_functions
  652. .long v4wbi_tlb_fns
  653. .long xscale_mc_user_fns
  654. .long xscale_cache_fns
  655. .size __8033x_proc_info, . - __8033x_proc_info
  656. .type __pxa250_proc_info,#object
  657. __pxa250_proc_info:
  658. .long 0x69052100
  659. .long 0xfffff7f0
  660. .long PMD_TYPE_SECT | \
  661. PMD_SECT_BUFFERABLE | \
  662. PMD_SECT_CACHEABLE | \
  663. PMD_SECT_AP_WRITE | \
  664. PMD_SECT_AP_READ
  665. .long PMD_TYPE_SECT | \
  666. PMD_SECT_AP_WRITE | \
  667. PMD_SECT_AP_READ
  668. b __xscale_setup
  669. .long cpu_arch_name
  670. .long cpu_elf_name
  671. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  672. .long cpu_pxa250_name
  673. .long xscale_processor_functions
  674. .long v4wbi_tlb_fns
  675. .long xscale_mc_user_fns
  676. .long xscale_cache_fns
  677. .size __pxa250_proc_info, . - __pxa250_proc_info
  678. .type __pxa210_proc_info,#object
  679. __pxa210_proc_info:
  680. .long 0x69052120
  681. .long 0xfffff3f0
  682. .long PMD_TYPE_SECT | \
  683. PMD_SECT_BUFFERABLE | \
  684. PMD_SECT_CACHEABLE | \
  685. PMD_SECT_AP_WRITE | \
  686. PMD_SECT_AP_READ
  687. .long PMD_TYPE_SECT | \
  688. PMD_SECT_AP_WRITE | \
  689. PMD_SECT_AP_READ
  690. b __xscale_setup
  691. .long cpu_arch_name
  692. .long cpu_elf_name
  693. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  694. .long cpu_pxa210_name
  695. .long xscale_processor_functions
  696. .long v4wbi_tlb_fns
  697. .long xscale_mc_user_fns
  698. .long xscale_cache_fns
  699. .size __pxa210_proc_info, . - __pxa210_proc_info
  700. .type __ixp2400_proc_info, #object
  701. __ixp2400_proc_info:
  702. .long 0x69054190
  703. .long 0xfffffff0
  704. .long PMD_TYPE_SECT | \
  705. PMD_SECT_BUFFERABLE | \
  706. PMD_SECT_CACHEABLE | \
  707. PMD_SECT_AP_WRITE | \
  708. PMD_SECT_AP_READ
  709. .long PMD_TYPE_SECT | \
  710. PMD_SECT_AP_WRITE | \
  711. PMD_SECT_AP_READ
  712. b __xscale_setup
  713. .long cpu_arch_name
  714. .long cpu_elf_name
  715. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  716. .long cpu_ixp2400_name
  717. .long xscale_processor_functions
  718. .long v4wbi_tlb_fns
  719. .long xscale_mc_user_fns
  720. .long xscale_cache_fns
  721. .size __ixp2400_proc_info, . - __ixp2400_proc_info
  722. .type __ixp2800_proc_info, #object
  723. __ixp2800_proc_info:
  724. .long 0x690541a0
  725. .long 0xfffffff0
  726. .long PMD_TYPE_SECT | \
  727. PMD_SECT_BUFFERABLE | \
  728. PMD_SECT_CACHEABLE | \
  729. PMD_SECT_AP_WRITE | \
  730. PMD_SECT_AP_READ
  731. .long PMD_TYPE_SECT | \
  732. PMD_SECT_AP_WRITE | \
  733. PMD_SECT_AP_READ
  734. b __xscale_setup
  735. .long cpu_arch_name
  736. .long cpu_elf_name
  737. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  738. .long cpu_ixp2800_name
  739. .long xscale_processor_functions
  740. .long v4wbi_tlb_fns
  741. .long xscale_mc_user_fns
  742. .long xscale_cache_fns
  743. .size __ixp2800_proc_info, . - __ixp2800_proc_info
  744. .type __ixp42x_proc_info, #object
  745. __ixp42x_proc_info:
  746. .long 0x690541c0
  747. .long 0xffffffc0
  748. .long PMD_TYPE_SECT | \
  749. PMD_SECT_BUFFERABLE | \
  750. PMD_SECT_CACHEABLE | \
  751. PMD_SECT_AP_WRITE | \
  752. PMD_SECT_AP_READ
  753. .long PMD_TYPE_SECT | \
  754. PMD_SECT_AP_WRITE | \
  755. PMD_SECT_AP_READ
  756. b __xscale_setup
  757. .long cpu_arch_name
  758. .long cpu_elf_name
  759. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  760. .long cpu_ixp42x_name
  761. .long xscale_processor_functions
  762. .long v4wbi_tlb_fns
  763. .long xscale_mc_user_fns
  764. .long xscale_cache_fns
  765. .size __ixp42x_proc_info, . - __ixp42x_proc_info
  766. .type __ixp46x_proc_info, #object
  767. __ixp46x_proc_info:
  768. .long 0x69054200
  769. .long 0xffffff00
  770. .long PMD_TYPE_SECT | \
  771. PMD_SECT_BUFFERABLE | \
  772. PMD_SECT_CACHEABLE | \
  773. PMD_SECT_AP_WRITE | \
  774. PMD_SECT_AP_READ
  775. .long PMD_TYPE_SECT | \
  776. PMD_SECT_AP_WRITE | \
  777. PMD_SECT_AP_READ
  778. b __xscale_setup
  779. .long cpu_arch_name
  780. .long cpu_elf_name
  781. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  782. .long cpu_ixp46x_name
  783. .long xscale_processor_functions
  784. .long v4wbi_tlb_fns
  785. .long xscale_mc_user_fns
  786. .long xscale_cache_fns
  787. .size __ixp46x_proc_info, . - __ixp46x_proc_info
  788. .type __pxa255_proc_info,#object
  789. __pxa255_proc_info:
  790. .long 0x69052d00
  791. .long 0xfffffff0
  792. .long PMD_TYPE_SECT | \
  793. PMD_SECT_BUFFERABLE | \
  794. PMD_SECT_CACHEABLE | \
  795. PMD_SECT_AP_WRITE | \
  796. PMD_SECT_AP_READ
  797. .long PMD_TYPE_SECT | \
  798. PMD_SECT_AP_WRITE | \
  799. PMD_SECT_AP_READ
  800. b __xscale_setup
  801. .long cpu_arch_name
  802. .long cpu_elf_name
  803. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  804. .long cpu_pxa255_name
  805. .long xscale_processor_functions
  806. .long v4wbi_tlb_fns
  807. .long xscale_mc_user_fns
  808. .long xscale_cache_fns
  809. .size __pxa255_proc_info, . - __pxa255_proc_info
  810. .type __pxa270_proc_info,#object
  811. __pxa270_proc_info:
  812. .long 0x69054110
  813. .long 0xfffffff0
  814. .long PMD_TYPE_SECT | \
  815. PMD_SECT_BUFFERABLE | \
  816. PMD_SECT_CACHEABLE | \
  817. PMD_SECT_AP_WRITE | \
  818. PMD_SECT_AP_READ
  819. .long PMD_TYPE_SECT | \
  820. PMD_SECT_AP_WRITE | \
  821. PMD_SECT_AP_READ
  822. b __xscale_setup
  823. .long cpu_arch_name
  824. .long cpu_elf_name
  825. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  826. .long cpu_pxa270_name
  827. .long xscale_processor_functions
  828. .long v4wbi_tlb_fns
  829. .long xscale_mc_user_fns
  830. .long xscale_cache_fns
  831. .size __pxa270_proc_info, . - __pxa270_proc_info