proc-xsc3.S 13 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-xsc3.S
  3. *
  4. * Original Author: Matthew Gilbert
  5. * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
  6. *
  7. * Copyright 2004 (C) Intel Corp.
  8. * Copyright 2005 (C) MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
  15. * an extension to Intel's original XScale core that adds the following
  16. * features:
  17. *
  18. * - ARMv6 Supersections
  19. * - Low Locality Reference pages (replaces mini-cache)
  20. * - 36-bit addressing
  21. * - L2 cache
  22. * - Cache coherency if chipset supports it
  23. *
  24. * Based on original XScale code by Nicolas Pitre.
  25. */
  26. #include <linux/linkage.h>
  27. #include <linux/init.h>
  28. #include <asm/assembler.h>
  29. #include <asm/elf.h>
  30. #include <asm/hardware.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/pgtable-hwdef.h>
  33. #include <asm/page.h>
  34. #include <asm/ptrace.h>
  35. #include "proc-macros.S"
  36. /*
  37. * This is the maximum size of an area which will be flushed. If the
  38. * area is larger than this, then we flush the whole cache.
  39. */
  40. #define MAX_AREA_SIZE 32768
  41. /*
  42. * The cache line size of the L1 I, L1 D and unified L2 cache.
  43. */
  44. #define CACHELINESIZE 32
  45. /*
  46. * The size of the L1 D cache.
  47. */
  48. #define CACHESIZE 32768
  49. /*
  50. * Run with L2 enabled.
  51. */
  52. #define L2_CACHE_ENABLE 1
  53. /*
  54. * This macro is used to wait for a CP15 write and is needed when we
  55. * have to ensure that the last operation to the coprocessor was
  56. * completed before continuing with operation.
  57. */
  58. .macro cpwait_ret, lr, rd
  59. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  60. sub pc, \lr, \rd, LSR #32 @ wait for completion and
  61. @ flush instruction pipeline
  62. .endm
  63. /*
  64. * This macro cleans and invalidates the entire L1 D cache.
  65. */
  66. .macro clean_d_cache rd, rs
  67. mov \rd, #0x1f00
  68. orr \rd, \rd, #0x00e0
  69. 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
  70. adds \rd, \rd, #0x40000000
  71. bcc 1b
  72. subs \rd, \rd, #0x20
  73. bpl 1b
  74. .endm
  75. .text
  76. /*
  77. * cpu_xsc3_proc_init()
  78. *
  79. * Nothing too exciting at the moment
  80. */
  81. ENTRY(cpu_xsc3_proc_init)
  82. mov pc, lr
  83. /*
  84. * cpu_xsc3_proc_fin()
  85. */
  86. ENTRY(cpu_xsc3_proc_fin)
  87. str lr, [sp, #-4]!
  88. mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  89. msr cpsr_c, r0
  90. bl xsc3_flush_kern_cache_all @ clean caches
  91. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  92. bic r0, r0, #0x1800 @ ...IZ...........
  93. bic r0, r0, #0x0006 @ .............CA.
  94. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  95. ldr pc, [sp], #4
  96. /*
  97. * cpu_xsc3_reset(loc)
  98. *
  99. * Perform a soft reset of the system. Put the CPU into the
  100. * same state as it would be if it had been reset, and branch
  101. * to what would be the reset vector.
  102. *
  103. * loc: location to jump to for soft reset
  104. */
  105. .align 5
  106. ENTRY(cpu_xsc3_reset)
  107. mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  108. msr cpsr_c, r1 @ reset CPSR
  109. mrc p15, 0, r1, c1, c0, 0 @ ctrl register
  110. bic r1, r1, #0x3900 @ ..VIZ..S........
  111. bic r1, r1, #0x0086 @ ........B....CA.
  112. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  113. mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
  114. bic r1, r1, #0x0001 @ ...............M
  115. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  116. @ CAUTION: MMU turned off from this point. We count on the pipeline
  117. @ already containing those two last instructions to survive.
  118. mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
  119. mov pc, r0
  120. /*
  121. * cpu_xsc3_do_idle()
  122. *
  123. * Cause the processor to idle
  124. *
  125. * For now we do nothing but go to idle mode for every case
  126. *
  127. * XScale supports clock switching, but using idle mode support
  128. * allows external hardware to react to system state changes.
  129. */
  130. .align 5
  131. ENTRY(cpu_xsc3_do_idle)
  132. mov r0, #1
  133. mcr p14, 0, r0, c7, c0, 0 @ go to idle
  134. mov pc, lr
  135. /* ================================= CACHE ================================ */
  136. /*
  137. * flush_user_cache_all()
  138. *
  139. * Invalidate all cache entries in a particular address
  140. * space.
  141. */
  142. ENTRY(xsc3_flush_user_cache_all)
  143. /* FALLTHROUGH */
  144. /*
  145. * flush_kern_cache_all()
  146. *
  147. * Clean and invalidate the entire cache.
  148. */
  149. ENTRY(xsc3_flush_kern_cache_all)
  150. mov r2, #VM_EXEC
  151. mov ip, #0
  152. __flush_whole_cache:
  153. clean_d_cache r0, r1
  154. tst r2, #VM_EXEC
  155. mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
  156. mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
  157. mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
  158. mov pc, lr
  159. /*
  160. * flush_user_cache_range(start, end, vm_flags)
  161. *
  162. * Invalidate a range of cache entries in the specified
  163. * address space.
  164. *
  165. * - start - start address (may not be aligned)
  166. * - end - end address (exclusive, may not be aligned)
  167. * - vma - vma_area_struct describing address space
  168. */
  169. .align 5
  170. ENTRY(xsc3_flush_user_cache_range)
  171. mov ip, #0
  172. sub r3, r1, r0 @ calculate total size
  173. cmp r3, #MAX_AREA_SIZE
  174. bhs __flush_whole_cache
  175. 1: tst r2, #VM_EXEC
  176. mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
  177. mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
  178. add r0, r0, #CACHELINESIZE
  179. cmp r0, r1
  180. blo 1b
  181. tst r2, #VM_EXEC
  182. mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
  183. mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
  184. mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
  185. mov pc, lr
  186. /*
  187. * coherent_kern_range(start, end)
  188. *
  189. * Ensure coherency between the I cache and the D cache in the
  190. * region described by start. If you have non-snooping
  191. * Harvard caches, you need to implement this function.
  192. *
  193. * - start - virtual start address
  194. * - end - virtual end address
  195. *
  196. * Note: single I-cache line invalidation isn't used here since
  197. * it also trashes the mini I-cache used by JTAG debuggers.
  198. */
  199. ENTRY(xsc3_coherent_kern_range)
  200. /* FALLTHROUGH */
  201. ENTRY(xsc3_coherent_user_range)
  202. bic r0, r0, #CACHELINESIZE - 1
  203. 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
  204. add r0, r0, #CACHELINESIZE
  205. cmp r0, r1
  206. blo 1b
  207. mov r0, #0
  208. mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
  209. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  210. mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
  211. mov pc, lr
  212. /*
  213. * flush_kern_dcache_page(void *page)
  214. *
  215. * Ensure no D cache aliasing occurs, either with itself or
  216. * the I cache.
  217. *
  218. * - addr - page aligned address
  219. */
  220. ENTRY(xsc3_flush_kern_dcache_page)
  221. add r1, r0, #PAGE_SZ
  222. 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
  223. add r0, r0, #CACHELINESIZE
  224. cmp r0, r1
  225. blo 1b
  226. mov r0, #0
  227. mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
  228. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  229. mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
  230. mov pc, lr
  231. /*
  232. * dma_inv_range(start, end)
  233. *
  234. * Invalidate (discard) the specified virtual address range.
  235. * May not write back any entries. If 'start' or 'end'
  236. * are not cache line aligned, those lines must be written
  237. * back.
  238. *
  239. * - start - virtual start address
  240. * - end - virtual end address
  241. */
  242. ENTRY(xsc3_dma_inv_range)
  243. tst r0, #CACHELINESIZE - 1
  244. bic r0, r0, #CACHELINESIZE - 1
  245. mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
  246. mcrne p15, 1, r0, c7, c11, 1 @ clean L2 line
  247. tst r1, #CACHELINESIZE - 1
  248. mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
  249. mcrne p15, 1, r1, c7, c11, 1 @ clean L2 line
  250. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
  251. mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
  252. add r0, r0, #CACHELINESIZE
  253. cmp r0, r1
  254. blo 1b
  255. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  256. mov pc, lr
  257. /*
  258. * dma_clean_range(start, end)
  259. *
  260. * Clean the specified virtual address range.
  261. *
  262. * - start - virtual start address
  263. * - end - virtual end address
  264. */
  265. ENTRY(xsc3_dma_clean_range)
  266. bic r0, r0, #CACHELINESIZE - 1
  267. 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
  268. mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
  269. add r0, r0, #CACHELINESIZE
  270. cmp r0, r1
  271. blo 1b
  272. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  273. mov pc, lr
  274. /*
  275. * dma_flush_range(start, end)
  276. *
  277. * Clean and invalidate the specified virtual address range.
  278. *
  279. * - start - virtual start address
  280. * - end - virtual end address
  281. */
  282. ENTRY(xsc3_dma_flush_range)
  283. bic r0, r0, #CACHELINESIZE - 1
  284. 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
  285. mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
  286. mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
  287. add r0, r0, #CACHELINESIZE
  288. cmp r0, r1
  289. blo 1b
  290. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  291. mov pc, lr
  292. ENTRY(xsc3_cache_fns)
  293. .long xsc3_flush_kern_cache_all
  294. .long xsc3_flush_user_cache_all
  295. .long xsc3_flush_user_cache_range
  296. .long xsc3_coherent_kern_range
  297. .long xsc3_coherent_user_range
  298. .long xsc3_flush_kern_dcache_page
  299. .long xsc3_dma_inv_range
  300. .long xsc3_dma_clean_range
  301. .long xsc3_dma_flush_range
  302. ENTRY(cpu_xsc3_dcache_clean_area)
  303. 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
  304. add r0, r0, #CACHELINESIZE
  305. subs r1, r1, #CACHELINESIZE
  306. bhi 1b
  307. mov pc, lr
  308. /* =============================== PageTable ============================== */
  309. /*
  310. * cpu_xsc3_switch_mm(pgd)
  311. *
  312. * Set the translation base pointer to be as described by pgd.
  313. *
  314. * pgd: new page tables
  315. */
  316. .align 5
  317. ENTRY(cpu_xsc3_switch_mm)
  318. clean_d_cache r1, r2
  319. mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
  320. mcr p15, 0, ip, c7, c10, 4 @ data write barrier
  321. mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
  322. #ifdef L2_CACHE_ENABLE
  323. orr r0, r0, #0x18 @ cache the page table in L2
  324. #endif
  325. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  326. mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
  327. cpwait_ret lr, ip
  328. /*
  329. * cpu_xsc3_set_pte_ext(ptep, pte, ext)
  330. *
  331. * Set a PTE and flush it out
  332. *
  333. */
  334. .align 5
  335. ENTRY(cpu_xsc3_set_pte_ext)
  336. str r1, [r0], #-2048 @ linux version
  337. bic r2, r1, #0xff0 @ keep C, B bits
  338. orr r2, r2, #PTE_TYPE_EXT @ extended page
  339. tst r1, #L_PTE_SHARED @ shared?
  340. orrne r2, r2, #0x200
  341. eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  342. tst r3, #L_PTE_USER @ user?
  343. orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
  344. tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
  345. orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
  346. @ combined with user -> user r/w
  347. #if L2_CACHE_ENABLE
  348. @ If it's cacheable, it needs to be in L2 also.
  349. eor ip, r1, #L_PTE_CACHEABLE
  350. tst ip, #L_PTE_CACHEABLE
  351. orreq r2, r2, #PTE_EXT_TEX(0x5)
  352. #endif
  353. tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
  354. movne r2, #0 @ no -> fault
  355. str r2, [r0] @ hardware version
  356. mov ip, #0
  357. mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
  358. mcr p15, 0, ip, c7, c10, 4 @ data write barrier
  359. mov pc, lr
  360. .ltorg
  361. .align
  362. __INIT
  363. .type __xsc3_setup, #function
  364. __xsc3_setup:
  365. mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  366. msr cpsr_c, r0
  367. mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
  368. mcr p15, 0, ip, c7, c10, 4 @ data write barrier
  369. mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
  370. mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
  371. #if L2_CACHE_ENABLE
  372. orr r4, r4, #0x18 @ cache the page table in L2
  373. #endif
  374. mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
  375. mov r0, #0 @ don't allow CP access
  376. mcr p15, 0, r0, c15, c1, 0 @ write CP access register
  377. mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
  378. and r0, r0, #2 @ preserve bit P bit setting
  379. #if L2_CACHE_ENABLE
  380. orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
  381. #endif
  382. mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
  383. adr r5, xsc3_crval
  384. ldmia r5, {r5, r6}
  385. mrc p15, 0, r0, c1, c0, 0 @ get control register
  386. bic r0, r0, r5 @ ..V. ..R. .... ..A.
  387. orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
  388. @ ...I Z..S .... .... (uc)
  389. #if L2_CACHE_ENABLE
  390. orr r0, r0, #0x04000000 @ L2 enable
  391. #endif
  392. mov pc, lr
  393. .size __xsc3_setup, . - __xsc3_setup
  394. .type xsc3_crval, #object
  395. xsc3_crval:
  396. crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
  397. __INITDATA
  398. /*
  399. * Purpose : Function pointers used to access above functions - all calls
  400. * come through these
  401. */
  402. .type xsc3_processor_functions, #object
  403. ENTRY(xsc3_processor_functions)
  404. .word v5t_early_abort
  405. .word cpu_xsc3_proc_init
  406. .word cpu_xsc3_proc_fin
  407. .word cpu_xsc3_reset
  408. .word cpu_xsc3_do_idle
  409. .word cpu_xsc3_dcache_clean_area
  410. .word cpu_xsc3_switch_mm
  411. .word cpu_xsc3_set_pte_ext
  412. .size xsc3_processor_functions, . - xsc3_processor_functions
  413. .section ".rodata"
  414. .type cpu_arch_name, #object
  415. cpu_arch_name:
  416. .asciz "armv5te"
  417. .size cpu_arch_name, . - cpu_arch_name
  418. .type cpu_elf_name, #object
  419. cpu_elf_name:
  420. .asciz "v5"
  421. .size cpu_elf_name, . - cpu_elf_name
  422. .type cpu_xsc3_name, #object
  423. cpu_xsc3_name:
  424. .asciz "XScale-V3 based processor"
  425. .size cpu_xsc3_name, . - cpu_xsc3_name
  426. .align
  427. .section ".proc.info.init", #alloc, #execinstr
  428. .type __xsc3_proc_info,#object
  429. __xsc3_proc_info:
  430. .long 0x69056000
  431. .long 0xffffe000
  432. .long PMD_TYPE_SECT | \
  433. PMD_SECT_BUFFERABLE | \
  434. PMD_SECT_CACHEABLE | \
  435. PMD_SECT_AP_WRITE | \
  436. PMD_SECT_AP_READ
  437. .long PMD_TYPE_SECT | \
  438. PMD_SECT_AP_WRITE | \
  439. PMD_SECT_AP_READ
  440. b __xsc3_setup
  441. .long cpu_arch_name
  442. .long cpu_elf_name
  443. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  444. .long cpu_xsc3_name
  445. .long xsc3_processor_functions
  446. .long v4wbi_tlb_fns
  447. .long xsc3_mc_user_fns
  448. .long xsc3_cache_fns
  449. .size __xsc3_proc_info, . - __xsc3_proc_info