proc-v6.S 6.6 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-v6.S
  3. *
  4. * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5. * Modified by Catalin Marinas for noMMU support
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This is the "shell" of the ARMv6 processor support.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/assembler.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/elf.h>
  17. #include <asm/pgtable-hwdef.h>
  18. #include <asm/pgtable.h>
  19. #ifdef CONFIG_SMP
  20. #include <asm/hardware/arm_scu.h>
  21. #endif
  22. #include "proc-macros.S"
  23. #define D_CACHE_LINE_SIZE 32
  24. #define TTB_C (1 << 0)
  25. #define TTB_S (1 << 1)
  26. #define TTB_IMP (1 << 2)
  27. #define TTB_RGN_NC (0 << 3)
  28. #define TTB_RGN_WBWA (1 << 3)
  29. #define TTB_RGN_WT (2 << 3)
  30. #define TTB_RGN_WB (3 << 3)
  31. #ifndef CONFIG_SMP
  32. #define TTB_FLAGS TTB_RGN_WBWA
  33. #else
  34. #define TTB_FLAGS TTB_RGN_WBWA|TTB_S
  35. #endif
  36. ENTRY(cpu_v6_proc_init)
  37. mov pc, lr
  38. ENTRY(cpu_v6_proc_fin)
  39. stmfd sp!, {lr}
  40. cpsid if @ disable interrupts
  41. bl v6_flush_kern_cache_all
  42. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  43. bic r0, r0, #0x1000 @ ...i............
  44. bic r0, r0, #0x0006 @ .............ca.
  45. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  46. ldmfd sp!, {pc}
  47. /*
  48. * cpu_v6_reset(loc)
  49. *
  50. * Perform a soft reset of the system. Put the CPU into the
  51. * same state as it would be if it had been reset, and branch
  52. * to what would be the reset vector.
  53. *
  54. * - loc - location to jump to for soft reset
  55. *
  56. * It is assumed that:
  57. */
  58. .align 5
  59. ENTRY(cpu_v6_reset)
  60. mov pc, r0
  61. /*
  62. * cpu_v6_do_idle()
  63. *
  64. * Idle the processor (eg, wait for interrupt).
  65. *
  66. * IRQs are already disabled.
  67. */
  68. ENTRY(cpu_v6_do_idle)
  69. mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
  70. mov pc, lr
  71. ENTRY(cpu_v6_dcache_clean_area)
  72. #ifndef TLB_CAN_READ_FROM_L1_CACHE
  73. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  74. add r0, r0, #D_CACHE_LINE_SIZE
  75. subs r1, r1, #D_CACHE_LINE_SIZE
  76. bhi 1b
  77. #endif
  78. mov pc, lr
  79. /*
  80. * cpu_arm926_switch_mm(pgd_phys, tsk)
  81. *
  82. * Set the translation table base pointer to be pgd_phys
  83. *
  84. * - pgd_phys - physical address of new TTB
  85. *
  86. * It is assumed that:
  87. * - we are not using split page tables
  88. */
  89. ENTRY(cpu_v6_switch_mm)
  90. #ifdef CONFIG_MMU
  91. mov r2, #0
  92. ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
  93. orr r0, r0, #TTB_FLAGS
  94. mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
  95. mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
  96. mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
  97. mcr p15, 0, r1, c13, c0, 1 @ set context ID
  98. #endif
  99. mov pc, lr
  100. /*
  101. * cpu_v6_set_pte_ext(ptep, pte, ext)
  102. *
  103. * Set a level 2 translation table entry.
  104. *
  105. * - ptep - pointer to level 2 translation table entry
  106. * (hardware version is stored at -1024 bytes)
  107. * - pte - PTE value to store
  108. * - ext - value for extended PTE bits
  109. *
  110. * Permissions:
  111. * YUWD APX AP1 AP0 SVC User
  112. * 0xxx 0 0 0 no acc no acc
  113. * 100x 1 0 1 r/o no acc
  114. * 10x0 1 0 1 r/o no acc
  115. * 1011 0 0 1 r/w no acc
  116. * 110x 0 1 0 r/w r/o
  117. * 11x0 0 1 0 r/w r/o
  118. * 1111 0 1 1 r/w r/w
  119. */
  120. ENTRY(cpu_v6_set_pte_ext)
  121. #ifdef CONFIG_MMU
  122. str r1, [r0], #-2048 @ linux version
  123. bic r3, r1, #0x000003f0
  124. bic r3, r3, #0x00000003
  125. orr r3, r3, r2
  126. orr r3, r3, #PTE_EXT_AP0 | 2
  127. tst r1, #L_PTE_WRITE
  128. tstne r1, #L_PTE_DIRTY
  129. orreq r3, r3, #PTE_EXT_APX
  130. tst r1, #L_PTE_USER
  131. orrne r3, r3, #PTE_EXT_AP1
  132. tstne r3, #PTE_EXT_APX
  133. bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
  134. tst r1, #L_PTE_YOUNG
  135. biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
  136. tst r1, #L_PTE_EXEC
  137. orreq r3, r3, #PTE_EXT_XN
  138. tst r1, #L_PTE_PRESENT
  139. moveq r3, #0
  140. str r3, [r0]
  141. mcr p15, 0, r0, c7, c10, 1 @ flush_pte
  142. #endif
  143. mov pc, lr
  144. cpu_v6_name:
  145. .asciz "ARMv6-compatible processor"
  146. .align
  147. .section ".text.init", #alloc, #execinstr
  148. /*
  149. * __v6_setup
  150. *
  151. * Initialise TLB, Caches, and MMU state ready to switch the MMU
  152. * on. Return in r0 the new CP15 C1 control register setting.
  153. *
  154. * We automatically detect if we have a Harvard cache, and use the
  155. * Harvard cache control instructions insead of the unified cache
  156. * control instructions.
  157. *
  158. * This should be able to cover all ARMv6 cores.
  159. *
  160. * It is assumed that:
  161. * - cache type register is implemented
  162. */
  163. __v6_setup:
  164. #ifdef CONFIG_SMP
  165. /* Set up the SCU on core 0 only */
  166. mrc p15, 0, r0, c0, c0, 5 @ CPU core number
  167. ands r0, r0, #15
  168. ldreq r0, =SCU_BASE
  169. ldreq r5, [r0, #SCU_CTRL]
  170. orreq r5, r5, #1
  171. streq r5, [r0, #SCU_CTRL]
  172. #ifndef CONFIG_CPU_DCACHE_DISABLE
  173. mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
  174. orr r0, r0, #0x20
  175. mcr p15, 0, r0, c1, c0, 1
  176. #endif
  177. #endif
  178. mov r0, #0
  179. mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
  180. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  181. mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
  182. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  183. #ifdef CONFIG_MMU
  184. mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
  185. mcr p15, 0, r0, c2, c0, 2 @ TTB control register
  186. orr r4, r4, #TTB_FLAGS
  187. mcr p15, 0, r4, c2, c0, 1 @ load TTB1
  188. #endif /* CONFIG_MMU */
  189. adr r5, v6_crval
  190. ldmia r5, {r5, r6}
  191. mrc p15, 0, r0, c1, c0, 0 @ read control register
  192. bic r0, r0, r5 @ clear bits them
  193. orr r0, r0, r6 @ set them
  194. mov pc, lr @ return to head.S:__ret
  195. /*
  196. * V X F I D LR
  197. * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
  198. * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
  199. * 0 110 0011 1.00 .111 1101 < we want
  200. */
  201. .type v6_crval, #object
  202. v6_crval:
  203. crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
  204. .type v6_processor_functions, #object
  205. ENTRY(v6_processor_functions)
  206. .word v6_early_abort
  207. .word cpu_v6_proc_init
  208. .word cpu_v6_proc_fin
  209. .word cpu_v6_reset
  210. .word cpu_v6_do_idle
  211. .word cpu_v6_dcache_clean_area
  212. .word cpu_v6_switch_mm
  213. .word cpu_v6_set_pte_ext
  214. .size v6_processor_functions, . - v6_processor_functions
  215. .type cpu_arch_name, #object
  216. cpu_arch_name:
  217. .asciz "armv6"
  218. .size cpu_arch_name, . - cpu_arch_name
  219. .type cpu_elf_name, #object
  220. cpu_elf_name:
  221. .asciz "v6"
  222. .size cpu_elf_name, . - cpu_elf_name
  223. .align
  224. .section ".proc.info.init", #alloc, #execinstr
  225. /*
  226. * Match any ARMv6 processor core.
  227. */
  228. .type __v6_proc_info, #object
  229. __v6_proc_info:
  230. .long 0x0007b000
  231. .long 0x0007f000
  232. .long PMD_TYPE_SECT | \
  233. PMD_SECT_BUFFERABLE | \
  234. PMD_SECT_CACHEABLE | \
  235. PMD_SECT_AP_WRITE | \
  236. PMD_SECT_AP_READ
  237. .long PMD_TYPE_SECT | \
  238. PMD_SECT_XN | \
  239. PMD_SECT_AP_WRITE | \
  240. PMD_SECT_AP_READ
  241. b __v6_setup
  242. .long cpu_arch_name
  243. .long cpu_elf_name
  244. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
  245. .long cpu_v6_name
  246. .long v6_processor_functions
  247. .long v6wbi_tlb_fns
  248. .long v6_user_fns
  249. .long v6_cache_fns
  250. .size __v6_proc_info, . - __v6_proc_info