proc-sa1100.S 7.4 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-sa1100.S
  3. *
  4. * Copyright (C) 1997-2002 Russell King
  5. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * MMU functions for SA110
  12. *
  13. * These are the low level assembler for performing cache and TLB
  14. * functions on the StrongARM-1100 and StrongARM-1110.
  15. *
  16. * Note that SA1100 and SA1110 share everything but their name and CPU ID.
  17. *
  18. * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
  19. * Flush the read buffer at context switches
  20. */
  21. #include <linux/linkage.h>
  22. #include <linux/init.h>
  23. #include <asm/assembler.h>
  24. #include <asm/asm-offsets.h>
  25. #include <asm/elf.h>
  26. #include <asm/hardware.h>
  27. #include <asm/pgtable-hwdef.h>
  28. #include <asm/pgtable.h>
  29. #include "proc-macros.S"
  30. /*
  31. * the cache line size of the I and D cache
  32. */
  33. #define DCACHELINESIZE 32
  34. __INIT
  35. /*
  36. * cpu_sa1100_proc_init()
  37. */
  38. ENTRY(cpu_sa1100_proc_init)
  39. mov r0, #0
  40. mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
  41. mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
  42. mov pc, lr
  43. .previous
  44. /*
  45. * cpu_sa1100_proc_fin()
  46. *
  47. * Prepare the CPU for reset:
  48. * - Disable interrupts
  49. * - Clean and turn off caches.
  50. */
  51. ENTRY(cpu_sa1100_proc_fin)
  52. stmfd sp!, {lr}
  53. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  54. msr cpsr_c, ip
  55. bl v4wb_flush_kern_cache_all
  56. mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
  57. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  58. bic r0, r0, #0x1000 @ ...i............
  59. bic r0, r0, #0x000e @ ............wca.
  60. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  61. ldmfd sp!, {pc}
  62. /*
  63. * cpu_sa1100_reset(loc)
  64. *
  65. * Perform a soft reset of the system. Put the CPU into the
  66. * same state as it would be if it had been reset, and branch
  67. * to what would be the reset vector.
  68. *
  69. * loc: location to jump to for soft reset
  70. */
  71. .align 5
  72. ENTRY(cpu_sa1100_reset)
  73. mov ip, #0
  74. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  75. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  76. #ifdef CONFIG_MMU
  77. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  78. #endif
  79. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  80. bic ip, ip, #0x000f @ ............wcam
  81. bic ip, ip, #0x1100 @ ...i...s........
  82. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  83. mov pc, r0
  84. /*
  85. * cpu_sa1100_do_idle(type)
  86. *
  87. * Cause the processor to idle
  88. *
  89. * type: call type:
  90. * 0 = slow idle
  91. * 1 = fast idle
  92. * 2 = switch to slow processor clock
  93. * 3 = switch to fast processor clock
  94. */
  95. .align 5
  96. ENTRY(cpu_sa1100_do_idle)
  97. mov r0, r0 @ 4 nop padding
  98. mov r0, r0
  99. mov r0, r0
  100. mov r0, r0 @ 4 nop padding
  101. mov r0, r0
  102. mov r0, r0
  103. mov r0, #0
  104. ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
  105. @ --- aligned to a cache line
  106. mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
  107. ldr r1, [r1, #0] @ force switch to MCLK
  108. mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
  109. mov r0, r0 @ safety
  110. mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
  111. mov pc, lr
  112. /* ================================= CACHE ================================ */
  113. /*
  114. * cpu_sa1100_dcache_clean_area(addr,sz)
  115. *
  116. * Clean the specified entry of any caches such that the MMU
  117. * translation fetches will obtain correct data.
  118. *
  119. * addr: cache-unaligned virtual address
  120. */
  121. .align 5
  122. ENTRY(cpu_sa1100_dcache_clean_area)
  123. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  124. add r0, r0, #DCACHELINESIZE
  125. subs r1, r1, #DCACHELINESIZE
  126. bhi 1b
  127. mov pc, lr
  128. /* =============================== PageTable ============================== */
  129. /*
  130. * cpu_sa1100_switch_mm(pgd)
  131. *
  132. * Set the translation base pointer to be as described by pgd.
  133. *
  134. * pgd: new page tables
  135. */
  136. .align 5
  137. ENTRY(cpu_sa1100_switch_mm)
  138. #ifdef CONFIG_MMU
  139. str lr, [sp, #-4]!
  140. bl v4wb_flush_kern_cache_all @ clears IP
  141. mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
  142. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  143. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  144. ldr pc, [sp], #4
  145. #else
  146. mov pc, lr
  147. #endif
  148. /*
  149. * cpu_sa1100_set_pte_ext(ptep, pte, ext)
  150. *
  151. * Set a PTE and flush it out
  152. */
  153. .align 5
  154. ENTRY(cpu_sa1100_set_pte_ext)
  155. #ifdef CONFIG_MMU
  156. str r1, [r0], #-2048 @ linux version
  157. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  158. bic r2, r1, #PTE_SMALL_AP_MASK
  159. bic r2, r2, #PTE_TYPE_MASK
  160. orr r2, r2, #PTE_TYPE_SMALL
  161. tst r1, #L_PTE_USER @ User?
  162. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  163. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  164. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  165. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  166. movne r2, #0
  167. str r2, [r0] @ hardware version
  168. mov r0, r0
  169. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  170. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  171. #endif
  172. mov pc, lr
  173. __INIT
  174. .type __sa1100_setup, #function
  175. __sa1100_setup:
  176. mov r0, #0
  177. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  178. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  179. #ifdef CONFIG_MMU
  180. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  181. #endif
  182. adr r5, sa1100_crval
  183. ldmia r5, {r5, r6}
  184. mrc p15, 0, r0, c1, c0 @ get control register v4
  185. bic r0, r0, r5
  186. orr r0, r0, r6
  187. mov pc, lr
  188. .size __sa1100_setup, . - __sa1100_setup
  189. /*
  190. * R
  191. * .RVI ZFRS BLDP WCAM
  192. * ..11 0001 ..11 1101
  193. *
  194. */
  195. .type sa1100_crval, #object
  196. sa1100_crval:
  197. crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
  198. __INITDATA
  199. /*
  200. * Purpose : Function pointers used to access above functions - all calls
  201. * come through these
  202. */
  203. /*
  204. * SA1100 and SA1110 share the same function calls
  205. */
  206. .type sa1100_processor_functions, #object
  207. ENTRY(sa1100_processor_functions)
  208. .word v4_early_abort
  209. .word cpu_sa1100_proc_init
  210. .word cpu_sa1100_proc_fin
  211. .word cpu_sa1100_reset
  212. .word cpu_sa1100_do_idle
  213. .word cpu_sa1100_dcache_clean_area
  214. .word cpu_sa1100_switch_mm
  215. .word cpu_sa1100_set_pte_ext
  216. .size sa1100_processor_functions, . - sa1100_processor_functions
  217. .section ".rodata"
  218. .type cpu_arch_name, #object
  219. cpu_arch_name:
  220. .asciz "armv4"
  221. .size cpu_arch_name, . - cpu_arch_name
  222. .type cpu_elf_name, #object
  223. cpu_elf_name:
  224. .asciz "v4"
  225. .size cpu_elf_name, . - cpu_elf_name
  226. .type cpu_sa1100_name, #object
  227. cpu_sa1100_name:
  228. .asciz "StrongARM-1100"
  229. .size cpu_sa1100_name, . - cpu_sa1100_name
  230. .type cpu_sa1110_name, #object
  231. cpu_sa1110_name:
  232. .asciz "StrongARM-1110"
  233. .size cpu_sa1110_name, . - cpu_sa1110_name
  234. .align
  235. .section ".proc.info.init", #alloc, #execinstr
  236. .type __sa1100_proc_info,#object
  237. __sa1100_proc_info:
  238. .long 0x4401a110
  239. .long 0xfffffff0
  240. .long PMD_TYPE_SECT | \
  241. PMD_SECT_BUFFERABLE | \
  242. PMD_SECT_CACHEABLE | \
  243. PMD_SECT_AP_WRITE | \
  244. PMD_SECT_AP_READ
  245. .long PMD_TYPE_SECT | \
  246. PMD_SECT_AP_WRITE | \
  247. PMD_SECT_AP_READ
  248. b __sa1100_setup
  249. .long cpu_arch_name
  250. .long cpu_elf_name
  251. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
  252. .long cpu_sa1100_name
  253. .long sa1100_processor_functions
  254. .long v4wb_tlb_fns
  255. .long v4_mc_user_fns
  256. .long v4wb_cache_fns
  257. .size __sa1100_proc_info, . - __sa1100_proc_info
  258. .type __sa1110_proc_info,#object
  259. __sa1110_proc_info:
  260. .long 0x6901b110
  261. .long 0xfffffff0
  262. .long PMD_TYPE_SECT | \
  263. PMD_SECT_BUFFERABLE | \
  264. PMD_SECT_CACHEABLE | \
  265. PMD_SECT_AP_WRITE | \
  266. PMD_SECT_AP_READ
  267. .long PMD_TYPE_SECT | \
  268. PMD_SECT_AP_WRITE | \
  269. PMD_SECT_AP_READ
  270. b __sa1100_setup
  271. .long cpu_arch_name
  272. .long cpu_elf_name
  273. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
  274. .long cpu_sa1110_name
  275. .long sa1100_processor_functions
  276. .long v4wb_tlb_fns
  277. .long v4_mc_user_fns
  278. .long v4wb_cache_fns
  279. .size __sa1110_proc_info, . - __sa1110_proc_info