proc-sa110.S 6.3 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-sa110.S
  3. *
  4. * Copyright (C) 1997-2002 Russell King
  5. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * MMU functions for SA110
  12. *
  13. * These are the low level assembler for performing cache and TLB
  14. * functions on the StrongARM-110.
  15. */
  16. #include <linux/linkage.h>
  17. #include <linux/init.h>
  18. #include <asm/assembler.h>
  19. #include <asm/asm-offsets.h>
  20. #include <asm/elf.h>
  21. #include <asm/hardware.h>
  22. #include <asm/pgtable-hwdef.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/ptrace.h>
  25. #include "proc-macros.S"
  26. /*
  27. * the cache line size of the I and D cache
  28. */
  29. #define DCACHELINESIZE 32
  30. .text
  31. /*
  32. * cpu_sa110_proc_init()
  33. */
  34. ENTRY(cpu_sa110_proc_init)
  35. mov r0, #0
  36. mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
  37. mov pc, lr
  38. /*
  39. * cpu_sa110_proc_fin()
  40. */
  41. ENTRY(cpu_sa110_proc_fin)
  42. stmfd sp!, {lr}
  43. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  44. msr cpsr_c, ip
  45. bl v4wb_flush_kern_cache_all @ clean caches
  46. 1: mov r0, #0
  47. mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
  48. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  49. bic r0, r0, #0x1000 @ ...i............
  50. bic r0, r0, #0x000e @ ............wca.
  51. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  52. ldmfd sp!, {pc}
  53. /*
  54. * cpu_sa110_reset(loc)
  55. *
  56. * Perform a soft reset of the system. Put the CPU into the
  57. * same state as it would be if it had been reset, and branch
  58. * to what would be the reset vector.
  59. *
  60. * loc: location to jump to for soft reset
  61. */
  62. .align 5
  63. ENTRY(cpu_sa110_reset)
  64. mov ip, #0
  65. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  66. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  67. #ifdef CONFIG_MMU
  68. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  69. #endif
  70. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  71. bic ip, ip, #0x000f @ ............wcam
  72. bic ip, ip, #0x1100 @ ...i...s........
  73. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  74. mov pc, r0
  75. /*
  76. * cpu_sa110_do_idle(type)
  77. *
  78. * Cause the processor to idle
  79. *
  80. * type: call type:
  81. * 0 = slow idle
  82. * 1 = fast idle
  83. * 2 = switch to slow processor clock
  84. * 3 = switch to fast processor clock
  85. */
  86. .align 5
  87. ENTRY(cpu_sa110_do_idle)
  88. mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
  89. ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
  90. ldr r1, [r1, #0] @ force switch to MCLK
  91. mov r0, r0 @ safety
  92. mov r0, r0 @ safety
  93. mov r0, r0 @ safety
  94. mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
  95. mov r0, r0 @ safety
  96. mov r0, r0 @ safety
  97. mov r0, r0 @ safety
  98. mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
  99. mov pc, lr
  100. /* ================================= CACHE ================================ */
  101. /*
  102. * cpu_sa110_dcache_clean_area(addr,sz)
  103. *
  104. * Clean the specified entry of any caches such that the MMU
  105. * translation fetches will obtain correct data.
  106. *
  107. * addr: cache-unaligned virtual address
  108. */
  109. .align 5
  110. ENTRY(cpu_sa110_dcache_clean_area)
  111. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  112. add r0, r0, #DCACHELINESIZE
  113. subs r1, r1, #DCACHELINESIZE
  114. bhi 1b
  115. mov pc, lr
  116. /* =============================== PageTable ============================== */
  117. /*
  118. * cpu_sa110_switch_mm(pgd)
  119. *
  120. * Set the translation base pointer to be as described by pgd.
  121. *
  122. * pgd: new page tables
  123. */
  124. .align 5
  125. ENTRY(cpu_sa110_switch_mm)
  126. #ifdef CONFIG_MMU
  127. str lr, [sp, #-4]!
  128. bl v4wb_flush_kern_cache_all @ clears IP
  129. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  130. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  131. ldr pc, [sp], #4
  132. #else
  133. mov pc, lr
  134. #endif
  135. /*
  136. * cpu_sa110_set_pte_ext(ptep, pte, ext)
  137. *
  138. * Set a PTE and flush it out
  139. */
  140. .align 5
  141. ENTRY(cpu_sa110_set_pte_ext)
  142. #ifdef CONFIG_MMU
  143. str r1, [r0], #-2048 @ linux version
  144. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  145. bic r2, r1, #PTE_SMALL_AP_MASK
  146. bic r2, r2, #PTE_TYPE_MASK
  147. orr r2, r2, #PTE_TYPE_SMALL
  148. tst r1, #L_PTE_USER @ User?
  149. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  150. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  151. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  152. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  153. movne r2, #0
  154. str r2, [r0] @ hardware version
  155. mov r0, r0
  156. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  157. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  158. #endif
  159. mov pc, lr
  160. __INIT
  161. .type __sa110_setup, #function
  162. __sa110_setup:
  163. mov r10, #0
  164. mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
  165. mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
  166. #ifdef CONFIG_MMU
  167. mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
  168. #endif
  169. adr r5, sa110_crval
  170. ldmia r5, {r5, r6}
  171. mrc p15, 0, r0, c1, c0 @ get control register v4
  172. bic r0, r0, r5
  173. orr r0, r0, r6
  174. mov pc, lr
  175. .size __sa110_setup, . - __sa110_setup
  176. /*
  177. * R
  178. * .RVI ZFRS BLDP WCAM
  179. * ..01 0001 ..11 1101
  180. *
  181. */
  182. .type sa110_crval, #object
  183. sa110_crval:
  184. crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
  185. __INITDATA
  186. /*
  187. * Purpose : Function pointers used to access above functions - all calls
  188. * come through these
  189. */
  190. .type sa110_processor_functions, #object
  191. ENTRY(sa110_processor_functions)
  192. .word v4_early_abort
  193. .word cpu_sa110_proc_init
  194. .word cpu_sa110_proc_fin
  195. .word cpu_sa110_reset
  196. .word cpu_sa110_do_idle
  197. .word cpu_sa110_dcache_clean_area
  198. .word cpu_sa110_switch_mm
  199. .word cpu_sa110_set_pte_ext
  200. .size sa110_processor_functions, . - sa110_processor_functions
  201. .section ".rodata"
  202. .type cpu_arch_name, #object
  203. cpu_arch_name:
  204. .asciz "armv4"
  205. .size cpu_arch_name, . - cpu_arch_name
  206. .type cpu_elf_name, #object
  207. cpu_elf_name:
  208. .asciz "v4"
  209. .size cpu_elf_name, . - cpu_elf_name
  210. .type cpu_sa110_name, #object
  211. cpu_sa110_name:
  212. .asciz "StrongARM-110"
  213. .size cpu_sa110_name, . - cpu_sa110_name
  214. .align
  215. .section ".proc.info.init", #alloc, #execinstr
  216. .type __sa110_proc_info,#object
  217. __sa110_proc_info:
  218. .long 0x4401a100
  219. .long 0xfffffff0
  220. .long PMD_TYPE_SECT | \
  221. PMD_SECT_BUFFERABLE | \
  222. PMD_SECT_CACHEABLE | \
  223. PMD_SECT_AP_WRITE | \
  224. PMD_SECT_AP_READ
  225. .long PMD_TYPE_SECT | \
  226. PMD_SECT_AP_WRITE | \
  227. PMD_SECT_AP_READ
  228. b __sa110_setup
  229. .long cpu_arch_name
  230. .long cpu_elf_name
  231. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
  232. .long cpu_sa110_name
  233. .long sa110_processor_functions
  234. .long v4wb_tlb_fns
  235. .long v4wb_user_fns
  236. .long v4wb_cache_fns
  237. .size __sa110_proc_info, . - __sa110_proc_info