proc-arm946.S 11 KB

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  1. /*
  2. * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
  3. *
  4. * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
  5. *
  6. * (Many of cache codes are from proc-arm926.S)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/linkage.h>
  14. #include <linux/init.h>
  15. #include <asm/assembler.h>
  16. #include <asm/elf.h>
  17. #include <asm/pgtable-hwdef.h>
  18. #include <asm/pgtable.h>
  19. #include <asm/ptrace.h>
  20. /*
  21. * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
  22. * comprising 256 lines of 32 bytes (8 words).
  23. */
  24. #define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
  25. #define CACHE_DLINESIZE 32 /* fixed */
  26. #define CACHE_DSEGMENTS 4 /* fixed */
  27. #define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
  28. #define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
  29. .text
  30. /*
  31. * cpu_arm946_proc_init()
  32. * cpu_arm946_switch_mm()
  33. *
  34. * These are not required.
  35. */
  36. ENTRY(cpu_arm946_proc_init)
  37. ENTRY(cpu_arm946_switch_mm)
  38. mov pc, lr
  39. /*
  40. * cpu_arm946_proc_fin()
  41. */
  42. ENTRY(cpu_arm946_proc_fin)
  43. stmfd sp!, {lr}
  44. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  45. msr cpsr_c, ip
  46. bl arm946_flush_kern_cache_all
  47. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  48. bic r0, r0, #0x00001000 @ i-cache
  49. bic r0, r0, #0x00000004 @ d-cache
  50. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  51. ldmfd sp!, {pc}
  52. /*
  53. * cpu_arm946_reset(loc)
  54. * Params : r0 = address to jump to
  55. * Notes : This sets up everything for a reset
  56. */
  57. ENTRY(cpu_arm946_reset)
  58. mov ip, #0
  59. mcr p15, 0, ip, c7, c5, 0 @ flush I cache
  60. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  61. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  62. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  63. bic ip, ip, #0x00000005 @ .............c.p
  64. bic ip, ip, #0x00001000 @ i-cache
  65. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  66. mov pc, r0
  67. /*
  68. * cpu_arm946_do_idle()
  69. */
  70. .align 5
  71. ENTRY(cpu_arm946_do_idle)
  72. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  73. mov pc, lr
  74. /*
  75. * flush_user_cache_all()
  76. */
  77. ENTRY(arm946_flush_user_cache_all)
  78. /* FALLTHROUGH */
  79. /*
  80. * flush_kern_cache_all()
  81. *
  82. * Clean and invalidate the entire cache.
  83. */
  84. ENTRY(arm946_flush_kern_cache_all)
  85. mov r2, #VM_EXEC
  86. mov ip, #0
  87. __flush_whole_cache:
  88. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  89. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  90. #else
  91. mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
  92. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
  93. 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
  94. subs r3, r3, #1 << 4
  95. bcs 2b @ entries n to 0
  96. subs r1, r1, #1 << 29
  97. bcs 1b @ segments 3 to 0
  98. #endif
  99. tst r2, #VM_EXEC
  100. mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
  101. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  102. mov pc, lr
  103. /*
  104. * flush_user_cache_range(start, end, flags)
  105. *
  106. * Clean and invalidate a range of cache entries in the
  107. * specified address range.
  108. *
  109. * - start - start address (inclusive)
  110. * - end - end address (exclusive)
  111. * - flags - vm_flags describing address space
  112. * (same as arm926)
  113. */
  114. ENTRY(arm946_flush_user_cache_range)
  115. mov ip, #0
  116. sub r3, r1, r0 @ calculate total size
  117. cmp r3, #CACHE_DLIMIT
  118. bhs __flush_whole_cache
  119. 1: tst r2, #VM_EXEC
  120. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  121. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  122. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  123. add r0, r0, #CACHE_DLINESIZE
  124. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  125. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  126. add r0, r0, #CACHE_DLINESIZE
  127. #else
  128. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  129. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  130. add r0, r0, #CACHE_DLINESIZE
  131. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  132. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  133. add r0, r0, #CACHE_DLINESIZE
  134. #endif
  135. cmp r0, r1
  136. blo 1b
  137. tst r2, #VM_EXEC
  138. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  139. mov pc, lr
  140. /*
  141. * coherent_kern_range(start, end)
  142. *
  143. * Ensure coherency between the Icache and the Dcache in the
  144. * region described by start, end. If you have non-snooping
  145. * Harvard caches, you need to implement this function.
  146. *
  147. * - start - virtual start address
  148. * - end - virtual end address
  149. */
  150. ENTRY(arm946_coherent_kern_range)
  151. /* FALLTHROUGH */
  152. /*
  153. * coherent_user_range(start, end)
  154. *
  155. * Ensure coherency between the Icache and the Dcache in the
  156. * region described by start, end. If you have non-snooping
  157. * Harvard caches, you need to implement this function.
  158. *
  159. * - start - virtual start address
  160. * - end - virtual end address
  161. * (same as arm926)
  162. */
  163. ENTRY(arm946_coherent_user_range)
  164. bic r0, r0, #CACHE_DLINESIZE - 1
  165. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  166. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  167. add r0, r0, #CACHE_DLINESIZE
  168. cmp r0, r1
  169. blo 1b
  170. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  171. mov pc, lr
  172. /*
  173. * flush_kern_dcache_page(void *page)
  174. *
  175. * Ensure no D cache aliasing occurs, either with itself or
  176. * the I cache
  177. *
  178. * - addr - page aligned address
  179. * (same as arm926)
  180. */
  181. ENTRY(arm946_flush_kern_dcache_page)
  182. add r1, r0, #PAGE_SZ
  183. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  184. add r0, r0, #CACHE_DLINESIZE
  185. cmp r0, r1
  186. blo 1b
  187. mov r0, #0
  188. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  189. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  190. mov pc, lr
  191. /*
  192. * dma_inv_range(start, end)
  193. *
  194. * Invalidate (discard) the specified virtual address range.
  195. * May not write back any entries. If 'start' or 'end'
  196. * are not cache line aligned, those lines must be written
  197. * back.
  198. *
  199. * - start - virtual start address
  200. * - end - virtual end address
  201. * (same as arm926)
  202. */
  203. ENTRY(arm946_dma_inv_range)
  204. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  205. tst r0, #CACHE_DLINESIZE - 1
  206. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  207. tst r1, #CACHE_DLINESIZE - 1
  208. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  209. #endif
  210. bic r0, r0, #CACHE_DLINESIZE - 1
  211. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  212. add r0, r0, #CACHE_DLINESIZE
  213. cmp r0, r1
  214. blo 1b
  215. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  216. mov pc, lr
  217. /*
  218. * dma_clean_range(start, end)
  219. *
  220. * Clean the specified virtual address range.
  221. *
  222. * - start - virtual start address
  223. * - end - virtual end address
  224. *
  225. * (same as arm926)
  226. */
  227. ENTRY(arm946_dma_clean_range)
  228. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  229. bic r0, r0, #CACHE_DLINESIZE - 1
  230. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  231. add r0, r0, #CACHE_DLINESIZE
  232. cmp r0, r1
  233. blo 1b
  234. #endif
  235. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  236. mov pc, lr
  237. /*
  238. * dma_flush_range(start, end)
  239. *
  240. * Clean and invalidate the specified virtual address range.
  241. *
  242. * - start - virtual start address
  243. * - end - virtual end address
  244. *
  245. * (same as arm926)
  246. */
  247. ENTRY(arm946_dma_flush_range)
  248. bic r0, r0, #CACHE_DLINESIZE - 1
  249. 1:
  250. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  251. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  252. #else
  253. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  254. #endif
  255. add r0, r0, #CACHE_DLINESIZE
  256. cmp r0, r1
  257. blo 1b
  258. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  259. mov pc, lr
  260. ENTRY(arm946_cache_fns)
  261. .long arm946_flush_kern_cache_all
  262. .long arm946_flush_user_cache_all
  263. .long arm946_flush_user_cache_range
  264. .long arm946_coherent_kern_range
  265. .long arm946_coherent_user_range
  266. .long arm946_flush_kern_dcache_page
  267. .long arm946_dma_inv_range
  268. .long arm946_dma_clean_range
  269. .long arm946_dma_flush_range
  270. ENTRY(cpu_arm946_dcache_clean_area)
  271. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  272. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  273. add r0, r0, #CACHE_DLINESIZE
  274. subs r1, r1, #CACHE_DLINESIZE
  275. bhi 1b
  276. #endif
  277. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  278. mov pc, lr
  279. __INIT
  280. .type __arm946_setup, #function
  281. __arm946_setup:
  282. mov r0, #0
  283. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  284. mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
  285. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  286. mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
  287. mcr p15, 0, r0, c6, c4, 0
  288. mcr p15, 0, r0, c6, c5, 0
  289. mcr p15, 0, r0, c6, c6, 0
  290. mcr p15, 0, r0, c6, c7, 0
  291. mov r0, #0x0000003F @ base = 0, size = 4GB
  292. mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
  293. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  294. ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
  295. mov r2, #10 @ 11 is the minimum (4KB)
  296. 1: add r2, r2, #1 @ area size *= 2
  297. mov r1, r1, lsr #1
  298. bne 1b @ count not zero r-shift
  299. orr r0, r0, r2, lsl #1 @ the region register value
  300. orr r0, r0, #1 @ set enable bit
  301. mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
  302. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  303. ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
  304. mov r2, #10 @ 11 is the minimum (4KB)
  305. 1: add r2, r2, #1 @ area size *= 2
  306. mov r1, r1, lsr #1
  307. bne 1b @ count not zero r-shift
  308. orr r0, r0, r2, lsl #1 @ the region register value
  309. orr r0, r0, #1 @ set enable bit
  310. mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
  311. mov r0, #0x06
  312. mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
  313. mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
  314. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  315. mov r0, #0x00 @ disable whole write buffer
  316. #else
  317. mov r0, #0x02 @ region 1 write bufferred
  318. #endif
  319. mcr p15, 0, r0, c3, c0, 0
  320. /*
  321. * Access Permission Settings for future permission control by PU.
  322. *
  323. * priv. user
  324. * region 0 (whole) rw -- : b0001
  325. * region 1 (RAM) rw rw : b0011
  326. * region 2 (FLASH) rw r- : b0010
  327. * region 3~7 (none) -- -- : b0000
  328. */
  329. mov r0, #0x00000031
  330. orr r0, r0, #0x00000200
  331. mcr p15, 0, r0, c5, c0, 2 @ set data access permission
  332. mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
  333. mrc p15, 0, r0, c1, c0 @ get control register
  334. orr r0, r0, #0x00001000 @ I-cache
  335. orr r0, r0, #0x00000005 @ MPU/D-cache
  336. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  337. orr r0, r0, #0x00004000 @ .1.. .... .... ....
  338. #endif
  339. mov pc, lr
  340. .size __arm946_setup, . - __arm946_setup
  341. __INITDATA
  342. /*
  343. * Purpose : Function pointers used to access above functions - all calls
  344. * come through these
  345. */
  346. .type arm946_processor_functions, #object
  347. ENTRY(arm946_processor_functions)
  348. .word nommu_early_abort
  349. .word cpu_arm946_proc_init
  350. .word cpu_arm946_proc_fin
  351. .word cpu_arm946_reset
  352. .word cpu_arm946_do_idle
  353. .word cpu_arm946_dcache_clean_area
  354. .word cpu_arm946_switch_mm
  355. .word 0 @ cpu_*_set_pte
  356. .size arm946_processor_functions, . - arm946_processor_functions
  357. .section ".rodata"
  358. .type cpu_arch_name, #object
  359. cpu_arch_name:
  360. .asciz "armv5te"
  361. .size cpu_arch_name, . - cpu_arch_name
  362. .type cpu_elf_name, #object
  363. cpu_elf_name:
  364. .asciz "v5t"
  365. .size cpu_elf_name, . - cpu_elf_name
  366. .type cpu_arm946_name, #object
  367. cpu_arm946_name:
  368. .ascii "ARM946E-S"
  369. .size cpu_arm946_name, . - cpu_arm946_name
  370. .align
  371. .section ".proc.info.init", #alloc, #execinstr
  372. .type __arm946_proc_info,#object
  373. __arm946_proc_info:
  374. .long 0x41009460
  375. .long 0xff00fff0
  376. .long 0
  377. b __arm946_setup
  378. .long cpu_arch_name
  379. .long cpu_elf_name
  380. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  381. .long cpu_arm946_name
  382. .long arm946_processor_functions
  383. .long 0
  384. .long 0
  385. .long arm940_cache_fns
  386. .size __arm946_proc_info, . - __arm946_proc_info