proc-arm940.S 9.4 KB

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  1. /*
  2. * linux/arch/arm/mm/arm940.S: utility functions for ARM940T
  3. *
  4. * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/init.h>
  13. #include <asm/assembler.h>
  14. #include <asm/elf.h>
  15. #include <asm/pgtable-hwdef.h>
  16. #include <asm/pgtable.h>
  17. #include <asm/ptrace.h>
  18. /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
  19. #define CACHE_DLINESIZE 16
  20. #define CACHE_DSEGMENTS 4
  21. #define CACHE_DENTRIES 64
  22. .text
  23. /*
  24. * cpu_arm940_proc_init()
  25. * cpu_arm940_switch_mm()
  26. *
  27. * These are not required.
  28. */
  29. ENTRY(cpu_arm940_proc_init)
  30. ENTRY(cpu_arm940_switch_mm)
  31. mov pc, lr
  32. /*
  33. * cpu_arm940_proc_fin()
  34. */
  35. ENTRY(cpu_arm940_proc_fin)
  36. stmfd sp!, {lr}
  37. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  38. msr cpsr_c, ip
  39. bl arm940_flush_kern_cache_all
  40. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  41. bic r0, r0, #0x00001000 @ i-cache
  42. bic r0, r0, #0x00000004 @ d-cache
  43. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  44. ldmfd sp!, {pc}
  45. /*
  46. * cpu_arm940_reset(loc)
  47. * Params : r0 = address to jump to
  48. * Notes : This sets up everything for a reset
  49. */
  50. ENTRY(cpu_arm940_reset)
  51. mov ip, #0
  52. mcr p15, 0, ip, c7, c5, 0 @ flush I cache
  53. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  54. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  55. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  56. bic ip, ip, #0x00000005 @ .............c.p
  57. bic ip, ip, #0x00001000 @ i-cache
  58. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  59. mov pc, r0
  60. /*
  61. * cpu_arm940_do_idle()
  62. */
  63. .align 5
  64. ENTRY(cpu_arm940_do_idle)
  65. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  66. mov pc, lr
  67. /*
  68. * flush_user_cache_all()
  69. */
  70. ENTRY(arm940_flush_user_cache_all)
  71. /* FALLTHROUGH */
  72. /*
  73. * flush_kern_cache_all()
  74. *
  75. * Clean and invalidate the entire cache.
  76. */
  77. ENTRY(arm940_flush_kern_cache_all)
  78. mov r2, #VM_EXEC
  79. /* FALLTHROUGH */
  80. /*
  81. * flush_user_cache_range(start, end, flags)
  82. *
  83. * There is no efficient way to flush a range of cache entries
  84. * in the specified address range. Thus, flushes all.
  85. *
  86. * - start - start address (inclusive)
  87. * - end - end address (exclusive)
  88. * - flags - vm_flags describing address space
  89. */
  90. ENTRY(arm940_flush_user_cache_range)
  91. mov ip, #0
  92. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  93. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  94. #else
  95. mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
  96. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  97. 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
  98. subs r3, r3, #1 << 26
  99. bcs 2b @ entries 63 to 0
  100. subs r1, r1, #1 << 4
  101. bcs 1b @ segments 3 to 0
  102. #endif
  103. tst r2, #VM_EXEC
  104. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  105. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  106. mov pc, lr
  107. /*
  108. * coherent_kern_range(start, end)
  109. *
  110. * Ensure coherency between the Icache and the Dcache in the
  111. * region described by start, end. If you have non-snooping
  112. * Harvard caches, you need to implement this function.
  113. *
  114. * - start - virtual start address
  115. * - end - virtual end address
  116. */
  117. ENTRY(arm940_coherent_kern_range)
  118. /* FALLTHROUGH */
  119. /*
  120. * coherent_user_range(start, end)
  121. *
  122. * Ensure coherency between the Icache and the Dcache in the
  123. * region described by start, end. If you have non-snooping
  124. * Harvard caches, you need to implement this function.
  125. *
  126. * - start - virtual start address
  127. * - end - virtual end address
  128. */
  129. ENTRY(arm940_coherent_user_range)
  130. /* FALLTHROUGH */
  131. /*
  132. * flush_kern_dcache_page(void *page)
  133. *
  134. * Ensure no D cache aliasing occurs, either with itself or
  135. * the I cache
  136. *
  137. * - addr - page aligned address
  138. */
  139. ENTRY(arm940_flush_kern_dcache_page)
  140. mov ip, #0
  141. mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
  142. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  143. 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
  144. subs r3, r3, #1 << 26
  145. bcs 2b @ entries 63 to 0
  146. subs r1, r1, #1 << 4
  147. bcs 1b @ segments 7 to 0
  148. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  149. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  150. mov pc, lr
  151. /*
  152. * dma_inv_range(start, end)
  153. *
  154. * There is no efficient way to invalidate a specifid virtual
  155. * address range. Thus, invalidates all.
  156. *
  157. * - start - virtual start address
  158. * - end - virtual end address
  159. */
  160. ENTRY(arm940_dma_inv_range)
  161. mov ip, #0
  162. mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
  163. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  164. 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
  165. subs r3, r3, #1 << 26
  166. bcs 2b @ entries 63 to 0
  167. subs r1, r1, #1 << 4
  168. bcs 1b @ segments 7 to 0
  169. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  170. mov pc, lr
  171. /*
  172. * dma_clean_range(start, end)
  173. *
  174. * There is no efficient way to clean a specifid virtual
  175. * address range. Thus, cleans all.
  176. *
  177. * - start - virtual start address
  178. * - end - virtual end address
  179. */
  180. ENTRY(arm940_dma_clean_range)
  181. ENTRY(cpu_arm940_dcache_clean_area)
  182. mov ip, #0
  183. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  184. mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
  185. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  186. 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
  187. subs r3, r3, #1 << 26
  188. bcs 2b @ entries 63 to 0
  189. subs r1, r1, #1 << 4
  190. bcs 1b @ segments 7 to 0
  191. #endif
  192. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  193. mov pc, lr
  194. /*
  195. * dma_flush_range(start, end)
  196. *
  197. * There is no efficient way to clean and invalidate a specifid
  198. * virtual address range.
  199. *
  200. * - start - virtual start address
  201. * - end - virtual end address
  202. */
  203. ENTRY(arm940_dma_flush_range)
  204. mov ip, #0
  205. mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
  206. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  207. 2:
  208. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  209. mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
  210. #else
  211. mcr p15, 0, r3, c7, c10, 2 @ clean D entry
  212. #endif
  213. subs r3, r3, #1 << 26
  214. bcs 2b @ entries 63 to 0
  215. subs r1, r1, #1 << 4
  216. bcs 1b @ segments 7 to 0
  217. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  218. mov pc, lr
  219. ENTRY(arm940_cache_fns)
  220. .long arm940_flush_kern_cache_all
  221. .long arm940_flush_user_cache_all
  222. .long arm940_flush_user_cache_range
  223. .long arm940_coherent_kern_range
  224. .long arm940_coherent_user_range
  225. .long arm940_flush_kern_dcache_page
  226. .long arm940_dma_inv_range
  227. .long arm940_dma_clean_range
  228. .long arm940_dma_flush_range
  229. __INIT
  230. .type __arm940_setup, #function
  231. __arm940_setup:
  232. mov r0, #0
  233. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  234. mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
  235. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  236. mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
  237. mcr p15, 0, r0, c6, c4, 0
  238. mcr p15, 0, r0, c6, c5, 0
  239. mcr p15, 0, r0, c6, c6, 0
  240. mcr p15, 0, r0, c6, c7, 0
  241. mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
  242. mcr p15, 0, r0, c6, c4, 1
  243. mcr p15, 0, r0, c6, c5, 1
  244. mcr p15, 0, r0, c6, c6, 1
  245. mcr p15, 0, r0, c6, c7, 1
  246. mov r0, #0x0000003F @ base = 0, size = 4GB
  247. mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
  248. mcr p15, 0, r0, c6, c0, 1
  249. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  250. ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
  251. mov r2, #10 @ 11 is the minimum (4KB)
  252. 1: add r2, r2, #1 @ area size *= 2
  253. mov r1, r1, lsr #1
  254. bne 1b @ count not zero r-shift
  255. orr r0, r0, r2, lsl #1 @ the area register value
  256. orr r0, r0, #1 @ set enable bit
  257. mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
  258. mcr p15, 0, r0, c6, c1, 1
  259. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  260. ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
  261. mov r2, #10 @ 11 is the minimum (4KB)
  262. 1: add r2, r2, #1 @ area size *= 2
  263. mov r1, r1, lsr #1
  264. bne 1b @ count not zero r-shift
  265. orr r0, r0, r2, lsl #1 @ the area register value
  266. orr r0, r0, #1 @ set enable bit
  267. mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
  268. mcr p15, 0, r0, c6, c2, 1
  269. mov r0, #0x06
  270. mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
  271. mcr p15, 0, r0, c2, c0, 1
  272. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  273. mov r0, #0x00 @ disable whole write buffer
  274. #else
  275. mov r0, #0x02 @ Region 1 write bufferred
  276. #endif
  277. mcr p15, 0, r0, c3, c0, 0
  278. mov r0, #0x10000
  279. sub r0, r0, #1 @ r0 = 0xffff
  280. mcr p15, 0, r0, c5, c0, 0 @ all read/write access
  281. mcr p15, 0, r0, c5, c0, 1
  282. mrc p15, 0, r0, c1, c0 @ get control register
  283. orr r0, r0, #0x00001000 @ I-cache
  284. orr r0, r0, #0x00000005 @ MPU/D-cache
  285. mov pc, lr
  286. .size __arm940_setup, . - __arm940_setup
  287. __INITDATA
  288. /*
  289. * Purpose : Function pointers used to access above functions - all calls
  290. * come through these
  291. */
  292. .type arm940_processor_functions, #object
  293. ENTRY(arm940_processor_functions)
  294. .word nommu_early_abort
  295. .word cpu_arm940_proc_init
  296. .word cpu_arm940_proc_fin
  297. .word cpu_arm940_reset
  298. .word cpu_arm940_do_idle
  299. .word cpu_arm940_dcache_clean_area
  300. .word cpu_arm940_switch_mm
  301. .word 0 @ cpu_*_set_pte
  302. .size arm940_processor_functions, . - arm940_processor_functions
  303. .section ".rodata"
  304. .type cpu_arch_name, #object
  305. cpu_arch_name:
  306. .asciz "armv4t"
  307. .size cpu_arch_name, . - cpu_arch_name
  308. .type cpu_elf_name, #object
  309. cpu_elf_name:
  310. .asciz "v4"
  311. .size cpu_elf_name, . - cpu_elf_name
  312. .type cpu_arm940_name, #object
  313. cpu_arm940_name:
  314. .ascii "ARM940T"
  315. .size cpu_arm940_name, . - cpu_arm940_name
  316. .align
  317. .section ".proc.info.init", #alloc, #execinstr
  318. .type __arm940_proc_info,#object
  319. __arm940_proc_info:
  320. .long 0x41009400
  321. .long 0xff00fff0
  322. .long 0
  323. b __arm940_setup
  324. .long cpu_arch_name
  325. .long cpu_elf_name
  326. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  327. .long cpu_arm940_name
  328. .long arm940_processor_functions
  329. .long 0
  330. .long 0
  331. .long arm940_cache_fns
  332. .size __arm940_proc_info, . - __arm940_proc_info