proc-arm926.S 12 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
  3. *
  4. * Copyright (C) 1999-2001 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. *
  23. * These are the low level assembler for performing cache and TLB
  24. * functions on the arm926.
  25. *
  26. * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
  27. */
  28. #include <linux/linkage.h>
  29. #include <linux/init.h>
  30. #include <asm/assembler.h>
  31. #include <asm/elf.h>
  32. #include <asm/pgtable-hwdef.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/page.h>
  35. #include <asm/ptrace.h>
  36. #include "proc-macros.S"
  37. /*
  38. * This is the maximum size of an area which will be invalidated
  39. * using the single invalidate entry instructions. Anything larger
  40. * than this, and we go for the whole cache.
  41. *
  42. * This value should be chosen such that we choose the cheapest
  43. * alternative.
  44. */
  45. #define CACHE_DLIMIT 16384
  46. /*
  47. * the cache line size of the I and D cache
  48. */
  49. #define CACHE_DLINESIZE 32
  50. .text
  51. /*
  52. * cpu_arm926_proc_init()
  53. */
  54. ENTRY(cpu_arm926_proc_init)
  55. mov pc, lr
  56. /*
  57. * cpu_arm926_proc_fin()
  58. */
  59. ENTRY(cpu_arm926_proc_fin)
  60. stmfd sp!, {lr}
  61. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  62. msr cpsr_c, ip
  63. bl arm926_flush_kern_cache_all
  64. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  65. bic r0, r0, #0x1000 @ ...i............
  66. bic r0, r0, #0x000e @ ............wca.
  67. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  68. ldmfd sp!, {pc}
  69. /*
  70. * cpu_arm926_reset(loc)
  71. *
  72. * Perform a soft reset of the system. Put the CPU into the
  73. * same state as it would be if it had been reset, and branch
  74. * to what would be the reset vector.
  75. *
  76. * loc: location to jump to for soft reset
  77. */
  78. .align 5
  79. ENTRY(cpu_arm926_reset)
  80. mov ip, #0
  81. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  82. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  83. #ifdef CONFIG_MMU
  84. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  85. #endif
  86. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  87. bic ip, ip, #0x000f @ ............wcam
  88. bic ip, ip, #0x1100 @ ...i...s........
  89. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  90. mov pc, r0
  91. /*
  92. * cpu_arm926_do_idle()
  93. *
  94. * Called with IRQs disabled
  95. */
  96. .align 10
  97. ENTRY(cpu_arm926_do_idle)
  98. mov r0, #0
  99. mrc p15, 0, r1, c1, c0, 0 @ Read control register
  100. mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
  101. bic r2, r1, #1 << 12
  102. mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
  103. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  104. mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
  105. mov pc, lr
  106. /*
  107. * flush_user_cache_all()
  108. *
  109. * Clean and invalidate all cache entries in a particular
  110. * address space.
  111. */
  112. ENTRY(arm926_flush_user_cache_all)
  113. /* FALLTHROUGH */
  114. /*
  115. * flush_kern_cache_all()
  116. *
  117. * Clean and invalidate the entire cache.
  118. */
  119. ENTRY(arm926_flush_kern_cache_all)
  120. mov r2, #VM_EXEC
  121. mov ip, #0
  122. __flush_whole_cache:
  123. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  124. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  125. #else
  126. 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
  127. bne 1b
  128. #endif
  129. tst r2, #VM_EXEC
  130. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  131. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  132. mov pc, lr
  133. /*
  134. * flush_user_cache_range(start, end, flags)
  135. *
  136. * Clean and invalidate a range of cache entries in the
  137. * specified address range.
  138. *
  139. * - start - start address (inclusive)
  140. * - end - end address (exclusive)
  141. * - flags - vm_flags describing address space
  142. */
  143. ENTRY(arm926_flush_user_cache_range)
  144. mov ip, #0
  145. sub r3, r1, r0 @ calculate total size
  146. cmp r3, #CACHE_DLIMIT
  147. bgt __flush_whole_cache
  148. 1: tst r2, #VM_EXEC
  149. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  150. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  151. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  152. add r0, r0, #CACHE_DLINESIZE
  153. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  154. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  155. add r0, r0, #CACHE_DLINESIZE
  156. #else
  157. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  158. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  159. add r0, r0, #CACHE_DLINESIZE
  160. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  161. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  162. add r0, r0, #CACHE_DLINESIZE
  163. #endif
  164. cmp r0, r1
  165. blo 1b
  166. tst r2, #VM_EXEC
  167. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  168. mov pc, lr
  169. /*
  170. * coherent_kern_range(start, end)
  171. *
  172. * Ensure coherency between the Icache and the Dcache in the
  173. * region described by start, end. If you have non-snooping
  174. * Harvard caches, you need to implement this function.
  175. *
  176. * - start - virtual start address
  177. * - end - virtual end address
  178. */
  179. ENTRY(arm926_coherent_kern_range)
  180. /* FALLTHROUGH */
  181. /*
  182. * coherent_user_range(start, end)
  183. *
  184. * Ensure coherency between the Icache and the Dcache in the
  185. * region described by start, end. If you have non-snooping
  186. * Harvard caches, you need to implement this function.
  187. *
  188. * - start - virtual start address
  189. * - end - virtual end address
  190. */
  191. ENTRY(arm926_coherent_user_range)
  192. bic r0, r0, #CACHE_DLINESIZE - 1
  193. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  194. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  195. add r0, r0, #CACHE_DLINESIZE
  196. cmp r0, r1
  197. blo 1b
  198. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  199. mov pc, lr
  200. /*
  201. * flush_kern_dcache_page(void *page)
  202. *
  203. * Ensure no D cache aliasing occurs, either with itself or
  204. * the I cache
  205. *
  206. * - addr - page aligned address
  207. */
  208. ENTRY(arm926_flush_kern_dcache_page)
  209. add r1, r0, #PAGE_SZ
  210. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  211. add r0, r0, #CACHE_DLINESIZE
  212. cmp r0, r1
  213. blo 1b
  214. mov r0, #0
  215. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  216. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  217. mov pc, lr
  218. /*
  219. * dma_inv_range(start, end)
  220. *
  221. * Invalidate (discard) the specified virtual address range.
  222. * May not write back any entries. If 'start' or 'end'
  223. * are not cache line aligned, those lines must be written
  224. * back.
  225. *
  226. * - start - virtual start address
  227. * - end - virtual end address
  228. *
  229. * (same as v4wb)
  230. */
  231. ENTRY(arm926_dma_inv_range)
  232. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  233. tst r0, #CACHE_DLINESIZE - 1
  234. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  235. tst r1, #CACHE_DLINESIZE - 1
  236. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  237. #endif
  238. bic r0, r0, #CACHE_DLINESIZE - 1
  239. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  240. add r0, r0, #CACHE_DLINESIZE
  241. cmp r0, r1
  242. blo 1b
  243. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  244. mov pc, lr
  245. /*
  246. * dma_clean_range(start, end)
  247. *
  248. * Clean the specified virtual address range.
  249. *
  250. * - start - virtual start address
  251. * - end - virtual end address
  252. *
  253. * (same as v4wb)
  254. */
  255. ENTRY(arm926_dma_clean_range)
  256. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  257. bic r0, r0, #CACHE_DLINESIZE - 1
  258. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  259. add r0, r0, #CACHE_DLINESIZE
  260. cmp r0, r1
  261. blo 1b
  262. #endif
  263. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  264. mov pc, lr
  265. /*
  266. * dma_flush_range(start, end)
  267. *
  268. * Clean and invalidate the specified virtual address range.
  269. *
  270. * - start - virtual start address
  271. * - end - virtual end address
  272. */
  273. ENTRY(arm926_dma_flush_range)
  274. bic r0, r0, #CACHE_DLINESIZE - 1
  275. 1:
  276. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  277. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  278. #else
  279. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  280. #endif
  281. add r0, r0, #CACHE_DLINESIZE
  282. cmp r0, r1
  283. blo 1b
  284. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  285. mov pc, lr
  286. ENTRY(arm926_cache_fns)
  287. .long arm926_flush_kern_cache_all
  288. .long arm926_flush_user_cache_all
  289. .long arm926_flush_user_cache_range
  290. .long arm926_coherent_kern_range
  291. .long arm926_coherent_user_range
  292. .long arm926_flush_kern_dcache_page
  293. .long arm926_dma_inv_range
  294. .long arm926_dma_clean_range
  295. .long arm926_dma_flush_range
  296. ENTRY(cpu_arm926_dcache_clean_area)
  297. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  298. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  299. add r0, r0, #CACHE_DLINESIZE
  300. subs r1, r1, #CACHE_DLINESIZE
  301. bhi 1b
  302. #endif
  303. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  304. mov pc, lr
  305. /* =============================== PageTable ============================== */
  306. /*
  307. * cpu_arm926_switch_mm(pgd)
  308. *
  309. * Set the translation base pointer to be as described by pgd.
  310. *
  311. * pgd: new page tables
  312. */
  313. .align 5
  314. ENTRY(cpu_arm926_switch_mm)
  315. #ifdef CONFIG_MMU
  316. mov ip, #0
  317. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  318. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  319. #else
  320. @ && 'Clean & Invalidate whole DCache'
  321. 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
  322. bne 1b
  323. #endif
  324. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  325. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  326. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  327. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  328. #endif
  329. mov pc, lr
  330. /*
  331. * cpu_arm926_set_pte_ext(ptep, pte, ext)
  332. *
  333. * Set a PTE and flush it out
  334. */
  335. .align 5
  336. ENTRY(cpu_arm926_set_pte_ext)
  337. #ifdef CONFIG_MMU
  338. str r1, [r0], #-2048 @ linux version
  339. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  340. bic r2, r1, #PTE_SMALL_AP_MASK
  341. bic r2, r2, #PTE_TYPE_MASK
  342. orr r2, r2, #PTE_TYPE_SMALL
  343. tst r1, #L_PTE_USER @ User?
  344. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  345. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  346. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  347. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  348. movne r2, #0
  349. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  350. eor r3, r2, #0x0a @ C & small page?
  351. tst r3, #0x0b
  352. biceq r2, r2, #4
  353. #endif
  354. str r2, [r0] @ hardware version
  355. mov r0, r0
  356. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  357. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  358. #endif
  359. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  360. #endif
  361. mov pc, lr
  362. __INIT
  363. .type __arm926_setup, #function
  364. __arm926_setup:
  365. mov r0, #0
  366. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  367. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  368. #ifdef CONFIG_MMU
  369. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  370. #endif
  371. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  372. mov r0, #4 @ disable write-back on caches explicitly
  373. mcr p15, 7, r0, c15, c0, 0
  374. #endif
  375. adr r5, arm926_crval
  376. ldmia r5, {r5, r6}
  377. mrc p15, 0, r0, c1, c0 @ get control register v4
  378. bic r0, r0, r5
  379. orr r0, r0, r6
  380. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  381. orr r0, r0, #0x4000 @ .1.. .... .... ....
  382. #endif
  383. mov pc, lr
  384. .size __arm926_setup, . - __arm926_setup
  385. /*
  386. * R
  387. * .RVI ZFRS BLDP WCAM
  388. * .011 0001 ..11 0101
  389. *
  390. */
  391. .type arm926_crval, #object
  392. arm926_crval:
  393. crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
  394. __INITDATA
  395. /*
  396. * Purpose : Function pointers used to access above functions - all calls
  397. * come through these
  398. */
  399. .type arm926_processor_functions, #object
  400. arm926_processor_functions:
  401. .word v5tj_early_abort
  402. .word cpu_arm926_proc_init
  403. .word cpu_arm926_proc_fin
  404. .word cpu_arm926_reset
  405. .word cpu_arm926_do_idle
  406. .word cpu_arm926_dcache_clean_area
  407. .word cpu_arm926_switch_mm
  408. .word cpu_arm926_set_pte_ext
  409. .size arm926_processor_functions, . - arm926_processor_functions
  410. .section ".rodata"
  411. .type cpu_arch_name, #object
  412. cpu_arch_name:
  413. .asciz "armv5tej"
  414. .size cpu_arch_name, . - cpu_arch_name
  415. .type cpu_elf_name, #object
  416. cpu_elf_name:
  417. .asciz "v5"
  418. .size cpu_elf_name, . - cpu_elf_name
  419. .type cpu_arm926_name, #object
  420. cpu_arm926_name:
  421. .asciz "ARM926EJ-S"
  422. .size cpu_arm926_name, . - cpu_arm926_name
  423. .align
  424. .section ".proc.info.init", #alloc, #execinstr
  425. .type __arm926_proc_info,#object
  426. __arm926_proc_info:
  427. .long 0x41069260 @ ARM926EJ-S (v5TEJ)
  428. .long 0xff0ffff0
  429. .long PMD_TYPE_SECT | \
  430. PMD_SECT_BUFFERABLE | \
  431. PMD_SECT_CACHEABLE | \
  432. PMD_BIT4 | \
  433. PMD_SECT_AP_WRITE | \
  434. PMD_SECT_AP_READ
  435. .long PMD_TYPE_SECT | \
  436. PMD_BIT4 | \
  437. PMD_SECT_AP_WRITE | \
  438. PMD_SECT_AP_READ
  439. b __arm926_setup
  440. .long cpu_arch_name
  441. .long cpu_elf_name
  442. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
  443. .long cpu_arm926_name
  444. .long arm926_processor_functions
  445. .long v4wbi_tlb_fns
  446. .long v4wb_user_fns
  447. .long arm926_cache_fns
  448. .size __arm926_proc_info, . - __arm926_proc_info