proc-arm925.S 14 KB

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  1. /*
  2. * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
  3. *
  4. * Copyright (C) 1999,2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * Copyright (C) 2002 RidgeRun, Inc.
  7. * Copyright (C) 2002-2003 MontaVista Software, Inc.
  8. *
  9. * Update for Linux-2.6 and cache flush improvements
  10. * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
  11. *
  12. * hacked for non-paged-MM by Hyok S. Choi, 2004.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  27. *
  28. *
  29. * These are the low level assembler for performing cache and TLB
  30. * functions on the arm925.
  31. *
  32. * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
  33. *
  34. * Some additional notes based on deciphering the TI TRM on OMAP-5910:
  35. *
  36. * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
  37. * entry mode" must be 0 to flush the entries in both segments
  38. * at once. This is the default value. See TRM 2-20 and 2-24 for
  39. * more information.
  40. *
  41. * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
  42. * like the "Transparent mode" must be on for partial cache flushes
  43. * to work in this mode. This mode only works with 16-bit external
  44. * memory. See TRM 2-24 for more information.
  45. *
  46. * NOTE3: Write-back cache flushing seems to be flakey with devices using
  47. * direct memory access, such as USB OHCI. The workaround is to use
  48. * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
  49. * the default for OMAP-1510).
  50. */
  51. #include <linux/linkage.h>
  52. #include <linux/init.h>
  53. #include <asm/assembler.h>
  54. #include <asm/elf.h>
  55. #include <asm/pgtable-hwdef.h>
  56. #include <asm/pgtable.h>
  57. #include <asm/page.h>
  58. #include <asm/ptrace.h>
  59. #include "proc-macros.S"
  60. /*
  61. * The size of one data cache line.
  62. */
  63. #define CACHE_DLINESIZE 16
  64. /*
  65. * The number of data cache segments.
  66. */
  67. #define CACHE_DSEGMENTS 2
  68. /*
  69. * The number of lines in a cache segment.
  70. */
  71. #define CACHE_DENTRIES 256
  72. /*
  73. * This is the size at which it becomes more efficient to
  74. * clean the whole cache, rather than using the individual
  75. * cache line maintainence instructions.
  76. */
  77. #define CACHE_DLIMIT 8192
  78. .text
  79. /*
  80. * cpu_arm925_proc_init()
  81. */
  82. ENTRY(cpu_arm925_proc_init)
  83. mov pc, lr
  84. /*
  85. * cpu_arm925_proc_fin()
  86. */
  87. ENTRY(cpu_arm925_proc_fin)
  88. stmfd sp!, {lr}
  89. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  90. msr cpsr_c, ip
  91. bl arm925_flush_kern_cache_all
  92. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  93. bic r0, r0, #0x1000 @ ...i............
  94. bic r0, r0, #0x000e @ ............wca.
  95. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  96. ldmfd sp!, {pc}
  97. /*
  98. * cpu_arm925_reset(loc)
  99. *
  100. * Perform a soft reset of the system. Put the CPU into the
  101. * same state as it would be if it had been reset, and branch
  102. * to what would be the reset vector.
  103. *
  104. * loc: location to jump to for soft reset
  105. */
  106. .align 5
  107. ENTRY(cpu_arm925_reset)
  108. /* Send software reset to MPU and DSP */
  109. mov ip, #0xff000000
  110. orr ip, ip, #0x00fe0000
  111. orr ip, ip, #0x0000ce00
  112. mov r4, #1
  113. strh r4, [ip, #0x10]
  114. mov ip, #0
  115. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  116. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  117. #ifdef CONFIG_MMU
  118. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  119. #endif
  120. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  121. bic ip, ip, #0x000f @ ............wcam
  122. bic ip, ip, #0x1100 @ ...i...s........
  123. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  124. mov pc, r0
  125. /*
  126. * cpu_arm925_do_idle()
  127. *
  128. * Called with IRQs disabled
  129. */
  130. .align 10
  131. ENTRY(cpu_arm925_do_idle)
  132. mov r0, #0
  133. mrc p15, 0, r1, c1, c0, 0 @ Read control register
  134. mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
  135. bic r2, r1, #1 << 12
  136. mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
  137. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  138. mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
  139. mov pc, lr
  140. /*
  141. * flush_user_cache_all()
  142. *
  143. * Clean and invalidate all cache entries in a particular
  144. * address space.
  145. */
  146. ENTRY(arm925_flush_user_cache_all)
  147. /* FALLTHROUGH */
  148. /*
  149. * flush_kern_cache_all()
  150. *
  151. * Clean and invalidate the entire cache.
  152. */
  153. ENTRY(arm925_flush_kern_cache_all)
  154. mov r2, #VM_EXEC
  155. mov ip, #0
  156. __flush_whole_cache:
  157. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  158. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  159. #else
  160. /* Flush entries in both segments at once, see NOTE1 above */
  161. mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
  162. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  163. subs r3, r3, #1 << 4
  164. bcs 2b @ entries 255 to 0
  165. #endif
  166. tst r2, #VM_EXEC
  167. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  168. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  169. mov pc, lr
  170. /*
  171. * flush_user_cache_range(start, end, flags)
  172. *
  173. * Clean and invalidate a range of cache entries in the
  174. * specified address range.
  175. *
  176. * - start - start address (inclusive)
  177. * - end - end address (exclusive)
  178. * - flags - vm_flags describing address space
  179. */
  180. ENTRY(arm925_flush_user_cache_range)
  181. mov ip, #0
  182. sub r3, r1, r0 @ calculate total size
  183. cmp r3, #CACHE_DLIMIT
  184. bgt __flush_whole_cache
  185. 1: tst r2, #VM_EXEC
  186. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  187. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  188. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  189. add r0, r0, #CACHE_DLINESIZE
  190. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  191. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  192. add r0, r0, #CACHE_DLINESIZE
  193. #else
  194. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  195. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  196. add r0, r0, #CACHE_DLINESIZE
  197. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  198. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  199. add r0, r0, #CACHE_DLINESIZE
  200. #endif
  201. cmp r0, r1
  202. blo 1b
  203. tst r2, #VM_EXEC
  204. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  205. mov pc, lr
  206. /*
  207. * coherent_kern_range(start, end)
  208. *
  209. * Ensure coherency between the Icache and the Dcache in the
  210. * region described by start, end. If you have non-snooping
  211. * Harvard caches, you need to implement this function.
  212. *
  213. * - start - virtual start address
  214. * - end - virtual end address
  215. */
  216. ENTRY(arm925_coherent_kern_range)
  217. /* FALLTHROUGH */
  218. /*
  219. * coherent_user_range(start, end)
  220. *
  221. * Ensure coherency between the Icache and the Dcache in the
  222. * region described by start, end. If you have non-snooping
  223. * Harvard caches, you need to implement this function.
  224. *
  225. * - start - virtual start address
  226. * - end - virtual end address
  227. */
  228. ENTRY(arm925_coherent_user_range)
  229. bic r0, r0, #CACHE_DLINESIZE - 1
  230. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  231. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  232. add r0, r0, #CACHE_DLINESIZE
  233. cmp r0, r1
  234. blo 1b
  235. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  236. mov pc, lr
  237. /*
  238. * flush_kern_dcache_page(void *page)
  239. *
  240. * Ensure no D cache aliasing occurs, either with itself or
  241. * the I cache
  242. *
  243. * - addr - page aligned address
  244. */
  245. ENTRY(arm925_flush_kern_dcache_page)
  246. add r1, r0, #PAGE_SZ
  247. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  248. add r0, r0, #CACHE_DLINESIZE
  249. cmp r0, r1
  250. blo 1b
  251. mov r0, #0
  252. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  253. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  254. mov pc, lr
  255. /*
  256. * dma_inv_range(start, end)
  257. *
  258. * Invalidate (discard) the specified virtual address range.
  259. * May not write back any entries. If 'start' or 'end'
  260. * are not cache line aligned, those lines must be written
  261. * back.
  262. *
  263. * - start - virtual start address
  264. * - end - virtual end address
  265. *
  266. * (same as v4wb)
  267. */
  268. ENTRY(arm925_dma_inv_range)
  269. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  270. tst r0, #CACHE_DLINESIZE - 1
  271. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  272. tst r1, #CACHE_DLINESIZE - 1
  273. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  274. #endif
  275. bic r0, r0, #CACHE_DLINESIZE - 1
  276. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  277. add r0, r0, #CACHE_DLINESIZE
  278. cmp r0, r1
  279. blo 1b
  280. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  281. mov pc, lr
  282. /*
  283. * dma_clean_range(start, end)
  284. *
  285. * Clean the specified virtual address range.
  286. *
  287. * - start - virtual start address
  288. * - end - virtual end address
  289. *
  290. * (same as v4wb)
  291. */
  292. ENTRY(arm925_dma_clean_range)
  293. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  294. bic r0, r0, #CACHE_DLINESIZE - 1
  295. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  296. add r0, r0, #CACHE_DLINESIZE
  297. cmp r0, r1
  298. blo 1b
  299. #endif
  300. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  301. mov pc, lr
  302. /*
  303. * dma_flush_range(start, end)
  304. *
  305. * Clean and invalidate the specified virtual address range.
  306. *
  307. * - start - virtual start address
  308. * - end - virtual end address
  309. */
  310. ENTRY(arm925_dma_flush_range)
  311. bic r0, r0, #CACHE_DLINESIZE - 1
  312. 1:
  313. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  314. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  315. #else
  316. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  317. #endif
  318. add r0, r0, #CACHE_DLINESIZE
  319. cmp r0, r1
  320. blo 1b
  321. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  322. mov pc, lr
  323. ENTRY(arm925_cache_fns)
  324. .long arm925_flush_kern_cache_all
  325. .long arm925_flush_user_cache_all
  326. .long arm925_flush_user_cache_range
  327. .long arm925_coherent_kern_range
  328. .long arm925_coherent_user_range
  329. .long arm925_flush_kern_dcache_page
  330. .long arm925_dma_inv_range
  331. .long arm925_dma_clean_range
  332. .long arm925_dma_flush_range
  333. ENTRY(cpu_arm925_dcache_clean_area)
  334. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  335. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  336. add r0, r0, #CACHE_DLINESIZE
  337. subs r1, r1, #CACHE_DLINESIZE
  338. bhi 1b
  339. #endif
  340. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  341. mov pc, lr
  342. /* =============================== PageTable ============================== */
  343. /*
  344. * cpu_arm925_switch_mm(pgd)
  345. *
  346. * Set the translation base pointer to be as described by pgd.
  347. *
  348. * pgd: new page tables
  349. */
  350. .align 5
  351. ENTRY(cpu_arm925_switch_mm)
  352. #ifdef CONFIG_MMU
  353. mov ip, #0
  354. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  355. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  356. #else
  357. /* Flush entries in bothe segments at once, see NOTE1 above */
  358. mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
  359. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  360. subs r3, r3, #1 << 4
  361. bcs 2b @ entries 255 to 0
  362. #endif
  363. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  364. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  365. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  366. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  367. #endif
  368. mov pc, lr
  369. /*
  370. * cpu_arm925_set_pte_ext(ptep, pte, ext)
  371. *
  372. * Set a PTE and flush it out
  373. */
  374. .align 5
  375. ENTRY(cpu_arm925_set_pte_ext)
  376. #ifdef CONFIG_MMU
  377. str r1, [r0], #-2048 @ linux version
  378. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  379. bic r2, r1, #PTE_SMALL_AP_MASK
  380. bic r2, r2, #PTE_TYPE_MASK
  381. orr r2, r2, #PTE_TYPE_SMALL
  382. tst r1, #L_PTE_USER @ User?
  383. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  384. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  385. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  386. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  387. movne r2, #0
  388. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  389. eor r3, r2, #0x0a @ C & small page?
  390. tst r3, #0x0b
  391. biceq r2, r2, #4
  392. #endif
  393. str r2, [r0] @ hardware version
  394. mov r0, r0
  395. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  396. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  397. #endif
  398. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  399. #endif /* CONFIG_MMU */
  400. mov pc, lr
  401. __INIT
  402. .type __arm925_setup, #function
  403. __arm925_setup:
  404. mov r0, #0
  405. #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
  406. orr r0,r0,#1 << 7
  407. #endif
  408. /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
  409. orr r0,r0,#1 << 1 @ transparent mode on
  410. mcr p15, 0, r0, c15, c1, 0 @ write TI config register
  411. mov r0, #0
  412. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  413. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  414. #ifdef CONFIG_MMU
  415. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  416. #endif
  417. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  418. mov r0, #4 @ disable write-back on caches explicitly
  419. mcr p15, 7, r0, c15, c0, 0
  420. #endif
  421. adr r5, arm925_crval
  422. ldmia r5, {r5, r6}
  423. mrc p15, 0, r0, c1, c0 @ get control register v4
  424. bic r0, r0, r5
  425. orr r0, r0, r6
  426. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  427. orr r0, r0, #0x4000 @ .1.. .... .... ....
  428. #endif
  429. mov pc, lr
  430. .size __arm925_setup, . - __arm925_setup
  431. /*
  432. * R
  433. * .RVI ZFRS BLDP WCAM
  434. * .011 0001 ..11 1101
  435. *
  436. */
  437. .type arm925_crval, #object
  438. arm925_crval:
  439. crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
  440. __INITDATA
  441. /*
  442. * Purpose : Function pointers used to access above functions - all calls
  443. * come through these
  444. */
  445. .type arm925_processor_functions, #object
  446. arm925_processor_functions:
  447. .word v4t_early_abort
  448. .word cpu_arm925_proc_init
  449. .word cpu_arm925_proc_fin
  450. .word cpu_arm925_reset
  451. .word cpu_arm925_do_idle
  452. .word cpu_arm925_dcache_clean_area
  453. .word cpu_arm925_switch_mm
  454. .word cpu_arm925_set_pte_ext
  455. .size arm925_processor_functions, . - arm925_processor_functions
  456. .section ".rodata"
  457. .type cpu_arch_name, #object
  458. cpu_arch_name:
  459. .asciz "armv4t"
  460. .size cpu_arch_name, . - cpu_arch_name
  461. .type cpu_elf_name, #object
  462. cpu_elf_name:
  463. .asciz "v4"
  464. .size cpu_elf_name, . - cpu_elf_name
  465. .type cpu_arm925_name, #object
  466. cpu_arm925_name:
  467. .asciz "ARM925T"
  468. .size cpu_arm925_name, . - cpu_arm925_name
  469. .align
  470. .section ".proc.info.init", #alloc, #execinstr
  471. .type __arm925_proc_info,#object
  472. __arm925_proc_info:
  473. .long 0x54029250
  474. .long 0xfffffff0
  475. .long PMD_TYPE_SECT | \
  476. PMD_BIT4 | \
  477. PMD_SECT_AP_WRITE | \
  478. PMD_SECT_AP_READ
  479. .long PMD_TYPE_SECT | \
  480. PMD_BIT4 | \
  481. PMD_SECT_AP_WRITE | \
  482. PMD_SECT_AP_READ
  483. b __arm925_setup
  484. .long cpu_arch_name
  485. .long cpu_elf_name
  486. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  487. .long cpu_arm925_name
  488. .long arm925_processor_functions
  489. .long v4wbi_tlb_fns
  490. .long v4wb_user_fns
  491. .long arm925_cache_fns
  492. .size __arm925_proc_info, . - __arm925_proc_info
  493. .type __arm915_proc_info,#object
  494. __arm915_proc_info:
  495. .long 0x54029150
  496. .long 0xfffffff0
  497. .long PMD_TYPE_SECT | \
  498. PMD_BIT4 | \
  499. PMD_SECT_AP_WRITE | \
  500. PMD_SECT_AP_READ
  501. .long PMD_TYPE_SECT | \
  502. PMD_BIT4 | \
  503. PMD_SECT_AP_WRITE | \
  504. PMD_SECT_AP_READ
  505. b __arm925_setup
  506. .long cpu_arch_name
  507. .long cpu_elf_name
  508. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  509. .long cpu_arm925_name
  510. .long arm925_processor_functions
  511. .long v4wbi_tlb_fns
  512. .long v4wb_user_fns
  513. .long arm925_cache_fns
  514. .size __arm925_proc_info, . - __arm925_proc_info