proc-arm922.S 12 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
  3. *
  4. * Copyright (C) 1999,2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * Copyright (C) 2001 Altera Corporation
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. *
  24. * These are the low level assembler for performing cache and TLB
  25. * functions on the arm922.
  26. *
  27. * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
  28. */
  29. #include <linux/linkage.h>
  30. #include <linux/init.h>
  31. #include <asm/assembler.h>
  32. #include <asm/elf.h>
  33. #include <asm/pgtable-hwdef.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/page.h>
  36. #include <asm/ptrace.h>
  37. #include "proc-macros.S"
  38. /*
  39. * The size of one data cache line.
  40. */
  41. #define CACHE_DLINESIZE 32
  42. /*
  43. * The number of data cache segments.
  44. */
  45. #define CACHE_DSEGMENTS 4
  46. /*
  47. * The number of lines in a cache segment.
  48. */
  49. #define CACHE_DENTRIES 64
  50. /*
  51. * This is the size at which it becomes more efficient to
  52. * clean the whole cache, rather than using the individual
  53. * cache line maintainence instructions. (I think this should
  54. * be 32768).
  55. */
  56. #define CACHE_DLIMIT 8192
  57. .text
  58. /*
  59. * cpu_arm922_proc_init()
  60. */
  61. ENTRY(cpu_arm922_proc_init)
  62. mov pc, lr
  63. /*
  64. * cpu_arm922_proc_fin()
  65. */
  66. ENTRY(cpu_arm922_proc_fin)
  67. stmfd sp!, {lr}
  68. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  69. msr cpsr_c, ip
  70. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  71. bl arm922_flush_kern_cache_all
  72. #else
  73. bl v4wt_flush_kern_cache_all
  74. #endif
  75. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  76. bic r0, r0, #0x1000 @ ...i............
  77. bic r0, r0, #0x000e @ ............wca.
  78. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  79. ldmfd sp!, {pc}
  80. /*
  81. * cpu_arm922_reset(loc)
  82. *
  83. * Perform a soft reset of the system. Put the CPU into the
  84. * same state as it would be if it had been reset, and branch
  85. * to what would be the reset vector.
  86. *
  87. * loc: location to jump to for soft reset
  88. */
  89. .align 5
  90. ENTRY(cpu_arm922_reset)
  91. mov ip, #0
  92. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  93. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  94. #ifdef CONFIG_MMU
  95. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  96. #endif
  97. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  98. bic ip, ip, #0x000f @ ............wcam
  99. bic ip, ip, #0x1100 @ ...i...s........
  100. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  101. mov pc, r0
  102. /*
  103. * cpu_arm922_do_idle()
  104. */
  105. .align 5
  106. ENTRY(cpu_arm922_do_idle)
  107. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  108. mov pc, lr
  109. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  110. /*
  111. * flush_user_cache_all()
  112. *
  113. * Clean and invalidate all cache entries in a particular
  114. * address space.
  115. */
  116. ENTRY(arm922_flush_user_cache_all)
  117. /* FALLTHROUGH */
  118. /*
  119. * flush_kern_cache_all()
  120. *
  121. * Clean and invalidate the entire cache.
  122. */
  123. ENTRY(arm922_flush_kern_cache_all)
  124. mov r2, #VM_EXEC
  125. mov ip, #0
  126. __flush_whole_cache:
  127. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  128. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  129. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  130. subs r3, r3, #1 << 26
  131. bcs 2b @ entries 63 to 0
  132. subs r1, r1, #1 << 5
  133. bcs 1b @ segments 7 to 0
  134. tst r2, #VM_EXEC
  135. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  136. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  137. mov pc, lr
  138. /*
  139. * flush_user_cache_range(start, end, flags)
  140. *
  141. * Clean and invalidate a range of cache entries in the
  142. * specified address range.
  143. *
  144. * - start - start address (inclusive)
  145. * - end - end address (exclusive)
  146. * - flags - vm_flags describing address space
  147. */
  148. ENTRY(arm922_flush_user_cache_range)
  149. mov ip, #0
  150. sub r3, r1, r0 @ calculate total size
  151. cmp r3, #CACHE_DLIMIT
  152. bhs __flush_whole_cache
  153. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  154. tst r2, #VM_EXEC
  155. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  156. add r0, r0, #CACHE_DLINESIZE
  157. cmp r0, r1
  158. blo 1b
  159. tst r2, #VM_EXEC
  160. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  161. mov pc, lr
  162. /*
  163. * coherent_kern_range(start, end)
  164. *
  165. * Ensure coherency between the Icache and the Dcache in the
  166. * region described by start, end. If you have non-snooping
  167. * Harvard caches, you need to implement this function.
  168. *
  169. * - start - virtual start address
  170. * - end - virtual end address
  171. */
  172. ENTRY(arm922_coherent_kern_range)
  173. /* FALLTHROUGH */
  174. /*
  175. * coherent_user_range(start, end)
  176. *
  177. * Ensure coherency between the Icache and the Dcache in the
  178. * region described by start, end. If you have non-snooping
  179. * Harvard caches, you need to implement this function.
  180. *
  181. * - start - virtual start address
  182. * - end - virtual end address
  183. */
  184. ENTRY(arm922_coherent_user_range)
  185. bic r0, r0, #CACHE_DLINESIZE - 1
  186. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  187. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  188. add r0, r0, #CACHE_DLINESIZE
  189. cmp r0, r1
  190. blo 1b
  191. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  192. mov pc, lr
  193. /*
  194. * flush_kern_dcache_page(void *page)
  195. *
  196. * Ensure no D cache aliasing occurs, either with itself or
  197. * the I cache
  198. *
  199. * - addr - page aligned address
  200. */
  201. ENTRY(arm922_flush_kern_dcache_page)
  202. add r1, r0, #PAGE_SZ
  203. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  204. add r0, r0, #CACHE_DLINESIZE
  205. cmp r0, r1
  206. blo 1b
  207. mov r0, #0
  208. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  209. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  210. mov pc, lr
  211. /*
  212. * dma_inv_range(start, end)
  213. *
  214. * Invalidate (discard) the specified virtual address range.
  215. * May not write back any entries. If 'start' or 'end'
  216. * are not cache line aligned, those lines must be written
  217. * back.
  218. *
  219. * - start - virtual start address
  220. * - end - virtual end address
  221. *
  222. * (same as v4wb)
  223. */
  224. ENTRY(arm922_dma_inv_range)
  225. tst r0, #CACHE_DLINESIZE - 1
  226. bic r0, r0, #CACHE_DLINESIZE - 1
  227. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  228. tst r1, #CACHE_DLINESIZE - 1
  229. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  230. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  231. add r0, r0, #CACHE_DLINESIZE
  232. cmp r0, r1
  233. blo 1b
  234. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  235. mov pc, lr
  236. /*
  237. * dma_clean_range(start, end)
  238. *
  239. * Clean the specified virtual address range.
  240. *
  241. * - start - virtual start address
  242. * - end - virtual end address
  243. *
  244. * (same as v4wb)
  245. */
  246. ENTRY(arm922_dma_clean_range)
  247. bic r0, r0, #CACHE_DLINESIZE - 1
  248. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  249. add r0, r0, #CACHE_DLINESIZE
  250. cmp r0, r1
  251. blo 1b
  252. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  253. mov pc, lr
  254. /*
  255. * dma_flush_range(start, end)
  256. *
  257. * Clean and invalidate the specified virtual address range.
  258. *
  259. * - start - virtual start address
  260. * - end - virtual end address
  261. */
  262. ENTRY(arm922_dma_flush_range)
  263. bic r0, r0, #CACHE_DLINESIZE - 1
  264. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  265. add r0, r0, #CACHE_DLINESIZE
  266. cmp r0, r1
  267. blo 1b
  268. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  269. mov pc, lr
  270. ENTRY(arm922_cache_fns)
  271. .long arm922_flush_kern_cache_all
  272. .long arm922_flush_user_cache_all
  273. .long arm922_flush_user_cache_range
  274. .long arm922_coherent_kern_range
  275. .long arm922_coherent_user_range
  276. .long arm922_flush_kern_dcache_page
  277. .long arm922_dma_inv_range
  278. .long arm922_dma_clean_range
  279. .long arm922_dma_flush_range
  280. #endif
  281. ENTRY(cpu_arm922_dcache_clean_area)
  282. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  283. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  284. add r0, r0, #CACHE_DLINESIZE
  285. subs r1, r1, #CACHE_DLINESIZE
  286. bhi 1b
  287. #endif
  288. mov pc, lr
  289. /* =============================== PageTable ============================== */
  290. /*
  291. * cpu_arm922_switch_mm(pgd)
  292. *
  293. * Set the translation base pointer to be as described by pgd.
  294. *
  295. * pgd: new page tables
  296. */
  297. .align 5
  298. ENTRY(cpu_arm922_switch_mm)
  299. #ifdef CONFIG_MMU
  300. mov ip, #0
  301. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  302. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  303. #else
  304. @ && 'Clean & Invalidate whole DCache'
  305. @ && Re-written to use Index Ops.
  306. @ && Uses registers r1, r3 and ip
  307. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
  308. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  309. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  310. subs r3, r3, #1 << 26
  311. bcs 2b @ entries 63 to 0
  312. subs r1, r1, #1 << 5
  313. bcs 1b @ segments 7 to 0
  314. #endif
  315. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  316. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  317. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  318. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  319. #endif
  320. mov pc, lr
  321. /*
  322. * cpu_arm922_set_pte_ext(ptep, pte, ext)
  323. *
  324. * Set a PTE and flush it out
  325. */
  326. .align 5
  327. ENTRY(cpu_arm922_set_pte_ext)
  328. #ifdef CONFIG_MMU
  329. str r1, [r0], #-2048 @ linux version
  330. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  331. bic r2, r1, #PTE_SMALL_AP_MASK
  332. bic r2, r2, #PTE_TYPE_MASK
  333. orr r2, r2, #PTE_TYPE_SMALL
  334. tst r1, #L_PTE_USER @ User?
  335. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  336. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  337. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  338. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  339. movne r2, #0
  340. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  341. eor r3, r2, #0x0a @ C & small page?
  342. tst r3, #0x0b
  343. biceq r2, r2, #4
  344. #endif
  345. str r2, [r0] @ hardware version
  346. mov r0, r0
  347. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  348. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  349. #endif /* CONFIG_MMU */
  350. mov pc, lr
  351. __INIT
  352. .type __arm922_setup, #function
  353. __arm922_setup:
  354. mov r0, #0
  355. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  356. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  357. #ifdef CONFIG_MMU
  358. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  359. #endif
  360. adr r5, arm922_crval
  361. ldmia r5, {r5, r6}
  362. mrc p15, 0, r0, c1, c0 @ get control register v4
  363. bic r0, r0, r5
  364. orr r0, r0, r6
  365. mov pc, lr
  366. .size __arm922_setup, . - __arm922_setup
  367. /*
  368. * R
  369. * .RVI ZFRS BLDP WCAM
  370. * ..11 0001 ..11 0101
  371. *
  372. */
  373. .type arm922_crval, #object
  374. arm922_crval:
  375. crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  376. __INITDATA
  377. /*
  378. * Purpose : Function pointers used to access above functions - all calls
  379. * come through these
  380. */
  381. .type arm922_processor_functions, #object
  382. arm922_processor_functions:
  383. .word v4t_early_abort
  384. .word cpu_arm922_proc_init
  385. .word cpu_arm922_proc_fin
  386. .word cpu_arm922_reset
  387. .word cpu_arm922_do_idle
  388. .word cpu_arm922_dcache_clean_area
  389. .word cpu_arm922_switch_mm
  390. .word cpu_arm922_set_pte_ext
  391. .size arm922_processor_functions, . - arm922_processor_functions
  392. .section ".rodata"
  393. .type cpu_arch_name, #object
  394. cpu_arch_name:
  395. .asciz "armv4t"
  396. .size cpu_arch_name, . - cpu_arch_name
  397. .type cpu_elf_name, #object
  398. cpu_elf_name:
  399. .asciz "v4"
  400. .size cpu_elf_name, . - cpu_elf_name
  401. .type cpu_arm922_name, #object
  402. cpu_arm922_name:
  403. .asciz "ARM922T"
  404. .size cpu_arm922_name, . - cpu_arm922_name
  405. .align
  406. .section ".proc.info.init", #alloc, #execinstr
  407. .type __arm922_proc_info,#object
  408. __arm922_proc_info:
  409. .long 0x41009220
  410. .long 0xff00fff0
  411. .long PMD_TYPE_SECT | \
  412. PMD_SECT_BUFFERABLE | \
  413. PMD_SECT_CACHEABLE | \
  414. PMD_BIT4 | \
  415. PMD_SECT_AP_WRITE | \
  416. PMD_SECT_AP_READ
  417. .long PMD_TYPE_SECT | \
  418. PMD_BIT4 | \
  419. PMD_SECT_AP_WRITE | \
  420. PMD_SECT_AP_READ
  421. b __arm922_setup
  422. .long cpu_arch_name
  423. .long cpu_elf_name
  424. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  425. .long cpu_arm922_name
  426. .long arm922_processor_functions
  427. .long v4wbi_tlb_fns
  428. .long v4wb_user_fns
  429. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  430. .long arm922_cache_fns
  431. #else
  432. .long v4wt_cache_fns
  433. #endif
  434. .size __arm922_proc_info, . - __arm922_proc_info