proc-arm920.S 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477
  1. /*
  2. * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
  3. *
  4. * Copyright (C) 1999,2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. *
  23. * These are the low level assembler for performing cache and TLB
  24. * functions on the arm920.
  25. *
  26. * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
  27. */
  28. #include <linux/linkage.h>
  29. #include <linux/init.h>
  30. #include <asm/assembler.h>
  31. #include <asm/elf.h>
  32. #include <asm/pgtable-hwdef.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/page.h>
  35. #include <asm/ptrace.h>
  36. #include "proc-macros.S"
  37. /*
  38. * The size of one data cache line.
  39. */
  40. #define CACHE_DLINESIZE 32
  41. /*
  42. * The number of data cache segments.
  43. */
  44. #define CACHE_DSEGMENTS 8
  45. /*
  46. * The number of lines in a cache segment.
  47. */
  48. #define CACHE_DENTRIES 64
  49. /*
  50. * This is the size at which it becomes more efficient to
  51. * clean the whole cache, rather than using the individual
  52. * cache line maintainence instructions.
  53. */
  54. #define CACHE_DLIMIT 65536
  55. .text
  56. /*
  57. * cpu_arm920_proc_init()
  58. */
  59. ENTRY(cpu_arm920_proc_init)
  60. mov pc, lr
  61. /*
  62. * cpu_arm920_proc_fin()
  63. */
  64. ENTRY(cpu_arm920_proc_fin)
  65. stmfd sp!, {lr}
  66. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  67. msr cpsr_c, ip
  68. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  69. bl arm920_flush_kern_cache_all
  70. #else
  71. bl v4wt_flush_kern_cache_all
  72. #endif
  73. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  74. bic r0, r0, #0x1000 @ ...i............
  75. bic r0, r0, #0x000e @ ............wca.
  76. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  77. ldmfd sp!, {pc}
  78. /*
  79. * cpu_arm920_reset(loc)
  80. *
  81. * Perform a soft reset of the system. Put the CPU into the
  82. * same state as it would be if it had been reset, and branch
  83. * to what would be the reset vector.
  84. *
  85. * loc: location to jump to for soft reset
  86. */
  87. .align 5
  88. ENTRY(cpu_arm920_reset)
  89. mov ip, #0
  90. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  91. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  92. #ifdef CONFIG_MMU
  93. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  94. #endif
  95. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  96. bic ip, ip, #0x000f @ ............wcam
  97. bic ip, ip, #0x1100 @ ...i...s........
  98. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  99. mov pc, r0
  100. /*
  101. * cpu_arm920_do_idle()
  102. */
  103. .align 5
  104. ENTRY(cpu_arm920_do_idle)
  105. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  106. mov pc, lr
  107. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  108. /*
  109. * flush_user_cache_all()
  110. *
  111. * Invalidate all cache entries in a particular address
  112. * space.
  113. */
  114. ENTRY(arm920_flush_user_cache_all)
  115. /* FALLTHROUGH */
  116. /*
  117. * flush_kern_cache_all()
  118. *
  119. * Clean and invalidate the entire cache.
  120. */
  121. ENTRY(arm920_flush_kern_cache_all)
  122. mov r2, #VM_EXEC
  123. mov ip, #0
  124. __flush_whole_cache:
  125. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  126. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  127. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  128. subs r3, r3, #1 << 26
  129. bcs 2b @ entries 63 to 0
  130. subs r1, r1, #1 << 5
  131. bcs 1b @ segments 7 to 0
  132. tst r2, #VM_EXEC
  133. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  134. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  135. mov pc, lr
  136. /*
  137. * flush_user_cache_range(start, end, flags)
  138. *
  139. * Invalidate a range of cache entries in the specified
  140. * address space.
  141. *
  142. * - start - start address (inclusive)
  143. * - end - end address (exclusive)
  144. * - flags - vm_flags for address space
  145. */
  146. ENTRY(arm920_flush_user_cache_range)
  147. mov ip, #0
  148. sub r3, r1, r0 @ calculate total size
  149. cmp r3, #CACHE_DLIMIT
  150. bhs __flush_whole_cache
  151. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  152. tst r2, #VM_EXEC
  153. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  154. add r0, r0, #CACHE_DLINESIZE
  155. cmp r0, r1
  156. blo 1b
  157. tst r2, #VM_EXEC
  158. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  159. mov pc, lr
  160. /*
  161. * coherent_kern_range(start, end)
  162. *
  163. * Ensure coherency between the Icache and the Dcache in the
  164. * region described by start, end. If you have non-snooping
  165. * Harvard caches, you need to implement this function.
  166. *
  167. * - start - virtual start address
  168. * - end - virtual end address
  169. */
  170. ENTRY(arm920_coherent_kern_range)
  171. /* FALLTHROUGH */
  172. /*
  173. * coherent_user_range(start, end)
  174. *
  175. * Ensure coherency between the Icache and the Dcache in the
  176. * region described by start, end. If you have non-snooping
  177. * Harvard caches, you need to implement this function.
  178. *
  179. * - start - virtual start address
  180. * - end - virtual end address
  181. */
  182. ENTRY(arm920_coherent_user_range)
  183. bic r0, r0, #CACHE_DLINESIZE - 1
  184. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  185. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  186. add r0, r0, #CACHE_DLINESIZE
  187. cmp r0, r1
  188. blo 1b
  189. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  190. mov pc, lr
  191. /*
  192. * flush_kern_dcache_page(void *page)
  193. *
  194. * Ensure no D cache aliasing occurs, either with itself or
  195. * the I cache
  196. *
  197. * - addr - page aligned address
  198. */
  199. ENTRY(arm920_flush_kern_dcache_page)
  200. add r1, r0, #PAGE_SZ
  201. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  202. add r0, r0, #CACHE_DLINESIZE
  203. cmp r0, r1
  204. blo 1b
  205. mov r0, #0
  206. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  207. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  208. mov pc, lr
  209. /*
  210. * dma_inv_range(start, end)
  211. *
  212. * Invalidate (discard) the specified virtual address range.
  213. * May not write back any entries. If 'start' or 'end'
  214. * are not cache line aligned, those lines must be written
  215. * back.
  216. *
  217. * - start - virtual start address
  218. * - end - virtual end address
  219. *
  220. * (same as v4wb)
  221. */
  222. ENTRY(arm920_dma_inv_range)
  223. tst r0, #CACHE_DLINESIZE - 1
  224. bic r0, r0, #CACHE_DLINESIZE - 1
  225. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  226. tst r1, #CACHE_DLINESIZE - 1
  227. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  228. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  229. add r0, r0, #CACHE_DLINESIZE
  230. cmp r0, r1
  231. blo 1b
  232. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  233. mov pc, lr
  234. /*
  235. * dma_clean_range(start, end)
  236. *
  237. * Clean the specified virtual address range.
  238. *
  239. * - start - virtual start address
  240. * - end - virtual end address
  241. *
  242. * (same as v4wb)
  243. */
  244. ENTRY(arm920_dma_clean_range)
  245. bic r0, r0, #CACHE_DLINESIZE - 1
  246. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  247. add r0, r0, #CACHE_DLINESIZE
  248. cmp r0, r1
  249. blo 1b
  250. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  251. mov pc, lr
  252. /*
  253. * dma_flush_range(start, end)
  254. *
  255. * Clean and invalidate the specified virtual address range.
  256. *
  257. * - start - virtual start address
  258. * - end - virtual end address
  259. */
  260. ENTRY(arm920_dma_flush_range)
  261. bic r0, r0, #CACHE_DLINESIZE - 1
  262. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  263. add r0, r0, #CACHE_DLINESIZE
  264. cmp r0, r1
  265. blo 1b
  266. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  267. mov pc, lr
  268. ENTRY(arm920_cache_fns)
  269. .long arm920_flush_kern_cache_all
  270. .long arm920_flush_user_cache_all
  271. .long arm920_flush_user_cache_range
  272. .long arm920_coherent_kern_range
  273. .long arm920_coherent_user_range
  274. .long arm920_flush_kern_dcache_page
  275. .long arm920_dma_inv_range
  276. .long arm920_dma_clean_range
  277. .long arm920_dma_flush_range
  278. #endif
  279. ENTRY(cpu_arm920_dcache_clean_area)
  280. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  281. add r0, r0, #CACHE_DLINESIZE
  282. subs r1, r1, #CACHE_DLINESIZE
  283. bhi 1b
  284. mov pc, lr
  285. /* =============================== PageTable ============================== */
  286. /*
  287. * cpu_arm920_switch_mm(pgd)
  288. *
  289. * Set the translation base pointer to be as described by pgd.
  290. *
  291. * pgd: new page tables
  292. */
  293. .align 5
  294. ENTRY(cpu_arm920_switch_mm)
  295. #ifdef CONFIG_MMU
  296. mov ip, #0
  297. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  298. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  299. #else
  300. @ && 'Clean & Invalidate whole DCache'
  301. @ && Re-written to use Index Ops.
  302. @ && Uses registers r1, r3 and ip
  303. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  304. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  305. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  306. subs r3, r3, #1 << 26
  307. bcs 2b @ entries 63 to 0
  308. subs r1, r1, #1 << 5
  309. bcs 1b @ segments 7 to 0
  310. #endif
  311. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  312. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  313. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  314. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  315. #endif
  316. mov pc, lr
  317. /*
  318. * cpu_arm920_set_pte(ptep, pte, ext)
  319. *
  320. * Set a PTE and flush it out
  321. */
  322. .align 5
  323. ENTRY(cpu_arm920_set_pte_ext)
  324. #ifdef CONFIG_MMU
  325. str r1, [r0], #-2048 @ linux version
  326. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  327. bic r2, r1, #PTE_SMALL_AP_MASK
  328. bic r2, r2, #PTE_TYPE_MASK
  329. orr r2, r2, #PTE_TYPE_SMALL
  330. tst r1, #L_PTE_USER @ User?
  331. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  332. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  333. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  334. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  335. movne r2, #0
  336. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  337. eor r3, r2, #0x0a @ C & small page?
  338. tst r3, #0x0b
  339. biceq r2, r2, #4
  340. #endif
  341. str r2, [r0] @ hardware version
  342. mov r0, r0
  343. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  344. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  345. #endif /* CONFIG_MMU */
  346. mov pc, lr
  347. __INIT
  348. .type __arm920_setup, #function
  349. __arm920_setup:
  350. mov r0, #0
  351. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  352. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  353. #ifdef CONFIG_MMU
  354. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  355. #endif
  356. adr r5, arm920_crval
  357. ldmia r5, {r5, r6}
  358. mrc p15, 0, r0, c1, c0 @ get control register v4
  359. bic r0, r0, r5
  360. orr r0, r0, r6
  361. mov pc, lr
  362. .size __arm920_setup, . - __arm920_setup
  363. /*
  364. * R
  365. * .RVI ZFRS BLDP WCAM
  366. * ..11 0001 ..11 0101
  367. *
  368. */
  369. .type arm920_crval, #object
  370. arm920_crval:
  371. crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  372. __INITDATA
  373. /*
  374. * Purpose : Function pointers used to access above functions - all calls
  375. * come through these
  376. */
  377. .type arm920_processor_functions, #object
  378. arm920_processor_functions:
  379. .word v4t_early_abort
  380. .word cpu_arm920_proc_init
  381. .word cpu_arm920_proc_fin
  382. .word cpu_arm920_reset
  383. .word cpu_arm920_do_idle
  384. .word cpu_arm920_dcache_clean_area
  385. .word cpu_arm920_switch_mm
  386. .word cpu_arm920_set_pte_ext
  387. .size arm920_processor_functions, . - arm920_processor_functions
  388. .section ".rodata"
  389. .type cpu_arch_name, #object
  390. cpu_arch_name:
  391. .asciz "armv4t"
  392. .size cpu_arch_name, . - cpu_arch_name
  393. .type cpu_elf_name, #object
  394. cpu_elf_name:
  395. .asciz "v4"
  396. .size cpu_elf_name, . - cpu_elf_name
  397. .type cpu_arm920_name, #object
  398. cpu_arm920_name:
  399. .asciz "ARM920T"
  400. .size cpu_arm920_name, . - cpu_arm920_name
  401. .align
  402. .section ".proc.info.init", #alloc, #execinstr
  403. .type __arm920_proc_info,#object
  404. __arm920_proc_info:
  405. .long 0x41009200
  406. .long 0xff00fff0
  407. .long PMD_TYPE_SECT | \
  408. PMD_SECT_BUFFERABLE | \
  409. PMD_SECT_CACHEABLE | \
  410. PMD_BIT4 | \
  411. PMD_SECT_AP_WRITE | \
  412. PMD_SECT_AP_READ
  413. .long PMD_TYPE_SECT | \
  414. PMD_BIT4 | \
  415. PMD_SECT_AP_WRITE | \
  416. PMD_SECT_AP_READ
  417. b __arm920_setup
  418. .long cpu_arch_name
  419. .long cpu_elf_name
  420. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  421. .long cpu_arm920_name
  422. .long arm920_processor_functions
  423. .long v4wbi_tlb_fns
  424. .long v4wb_user_fns
  425. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  426. .long arm920_cache_fns
  427. #else
  428. .long v4wt_cache_fns
  429. #endif
  430. .size __arm920_proc_info, . - __arm920_proc_info