proc-arm740.S 4.4 KB

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  1. /*
  2. * linux/arch/arm/mm/arm740.S: utility functions for ARM740
  3. *
  4. * Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/linkage.h>
  12. #include <linux/init.h>
  13. #include <asm/assembler.h>
  14. #include <asm/asm-offsets.h>
  15. #include <asm/elf.h>
  16. #include <asm/pgtable-hwdef.h>
  17. #include <asm/pgtable.h>
  18. #include <asm/ptrace.h>
  19. .text
  20. /*
  21. * cpu_arm740_proc_init()
  22. * cpu_arm740_do_idle()
  23. * cpu_arm740_dcache_clean_area()
  24. * cpu_arm740_switch_mm()
  25. *
  26. * These are not required.
  27. */
  28. ENTRY(cpu_arm740_proc_init)
  29. ENTRY(cpu_arm740_do_idle)
  30. ENTRY(cpu_arm740_dcache_clean_area)
  31. ENTRY(cpu_arm740_switch_mm)
  32. mov pc, lr
  33. /*
  34. * cpu_arm740_proc_fin()
  35. */
  36. ENTRY(cpu_arm740_proc_fin)
  37. stmfd sp!, {lr}
  38. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  39. msr cpsr_c, ip
  40. mrc p15, 0, r0, c1, c0, 0
  41. bic r0, r0, #0x3f000000 @ bank/f/lock/s
  42. bic r0, r0, #0x0000000c @ w-buffer/cache
  43. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  44. mcr p15, 0, r0, c7, c0, 0 @ invalidate cache
  45. ldmfd sp!, {pc}
  46. /*
  47. * cpu_arm740_reset(loc)
  48. * Params : r0 = address to jump to
  49. * Notes : This sets up everything for a reset
  50. */
  51. ENTRY(cpu_arm740_reset)
  52. mov ip, #0
  53. mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
  54. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  55. bic ip, ip, #0x0000000c @ ............wc..
  56. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  57. mov pc, r0
  58. __INIT
  59. .type __arm740_setup, #function
  60. __arm740_setup:
  61. mov r0, #0
  62. mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
  63. mcr p15, 0, r0, c6, c3 @ disable area 3~7
  64. mcr p15, 0, r0, c6, c4
  65. mcr p15, 0, r0, c6, c5
  66. mcr p15, 0, r0, c6, c6
  67. mcr p15, 0, r0, c6, c7
  68. mov r0, #0x0000003F @ base = 0, size = 4GB
  69. mcr p15, 0, r0, c6, c0 @ set area 0, default
  70. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  71. ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
  72. mov r2, #10 @ 11 is the minimum (4KB)
  73. 1: add r2, r2, #1 @ area size *= 2
  74. mov r1, r1, lsr #1
  75. bne 1b @ count not zero r-shift
  76. orr r0, r0, r2, lsl #1 @ the area register value
  77. orr r0, r0, #1 @ set enable bit
  78. mcr p15, 0, r0, c6, c1 @ set area 1, RAM
  79. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  80. ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
  81. mov r2, #10 @ 11 is the minimum (4KB)
  82. 1: add r2, r2, #1 @ area size *= 2
  83. mov r1, r1, lsr #1
  84. bne 1b @ count not zero r-shift
  85. orr r0, r0, r2, lsl #1 @ the area register value
  86. orr r0, r0, #1 @ set enable bit
  87. mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
  88. mov r0, #0x06
  89. mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
  90. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  91. mov r0, #0x00 @ disable whole write buffer
  92. #else
  93. mov r0, #0x02 @ Region 1 write bufferred
  94. #endif
  95. mcr p15, 0, r0, c3, c0
  96. mov r0, #0x10000
  97. sub r0, r0, #1 @ r0 = 0xffff
  98. mcr p15, 0, r0, c5, c0 @ all read/write access
  99. mrc p15, 0, r0, c1, c0 @ get control register
  100. bic r0, r0, #0x3F000000 @ set to standard caching mode
  101. @ need some benchmark
  102. orr r0, r0, #0x0000000d @ MPU/Cache/WB
  103. mov pc, lr
  104. .size __arm740_setup, . - __arm740_setup
  105. __INITDATA
  106. /*
  107. * Purpose : Function pointers used to access above functions - all calls
  108. * come through these
  109. */
  110. .type arm740_processor_functions, #object
  111. ENTRY(arm740_processor_functions)
  112. .word v4t_late_abort
  113. .word cpu_arm740_proc_init
  114. .word cpu_arm740_proc_fin
  115. .word cpu_arm740_reset
  116. .word cpu_arm740_do_idle
  117. .word cpu_arm740_dcache_clean_area
  118. .word cpu_arm740_switch_mm
  119. .word 0 @ cpu_*_set_pte
  120. .size arm740_processor_functions, . - arm740_processor_functions
  121. .section ".rodata"
  122. .type cpu_arch_name, #object
  123. cpu_arch_name:
  124. .asciz "armv4"
  125. .size cpu_arch_name, . - cpu_arch_name
  126. .type cpu_elf_name, #object
  127. cpu_elf_name:
  128. .asciz "v4"
  129. .size cpu_elf_name, . - cpu_elf_name
  130. .type cpu_arm740_name, #object
  131. cpu_arm740_name:
  132. .ascii "ARM740T"
  133. .size cpu_arm740_name, . - cpu_arm740_name
  134. .align
  135. .section ".proc.info.init", #alloc, #execinstr
  136. .type __arm740_proc_info,#object
  137. __arm740_proc_info:
  138. .long 0x41807400
  139. .long 0xfffffff0
  140. .long 0
  141. b __arm740_setup
  142. .long cpu_arch_name
  143. .long cpu_elf_name
  144. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
  145. .long cpu_arm740_name
  146. .long arm740_processor_functions
  147. .long 0
  148. .long 0
  149. .long v3_cache_fns @ cache model
  150. .size __arm740_proc_info, . - __arm740_proc_info