proc-arm6_7.S 11 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-arm6,7.S
  3. *
  4. * Copyright (C) 1997-2000 Russell King
  5. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * These are the low level assembler for performing cache and TLB
  12. * functions on the ARM610 & ARM710.
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/init.h>
  16. #include <asm/assembler.h>
  17. #include <asm/asm-offsets.h>
  18. #include <asm/elf.h>
  19. #include <asm/pgtable-hwdef.h>
  20. #include <asm/pgtable.h>
  21. #include <asm/ptrace.h>
  22. ENTRY(cpu_arm6_dcache_clean_area)
  23. ENTRY(cpu_arm7_dcache_clean_area)
  24. mov pc, lr
  25. /*
  26. * Function: arm6_7_data_abort ()
  27. *
  28. * Params : r2 = address of aborted instruction
  29. * : sp = pointer to registers
  30. *
  31. * Purpose : obtain information about current aborted instruction
  32. *
  33. * Returns : r0 = address of abort
  34. * : r1 = FSR
  35. */
  36. ENTRY(cpu_arm7_data_abort)
  37. mrc p15, 0, r1, c5, c0, 0 @ get FSR
  38. mrc p15, 0, r0, c6, c0, 0 @ get FAR
  39. ldr r8, [r0] @ read arm instruction
  40. tst r8, #1 << 20 @ L = 0 -> write?
  41. orreq r1, r1, #1 << 11 @ yes.
  42. and r7, r8, #15 << 24
  43. add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
  44. nop
  45. /* 0 */ b .data_unknown
  46. /* 1 */ mov pc, lr @ swp
  47. /* 2 */ b .data_unknown
  48. /* 3 */ b .data_unknown
  49. /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
  50. /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
  51. /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
  52. /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
  53. /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
  54. /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
  55. /* a */ b .data_unknown
  56. /* b */ b .data_unknown
  57. /* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
  58. /* d */ mov pc, lr @ ldc rd, [rn, #m]
  59. /* e */ b .data_unknown
  60. /* f */
  61. .data_unknown: @ Part of jumptable
  62. mov r0, r2
  63. mov r1, r8
  64. mov r2, sp
  65. bl baddataabort
  66. b ret_from_exception
  67. ENTRY(cpu_arm6_data_abort)
  68. mrc p15, 0, r1, c5, c0, 0 @ get FSR
  69. mrc p15, 0, r0, c6, c0, 0 @ get FAR
  70. ldr r8, [r2] @ read arm instruction
  71. tst r8, #1 << 20 @ L = 0 -> write?
  72. orreq r1, r1, #1 << 11 @ yes.
  73. and r7, r8, #14 << 24
  74. teq r7, #8 << 24 @ was it ldm/stm
  75. movne pc, lr
  76. .data_arm_ldmstm:
  77. tst r8, #1 << 21 @ check writeback bit
  78. moveq pc, lr @ no writeback -> no fixup
  79. mov r7, #0x11
  80. orr r7, r7, #0x1100
  81. and r6, r8, r7
  82. and r2, r8, r7, lsl #1
  83. add r6, r6, r2, lsr #1
  84. and r2, r8, r7, lsl #2
  85. add r6, r6, r2, lsr #2
  86. and r2, r8, r7, lsl #3
  87. add r6, r6, r2, lsr #3
  88. add r6, r6, r6, lsr #8
  89. add r6, r6, r6, lsr #4
  90. and r6, r6, #15 @ r6 = no. of registers to transfer.
  91. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  92. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  93. tst r8, #1 << 23 @ Check U bit
  94. subne r7, r7, r6, lsl #2 @ Undo increment
  95. addeq r7, r7, r6, lsl #2 @ Undo decrement
  96. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  97. mov pc, lr
  98. .data_arm_apply_r6_and_rn:
  99. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  100. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  101. tst r8, #1 << 23 @ Check U bit
  102. subne r7, r7, r6 @ Undo incrmenet
  103. addeq r7, r7, r6 @ Undo decrement
  104. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  105. mov pc, lr
  106. .data_arm_lateldrpreconst:
  107. tst r8, #1 << 21 @ check writeback bit
  108. moveq pc, lr @ no writeback -> no fixup
  109. .data_arm_lateldrpostconst:
  110. movs r2, r8, lsl #20 @ Get offset
  111. moveq pc, lr @ zero -> no fixup
  112. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  113. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  114. tst r8, #1 << 23 @ Check U bit
  115. subne r7, r7, r2, lsr #20 @ Undo increment
  116. addeq r7, r7, r2, lsr #20 @ Undo decrement
  117. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  118. mov pc, lr
  119. .data_arm_lateldrprereg:
  120. tst r8, #1 << 21 @ check writeback bit
  121. moveq pc, lr @ no writeback -> no fixup
  122. .data_arm_lateldrpostreg:
  123. and r7, r8, #15 @ Extract 'm' from instruction
  124. ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
  125. mov r5, r8, lsr #7 @ get shift count
  126. ands r5, r5, #31
  127. and r7, r8, #0x70 @ get shift type
  128. orreq r7, r7, #8 @ shift count = 0
  129. add pc, pc, r7
  130. nop
  131. mov r6, r6, lsl r5 @ 0: LSL #!0
  132. b .data_arm_apply_r6_and_rn
  133. b .data_arm_apply_r6_and_rn @ 1: LSL #0
  134. nop
  135. b .data_unknown @ 2: MUL?
  136. nop
  137. b .data_unknown @ 3: MUL?
  138. nop
  139. mov r6, r6, lsr r5 @ 4: LSR #!0
  140. b .data_arm_apply_r6_and_rn
  141. mov r6, r6, lsr #32 @ 5: LSR #32
  142. b .data_arm_apply_r6_and_rn
  143. b .data_unknown @ 6: MUL?
  144. nop
  145. b .data_unknown @ 7: MUL?
  146. nop
  147. mov r6, r6, asr r5 @ 8: ASR #!0
  148. b .data_arm_apply_r6_and_rn
  149. mov r6, r6, asr #32 @ 9: ASR #32
  150. b .data_arm_apply_r6_and_rn
  151. b .data_unknown @ A: MUL?
  152. nop
  153. b .data_unknown @ B: MUL?
  154. nop
  155. mov r6, r6, ror r5 @ C: ROR #!0
  156. b .data_arm_apply_r6_and_rn
  157. mov r6, r6, rrx @ D: RRX
  158. b .data_arm_apply_r6_and_rn
  159. b .data_unknown @ E: MUL?
  160. nop
  161. b .data_unknown @ F: MUL?
  162. /*
  163. * Function: arm6_7_proc_init (void)
  164. * : arm6_7_proc_fin (void)
  165. *
  166. * Notes : This processor does not require these
  167. */
  168. ENTRY(cpu_arm6_proc_init)
  169. ENTRY(cpu_arm7_proc_init)
  170. mov pc, lr
  171. ENTRY(cpu_arm6_proc_fin)
  172. ENTRY(cpu_arm7_proc_fin)
  173. mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  174. msr cpsr_c, r0
  175. mov r0, #0x31 @ ....S..DP...M
  176. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  177. mov pc, lr
  178. ENTRY(cpu_arm6_do_idle)
  179. ENTRY(cpu_arm7_do_idle)
  180. mov pc, lr
  181. /*
  182. * Function: arm6_7_switch_mm(unsigned long pgd_phys)
  183. * Params : pgd_phys Physical address of page table
  184. * Purpose : Perform a task switch, saving the old processes state, and restoring
  185. * the new.
  186. */
  187. ENTRY(cpu_arm6_switch_mm)
  188. ENTRY(cpu_arm7_switch_mm)
  189. #ifdef CONFIG_MMU
  190. mov r1, #0
  191. mcr p15, 0, r1, c7, c0, 0 @ flush cache
  192. mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
  193. mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
  194. #endif
  195. mov pc, lr
  196. /*
  197. * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
  198. * Params : r0 = Address to set
  199. * : r1 = value to set
  200. * Purpose : Set a PTE and flush it out of any WB cache
  201. */
  202. .align 5
  203. ENTRY(cpu_arm6_set_pte_ext)
  204. ENTRY(cpu_arm7_set_pte_ext)
  205. #ifdef CONFIG_MMU
  206. str r1, [r0], #-2048 @ linux version
  207. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  208. bic r2, r1, #PTE_SMALL_AP_MASK
  209. bic r2, r2, #PTE_TYPE_MASK
  210. orr r2, r2, #PTE_TYPE_SMALL
  211. tst r1, #L_PTE_USER @ User?
  212. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  213. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  214. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  215. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
  216. movne r2, #0
  217. str r2, [r0] @ hardware version
  218. #endif /* CONFIG_MMU */
  219. mov pc, lr
  220. /*
  221. * Function: _arm6_7_reset
  222. * Params : r0 = address to jump to
  223. * Notes : This sets up everything for a reset
  224. */
  225. ENTRY(cpu_arm6_reset)
  226. ENTRY(cpu_arm7_reset)
  227. mov r1, #0
  228. mcr p15, 0, r1, c7, c0, 0 @ flush cache
  229. #ifdef CONFIG_MMU
  230. mcr p15, 0, r1, c5, c0, 0 @ flush TLB
  231. #endif
  232. mov r1, #0x30
  233. mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
  234. mov pc, r0
  235. __INIT
  236. .type __arm6_setup, #function
  237. __arm6_setup: mov r0, #0
  238. mcr p15, 0, r0, c7, c0 @ flush caches on v3
  239. #ifdef CONFIG_MMU
  240. mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
  241. mov r0, #0x3d @ . ..RS BLDP WCAM
  242. orr r0, r0, #0x100 @ . ..01 0011 1101
  243. #else
  244. mov r0, #0x3c @ . ..RS BLDP WCA.
  245. #endif
  246. mov pc, lr
  247. .size __arm6_setup, . - __arm6_setup
  248. .type __arm7_setup, #function
  249. __arm7_setup: mov r0, #0
  250. mcr p15, 0, r0, c7, c0 @ flush caches on v3
  251. #ifdef CONFIG_MMU
  252. mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
  253. mcr p15, 0, r0, c3, c0 @ load domain access register
  254. mov r0, #0x7d @ . ..RS BLDP WCAM
  255. orr r0, r0, #0x100 @ . ..01 0111 1101
  256. #else
  257. mov r0, #0x7c @ . ..RS BLDP WCA.
  258. #endif
  259. mov pc, lr
  260. .size __arm7_setup, . - __arm7_setup
  261. __INITDATA
  262. /*
  263. * Purpose : Function pointers used to access above functions - all calls
  264. * come through these
  265. */
  266. .type arm6_processor_functions, #object
  267. ENTRY(arm6_processor_functions)
  268. .word cpu_arm6_data_abort
  269. .word cpu_arm6_proc_init
  270. .word cpu_arm6_proc_fin
  271. .word cpu_arm6_reset
  272. .word cpu_arm6_do_idle
  273. .word cpu_arm6_dcache_clean_area
  274. .word cpu_arm6_switch_mm
  275. .word cpu_arm6_set_pte_ext
  276. .size arm6_processor_functions, . - arm6_processor_functions
  277. /*
  278. * Purpose : Function pointers used to access above functions - all calls
  279. * come through these
  280. */
  281. .type arm7_processor_functions, #object
  282. ENTRY(arm7_processor_functions)
  283. .word cpu_arm7_data_abort
  284. .word cpu_arm7_proc_init
  285. .word cpu_arm7_proc_fin
  286. .word cpu_arm7_reset
  287. .word cpu_arm7_do_idle
  288. .word cpu_arm7_dcache_clean_area
  289. .word cpu_arm7_switch_mm
  290. .word cpu_arm7_set_pte_ext
  291. .size arm7_processor_functions, . - arm7_processor_functions
  292. .section ".rodata"
  293. .type cpu_arch_name, #object
  294. cpu_arch_name: .asciz "armv3"
  295. .size cpu_arch_name, . - cpu_arch_name
  296. .type cpu_elf_name, #object
  297. cpu_elf_name: .asciz "v3"
  298. .size cpu_elf_name, . - cpu_elf_name
  299. .type cpu_arm6_name, #object
  300. cpu_arm6_name: .asciz "ARM6"
  301. .size cpu_arm6_name, . - cpu_arm6_name
  302. .type cpu_arm610_name, #object
  303. cpu_arm610_name:
  304. .asciz "ARM610"
  305. .size cpu_arm610_name, . - cpu_arm610_name
  306. .type cpu_arm7_name, #object
  307. cpu_arm7_name: .asciz "ARM7"
  308. .size cpu_arm7_name, . - cpu_arm7_name
  309. .type cpu_arm710_name, #object
  310. cpu_arm710_name:
  311. .asciz "ARM710"
  312. .size cpu_arm710_name, . - cpu_arm710_name
  313. .align
  314. .section ".proc.info.init", #alloc, #execinstr
  315. .type __arm6_proc_info, #object
  316. __arm6_proc_info:
  317. .long 0x41560600
  318. .long 0xfffffff0
  319. .long 0x00000c1e
  320. .long PMD_TYPE_SECT | \
  321. PMD_BIT4 | \
  322. PMD_SECT_AP_WRITE | \
  323. PMD_SECT_AP_READ
  324. b __arm6_setup
  325. .long cpu_arch_name
  326. .long cpu_elf_name
  327. .long HWCAP_SWP | HWCAP_26BIT
  328. .long cpu_arm6_name
  329. .long arm6_processor_functions
  330. .long v3_tlb_fns
  331. .long v3_user_fns
  332. .long v3_cache_fns
  333. .size __arm6_proc_info, . - __arm6_proc_info
  334. .type __arm610_proc_info, #object
  335. __arm610_proc_info:
  336. .long 0x41560610
  337. .long 0xfffffff0
  338. .long 0x00000c1e
  339. .long PMD_TYPE_SECT | \
  340. PMD_BIT4 | \
  341. PMD_SECT_AP_WRITE | \
  342. PMD_SECT_AP_READ
  343. b __arm6_setup
  344. .long cpu_arch_name
  345. .long cpu_elf_name
  346. .long HWCAP_SWP | HWCAP_26BIT
  347. .long cpu_arm610_name
  348. .long arm6_processor_functions
  349. .long v3_tlb_fns
  350. .long v3_user_fns
  351. .long v3_cache_fns
  352. .size __arm610_proc_info, . - __arm610_proc_info
  353. .type __arm7_proc_info, #object
  354. __arm7_proc_info:
  355. .long 0x41007000
  356. .long 0xffffff00
  357. .long 0x00000c1e
  358. .long PMD_TYPE_SECT | \
  359. PMD_BIT4 | \
  360. PMD_SECT_AP_WRITE | \
  361. PMD_SECT_AP_READ
  362. b __arm7_setup
  363. .long cpu_arch_name
  364. .long cpu_elf_name
  365. .long HWCAP_SWP | HWCAP_26BIT
  366. .long cpu_arm7_name
  367. .long arm7_processor_functions
  368. .long v3_tlb_fns
  369. .long v3_user_fns
  370. .long v3_cache_fns
  371. .size __arm7_proc_info, . - __arm7_proc_info
  372. .type __arm710_proc_info, #object
  373. __arm710_proc_info:
  374. .long 0x41007100
  375. .long 0xfff8ff00
  376. .long PMD_TYPE_SECT | \
  377. PMD_SECT_BUFFERABLE | \
  378. PMD_SECT_CACHEABLE | \
  379. PMD_BIT4 | \
  380. PMD_SECT_AP_WRITE | \
  381. PMD_SECT_AP_READ
  382. .long PMD_TYPE_SECT | \
  383. PMD_BIT4 | \
  384. PMD_SECT_AP_WRITE | \
  385. PMD_SECT_AP_READ
  386. b __arm7_setup
  387. .long cpu_arch_name
  388. .long cpu_elf_name
  389. .long HWCAP_SWP | HWCAP_26BIT
  390. .long cpu_arm710_name
  391. .long arm7_processor_functions
  392. .long v3_tlb_fns
  393. .long v3_user_fns
  394. .long v3_cache_fns
  395. .size __arm710_proc_info, . - __arm710_proc_info