proc-arm1026.S 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485
  1. /*
  2. * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
  3. *
  4. * Copyright (C) 2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. *
  14. * These are the low level assembler for performing cache and TLB
  15. * functions on the ARM1026EJ-S.
  16. */
  17. #include <linux/linkage.h>
  18. #include <linux/init.h>
  19. #include <asm/assembler.h>
  20. #include <asm/asm-offsets.h>
  21. #include <asm/elf.h>
  22. #include <asm/pgtable-hwdef.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/ptrace.h>
  25. #include "proc-macros.S"
  26. /*
  27. * This is the maximum size of an area which will be invalidated
  28. * using the single invalidate entry instructions. Anything larger
  29. * than this, and we go for the whole cache.
  30. *
  31. * This value should be chosen such that we choose the cheapest
  32. * alternative.
  33. */
  34. #define MAX_AREA_SIZE 32768
  35. /*
  36. * The size of one data cache line.
  37. */
  38. #define CACHE_DLINESIZE 32
  39. /*
  40. * The number of data cache segments.
  41. */
  42. #define CACHE_DSEGMENTS 16
  43. /*
  44. * The number of lines in a cache segment.
  45. */
  46. #define CACHE_DENTRIES 64
  47. /*
  48. * This is the size at which it becomes more efficient to
  49. * clean the whole cache, rather than using the individual
  50. * cache line maintainence instructions.
  51. */
  52. #define CACHE_DLIMIT 32768
  53. .text
  54. /*
  55. * cpu_arm1026_proc_init()
  56. */
  57. ENTRY(cpu_arm1026_proc_init)
  58. mov pc, lr
  59. /*
  60. * cpu_arm1026_proc_fin()
  61. */
  62. ENTRY(cpu_arm1026_proc_fin)
  63. stmfd sp!, {lr}
  64. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  65. msr cpsr_c, ip
  66. bl arm1026_flush_kern_cache_all
  67. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  68. bic r0, r0, #0x1000 @ ...i............
  69. bic r0, r0, #0x000e @ ............wca.
  70. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  71. ldmfd sp!, {pc}
  72. /*
  73. * cpu_arm1026_reset(loc)
  74. *
  75. * Perform a soft reset of the system. Put the CPU into the
  76. * same state as it would be if it had been reset, and branch
  77. * to what would be the reset vector.
  78. *
  79. * loc: location to jump to for soft reset
  80. */
  81. .align 5
  82. ENTRY(cpu_arm1026_reset)
  83. mov ip, #0
  84. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  85. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  86. #ifdef CONFIG_MMU
  87. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  88. #endif
  89. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  90. bic ip, ip, #0x000f @ ............wcam
  91. bic ip, ip, #0x1100 @ ...i...s........
  92. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  93. mov pc, r0
  94. /*
  95. * cpu_arm1026_do_idle()
  96. */
  97. .align 5
  98. ENTRY(cpu_arm1026_do_idle)
  99. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  100. mov pc, lr
  101. /* ================================= CACHE ================================ */
  102. .align 5
  103. /*
  104. * flush_user_cache_all()
  105. *
  106. * Invalidate all cache entries in a particular address
  107. * space.
  108. */
  109. ENTRY(arm1026_flush_user_cache_all)
  110. /* FALLTHROUGH */
  111. /*
  112. * flush_kern_cache_all()
  113. *
  114. * Clean and invalidate the entire cache.
  115. */
  116. ENTRY(arm1026_flush_kern_cache_all)
  117. mov r2, #VM_EXEC
  118. mov ip, #0
  119. __flush_whole_cache:
  120. #ifndef CONFIG_CPU_DCACHE_DISABLE
  121. 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
  122. bne 1b
  123. #endif
  124. tst r2, #VM_EXEC
  125. #ifndef CONFIG_CPU_ICACHE_DISABLE
  126. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  127. #endif
  128. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  129. mov pc, lr
  130. /*
  131. * flush_user_cache_range(start, end, flags)
  132. *
  133. * Invalidate a range of cache entries in the specified
  134. * address space.
  135. *
  136. * - start - start address (inclusive)
  137. * - end - end address (exclusive)
  138. * - flags - vm_flags for this space
  139. */
  140. ENTRY(arm1026_flush_user_cache_range)
  141. mov ip, #0
  142. sub r3, r1, r0 @ calculate total size
  143. cmp r3, #CACHE_DLIMIT
  144. bhs __flush_whole_cache
  145. #ifndef CONFIG_CPU_DCACHE_DISABLE
  146. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  147. add r0, r0, #CACHE_DLINESIZE
  148. cmp r0, r1
  149. blo 1b
  150. #endif
  151. tst r2, #VM_EXEC
  152. #ifndef CONFIG_CPU_ICACHE_DISABLE
  153. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  154. #endif
  155. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  156. mov pc, lr
  157. /*
  158. * coherent_kern_range(start, end)
  159. *
  160. * Ensure coherency between the Icache and the Dcache in the
  161. * region described by start. If you have non-snooping
  162. * Harvard caches, you need to implement this function.
  163. *
  164. * - start - virtual start address
  165. * - end - virtual end address
  166. */
  167. ENTRY(arm1026_coherent_kern_range)
  168. /* FALLTHROUGH */
  169. /*
  170. * coherent_user_range(start, end)
  171. *
  172. * Ensure coherency between the Icache and the Dcache in the
  173. * region described by start. If you have non-snooping
  174. * Harvard caches, you need to implement this function.
  175. *
  176. * - start - virtual start address
  177. * - end - virtual end address
  178. */
  179. ENTRY(arm1026_coherent_user_range)
  180. mov ip, #0
  181. bic r0, r0, #CACHE_DLINESIZE - 1
  182. 1:
  183. #ifndef CONFIG_CPU_DCACHE_DISABLE
  184. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  185. #endif
  186. #ifndef CONFIG_CPU_ICACHE_DISABLE
  187. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  188. #endif
  189. add r0, r0, #CACHE_DLINESIZE
  190. cmp r0, r1
  191. blo 1b
  192. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  193. mov pc, lr
  194. /*
  195. * flush_kern_dcache_page(void *page)
  196. *
  197. * Ensure no D cache aliasing occurs, either with itself or
  198. * the I cache
  199. *
  200. * - page - page aligned address
  201. */
  202. ENTRY(arm1026_flush_kern_dcache_page)
  203. mov ip, #0
  204. #ifndef CONFIG_CPU_DCACHE_DISABLE
  205. add r1, r0, #PAGE_SZ
  206. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  207. add r0, r0, #CACHE_DLINESIZE
  208. cmp r0, r1
  209. blo 1b
  210. #endif
  211. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  212. mov pc, lr
  213. /*
  214. * dma_inv_range(start, end)
  215. *
  216. * Invalidate (discard) the specified virtual address range.
  217. * May not write back any entries. If 'start' or 'end'
  218. * are not cache line aligned, those lines must be written
  219. * back.
  220. *
  221. * - start - virtual start address
  222. * - end - virtual end address
  223. *
  224. * (same as v4wb)
  225. */
  226. ENTRY(arm1026_dma_inv_range)
  227. mov ip, #0
  228. #ifndef CONFIG_CPU_DCACHE_DISABLE
  229. tst r0, #CACHE_DLINESIZE - 1
  230. bic r0, r0, #CACHE_DLINESIZE - 1
  231. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  232. tst r1, #CACHE_DLINESIZE - 1
  233. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  234. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  235. add r0, r0, #CACHE_DLINESIZE
  236. cmp r0, r1
  237. blo 1b
  238. #endif
  239. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  240. mov pc, lr
  241. /*
  242. * dma_clean_range(start, end)
  243. *
  244. * Clean the specified virtual address range.
  245. *
  246. * - start - virtual start address
  247. * - end - virtual end address
  248. *
  249. * (same as v4wb)
  250. */
  251. ENTRY(arm1026_dma_clean_range)
  252. mov ip, #0
  253. #ifndef CONFIG_CPU_DCACHE_DISABLE
  254. bic r0, r0, #CACHE_DLINESIZE - 1
  255. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  256. add r0, r0, #CACHE_DLINESIZE
  257. cmp r0, r1
  258. blo 1b
  259. #endif
  260. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  261. mov pc, lr
  262. /*
  263. * dma_flush_range(start, end)
  264. *
  265. * Clean and invalidate the specified virtual address range.
  266. *
  267. * - start - virtual start address
  268. * - end - virtual end address
  269. */
  270. ENTRY(arm1026_dma_flush_range)
  271. mov ip, #0
  272. #ifndef CONFIG_CPU_DCACHE_DISABLE
  273. bic r0, r0, #CACHE_DLINESIZE - 1
  274. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  275. add r0, r0, #CACHE_DLINESIZE
  276. cmp r0, r1
  277. blo 1b
  278. #endif
  279. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  280. mov pc, lr
  281. ENTRY(arm1026_cache_fns)
  282. .long arm1026_flush_kern_cache_all
  283. .long arm1026_flush_user_cache_all
  284. .long arm1026_flush_user_cache_range
  285. .long arm1026_coherent_kern_range
  286. .long arm1026_coherent_user_range
  287. .long arm1026_flush_kern_dcache_page
  288. .long arm1026_dma_inv_range
  289. .long arm1026_dma_clean_range
  290. .long arm1026_dma_flush_range
  291. .align 5
  292. ENTRY(cpu_arm1026_dcache_clean_area)
  293. #ifndef CONFIG_CPU_DCACHE_DISABLE
  294. mov ip, #0
  295. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  296. add r0, r0, #CACHE_DLINESIZE
  297. subs r1, r1, #CACHE_DLINESIZE
  298. bhi 1b
  299. #endif
  300. mov pc, lr
  301. /* =============================== PageTable ============================== */
  302. /*
  303. * cpu_arm1026_switch_mm(pgd)
  304. *
  305. * Set the translation base pointer to be as described by pgd.
  306. *
  307. * pgd: new page tables
  308. */
  309. .align 5
  310. ENTRY(cpu_arm1026_switch_mm)
  311. #ifdef CONFIG_MMU
  312. mov r1, #0
  313. #ifndef CONFIG_CPU_DCACHE_DISABLE
  314. 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
  315. bne 1b
  316. #endif
  317. #ifndef CONFIG_CPU_ICACHE_DISABLE
  318. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  319. #endif
  320. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  321. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  322. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  323. #endif
  324. mov pc, lr
  325. /*
  326. * cpu_arm1026_set_pte_ext(ptep, pte, ext)
  327. *
  328. * Set a PTE and flush it out
  329. */
  330. .align 5
  331. ENTRY(cpu_arm1026_set_pte_ext)
  332. #ifdef CONFIG_MMU
  333. str r1, [r0], #-2048 @ linux version
  334. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  335. bic r2, r1, #PTE_SMALL_AP_MASK
  336. bic r2, r2, #PTE_TYPE_MASK
  337. orr r2, r2, #PTE_TYPE_SMALL
  338. tst r1, #L_PTE_USER @ User?
  339. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  340. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  341. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  342. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  343. movne r2, #0
  344. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  345. eor r3, r1, #0x0a @ C & small page?
  346. tst r3, #0x0b
  347. biceq r2, r2, #4
  348. #endif
  349. str r2, [r0] @ hardware version
  350. mov r0, r0
  351. #ifndef CONFIG_CPU_DCACHE_DISABLE
  352. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  353. #endif
  354. #endif /* CONFIG_MMU */
  355. mov pc, lr
  356. __INIT
  357. .type __arm1026_setup, #function
  358. __arm1026_setup:
  359. mov r0, #0
  360. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  361. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  362. #ifdef CONFIG_MMU
  363. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  364. mcr p15, 0, r4, c2, c0 @ load page table pointer
  365. #endif
  366. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  367. mov r0, #4 @ explicitly disable writeback
  368. mcr p15, 7, r0, c15, c0, 0
  369. #endif
  370. adr r5, arm1026_crval
  371. ldmia r5, {r5, r6}
  372. mrc p15, 0, r0, c1, c0 @ get control register v4
  373. bic r0, r0, r5
  374. orr r0, r0, r6
  375. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  376. orr r0, r0, #0x4000 @ .R.. .... .... ....
  377. #endif
  378. mov pc, lr
  379. .size __arm1026_setup, . - __arm1026_setup
  380. /*
  381. * R
  382. * .RVI ZFRS BLDP WCAM
  383. * .011 1001 ..11 0101
  384. *
  385. */
  386. .type arm1026_crval, #object
  387. arm1026_crval:
  388. crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
  389. __INITDATA
  390. /*
  391. * Purpose : Function pointers used to access above functions - all calls
  392. * come through these
  393. */
  394. .type arm1026_processor_functions, #object
  395. arm1026_processor_functions:
  396. .word v5t_early_abort
  397. .word cpu_arm1026_proc_init
  398. .word cpu_arm1026_proc_fin
  399. .word cpu_arm1026_reset
  400. .word cpu_arm1026_do_idle
  401. .word cpu_arm1026_dcache_clean_area
  402. .word cpu_arm1026_switch_mm
  403. .word cpu_arm1026_set_pte_ext
  404. .size arm1026_processor_functions, . - arm1026_processor_functions
  405. .section .rodata
  406. .type cpu_arch_name, #object
  407. cpu_arch_name:
  408. .asciz "armv5tej"
  409. .size cpu_arch_name, . - cpu_arch_name
  410. .type cpu_elf_name, #object
  411. cpu_elf_name:
  412. .asciz "v5"
  413. .size cpu_elf_name, . - cpu_elf_name
  414. .align
  415. .type cpu_arm1026_name, #object
  416. cpu_arm1026_name:
  417. .asciz "ARM1026EJ-S"
  418. .size cpu_arm1026_name, . - cpu_arm1026_name
  419. .align
  420. .section ".proc.info.init", #alloc, #execinstr
  421. .type __arm1026_proc_info,#object
  422. __arm1026_proc_info:
  423. .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
  424. .long 0xff0ffff0
  425. .long PMD_TYPE_SECT | \
  426. PMD_BIT4 | \
  427. PMD_SECT_AP_WRITE | \
  428. PMD_SECT_AP_READ
  429. .long PMD_TYPE_SECT | \
  430. PMD_BIT4 | \
  431. PMD_SECT_AP_WRITE | \
  432. PMD_SECT_AP_READ
  433. b __arm1026_setup
  434. .long cpu_arch_name
  435. .long cpu_elf_name
  436. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
  437. .long cpu_arm1026_name
  438. .long arm1026_processor_functions
  439. .long v4wbi_tlb_fns
  440. .long v4wb_user_fns
  441. .long arm1026_cache_fns
  442. .size __arm1026_proc_info, . - __arm1026_proc_info