proc-arm1020e.S 12 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
  3. *
  4. * Copyright (C) 2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. *
  23. * These are the low level assembler for performing cache and TLB
  24. * functions on the arm1020e.
  25. *
  26. * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
  27. */
  28. #include <linux/linkage.h>
  29. #include <linux/init.h>
  30. #include <asm/assembler.h>
  31. #include <asm/asm-offsets.h>
  32. #include <asm/elf.h>
  33. #include <asm/pgtable-hwdef.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/ptrace.h>
  36. #include "proc-macros.S"
  37. /*
  38. * This is the maximum size of an area which will be invalidated
  39. * using the single invalidate entry instructions. Anything larger
  40. * than this, and we go for the whole cache.
  41. *
  42. * This value should be chosen such that we choose the cheapest
  43. * alternative.
  44. */
  45. #define MAX_AREA_SIZE 32768
  46. /*
  47. * The size of one data cache line.
  48. */
  49. #define CACHE_DLINESIZE 32
  50. /*
  51. * The number of data cache segments.
  52. */
  53. #define CACHE_DSEGMENTS 16
  54. /*
  55. * The number of lines in a cache segment.
  56. */
  57. #define CACHE_DENTRIES 64
  58. /*
  59. * This is the size at which it becomes more efficient to
  60. * clean the whole cache, rather than using the individual
  61. * cache line maintainence instructions.
  62. */
  63. #define CACHE_DLIMIT 32768
  64. .text
  65. /*
  66. * cpu_arm1020e_proc_init()
  67. */
  68. ENTRY(cpu_arm1020e_proc_init)
  69. mov pc, lr
  70. /*
  71. * cpu_arm1020e_proc_fin()
  72. */
  73. ENTRY(cpu_arm1020e_proc_fin)
  74. stmfd sp!, {lr}
  75. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  76. msr cpsr_c, ip
  77. bl arm1020e_flush_kern_cache_all
  78. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  79. bic r0, r0, #0x1000 @ ...i............
  80. bic r0, r0, #0x000e @ ............wca.
  81. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  82. ldmfd sp!, {pc}
  83. /*
  84. * cpu_arm1020e_reset(loc)
  85. *
  86. * Perform a soft reset of the system. Put the CPU into the
  87. * same state as it would be if it had been reset, and branch
  88. * to what would be the reset vector.
  89. *
  90. * loc: location to jump to for soft reset
  91. */
  92. .align 5
  93. ENTRY(cpu_arm1020e_reset)
  94. mov ip, #0
  95. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  96. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  97. #ifdef CONFIG_MMU
  98. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  99. #endif
  100. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  101. bic ip, ip, #0x000f @ ............wcam
  102. bic ip, ip, #0x1100 @ ...i...s........
  103. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  104. mov pc, r0
  105. /*
  106. * cpu_arm1020e_do_idle()
  107. */
  108. .align 5
  109. ENTRY(cpu_arm1020e_do_idle)
  110. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  111. mov pc, lr
  112. /* ================================= CACHE ================================ */
  113. .align 5
  114. /*
  115. * flush_user_cache_all()
  116. *
  117. * Invalidate all cache entries in a particular address
  118. * space.
  119. */
  120. ENTRY(arm1020e_flush_user_cache_all)
  121. /* FALLTHROUGH */
  122. /*
  123. * flush_kern_cache_all()
  124. *
  125. * Clean and invalidate the entire cache.
  126. */
  127. ENTRY(arm1020e_flush_kern_cache_all)
  128. mov r2, #VM_EXEC
  129. mov ip, #0
  130. __flush_whole_cache:
  131. #ifndef CONFIG_CPU_DCACHE_DISABLE
  132. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  133. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
  134. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  135. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  136. subs r3, r3, #1 << 26
  137. bcs 2b @ entries 63 to 0
  138. subs r1, r1, #1 << 5
  139. bcs 1b @ segments 15 to 0
  140. #endif
  141. tst r2, #VM_EXEC
  142. #ifndef CONFIG_CPU_ICACHE_DISABLE
  143. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  144. #endif
  145. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  146. mov pc, lr
  147. /*
  148. * flush_user_cache_range(start, end, flags)
  149. *
  150. * Invalidate a range of cache entries in the specified
  151. * address space.
  152. *
  153. * - start - start address (inclusive)
  154. * - end - end address (exclusive)
  155. * - flags - vm_flags for this space
  156. */
  157. ENTRY(arm1020e_flush_user_cache_range)
  158. mov ip, #0
  159. sub r3, r1, r0 @ calculate total size
  160. cmp r3, #CACHE_DLIMIT
  161. bhs __flush_whole_cache
  162. #ifndef CONFIG_CPU_DCACHE_DISABLE
  163. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  164. add r0, r0, #CACHE_DLINESIZE
  165. cmp r0, r1
  166. blo 1b
  167. #endif
  168. tst r2, #VM_EXEC
  169. #ifndef CONFIG_CPU_ICACHE_DISABLE
  170. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  171. #endif
  172. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  173. mov pc, lr
  174. /*
  175. * coherent_kern_range(start, end)
  176. *
  177. * Ensure coherency between the Icache and the Dcache in the
  178. * region described by start. If you have non-snooping
  179. * Harvard caches, you need to implement this function.
  180. *
  181. * - start - virtual start address
  182. * - end - virtual end address
  183. */
  184. ENTRY(arm1020e_coherent_kern_range)
  185. /* FALLTHROUGH */
  186. /*
  187. * coherent_user_range(start, end)
  188. *
  189. * Ensure coherency between the Icache and the Dcache in the
  190. * region described by start. If you have non-snooping
  191. * Harvard caches, you need to implement this function.
  192. *
  193. * - start - virtual start address
  194. * - end - virtual end address
  195. */
  196. ENTRY(arm1020e_coherent_user_range)
  197. mov ip, #0
  198. bic r0, r0, #CACHE_DLINESIZE - 1
  199. 1:
  200. #ifndef CONFIG_CPU_DCACHE_DISABLE
  201. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  202. #endif
  203. #ifndef CONFIG_CPU_ICACHE_DISABLE
  204. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  205. #endif
  206. add r0, r0, #CACHE_DLINESIZE
  207. cmp r0, r1
  208. blo 1b
  209. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  210. mov pc, lr
  211. /*
  212. * flush_kern_dcache_page(void *page)
  213. *
  214. * Ensure no D cache aliasing occurs, either with itself or
  215. * the I cache
  216. *
  217. * - page - page aligned address
  218. */
  219. ENTRY(arm1020e_flush_kern_dcache_page)
  220. mov ip, #0
  221. #ifndef CONFIG_CPU_DCACHE_DISABLE
  222. add r1, r0, #PAGE_SZ
  223. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  224. add r0, r0, #CACHE_DLINESIZE
  225. cmp r0, r1
  226. blo 1b
  227. #endif
  228. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  229. mov pc, lr
  230. /*
  231. * dma_inv_range(start, end)
  232. *
  233. * Invalidate (discard) the specified virtual address range.
  234. * May not write back any entries. If 'start' or 'end'
  235. * are not cache line aligned, those lines must be written
  236. * back.
  237. *
  238. * - start - virtual start address
  239. * - end - virtual end address
  240. *
  241. * (same as v4wb)
  242. */
  243. ENTRY(arm1020e_dma_inv_range)
  244. mov ip, #0
  245. #ifndef CONFIG_CPU_DCACHE_DISABLE
  246. tst r0, #CACHE_DLINESIZE - 1
  247. bic r0, r0, #CACHE_DLINESIZE - 1
  248. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  249. tst r1, #CACHE_DLINESIZE - 1
  250. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  251. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  252. add r0, r0, #CACHE_DLINESIZE
  253. cmp r0, r1
  254. blo 1b
  255. #endif
  256. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  257. mov pc, lr
  258. /*
  259. * dma_clean_range(start, end)
  260. *
  261. * Clean the specified virtual address range.
  262. *
  263. * - start - virtual start address
  264. * - end - virtual end address
  265. *
  266. * (same as v4wb)
  267. */
  268. ENTRY(arm1020e_dma_clean_range)
  269. mov ip, #0
  270. #ifndef CONFIG_CPU_DCACHE_DISABLE
  271. bic r0, r0, #CACHE_DLINESIZE - 1
  272. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  273. add r0, r0, #CACHE_DLINESIZE
  274. cmp r0, r1
  275. blo 1b
  276. #endif
  277. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  278. mov pc, lr
  279. /*
  280. * dma_flush_range(start, end)
  281. *
  282. * Clean and invalidate the specified virtual address range.
  283. *
  284. * - start - virtual start address
  285. * - end - virtual end address
  286. */
  287. ENTRY(arm1020e_dma_flush_range)
  288. mov ip, #0
  289. #ifndef CONFIG_CPU_DCACHE_DISABLE
  290. bic r0, r0, #CACHE_DLINESIZE - 1
  291. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  292. add r0, r0, #CACHE_DLINESIZE
  293. cmp r0, r1
  294. blo 1b
  295. #endif
  296. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  297. mov pc, lr
  298. ENTRY(arm1020e_cache_fns)
  299. .long arm1020e_flush_kern_cache_all
  300. .long arm1020e_flush_user_cache_all
  301. .long arm1020e_flush_user_cache_range
  302. .long arm1020e_coherent_kern_range
  303. .long arm1020e_coherent_user_range
  304. .long arm1020e_flush_kern_dcache_page
  305. .long arm1020e_dma_inv_range
  306. .long arm1020e_dma_clean_range
  307. .long arm1020e_dma_flush_range
  308. .align 5
  309. ENTRY(cpu_arm1020e_dcache_clean_area)
  310. #ifndef CONFIG_CPU_DCACHE_DISABLE
  311. mov ip, #0
  312. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  313. add r0, r0, #CACHE_DLINESIZE
  314. subs r1, r1, #CACHE_DLINESIZE
  315. bhi 1b
  316. #endif
  317. mov pc, lr
  318. /* =============================== PageTable ============================== */
  319. /*
  320. * cpu_arm1020e_switch_mm(pgd)
  321. *
  322. * Set the translation base pointer to be as described by pgd.
  323. *
  324. * pgd: new page tables
  325. */
  326. .align 5
  327. ENTRY(cpu_arm1020e_switch_mm)
  328. #ifdef CONFIG_MMU
  329. #ifndef CONFIG_CPU_DCACHE_DISABLE
  330. mcr p15, 0, r3, c7, c10, 4
  331. mov r1, #0xF @ 16 segments
  332. 1: mov r3, #0x3F @ 64 entries
  333. 2: mov ip, r3, LSL #26 @ shift up entry
  334. orr ip, ip, r1, LSL #5 @ shift in/up index
  335. mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
  336. mov ip, #0
  337. subs r3, r3, #1
  338. cmp r3, #0
  339. bge 2b @ entries 3F to 0
  340. subs r1, r1, #1
  341. cmp r1, #0
  342. bge 1b @ segments 15 to 0
  343. #endif
  344. mov r1, #0
  345. #ifndef CONFIG_CPU_ICACHE_DISABLE
  346. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  347. #endif
  348. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  349. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  350. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  351. #endif
  352. mov pc, lr
  353. /*
  354. * cpu_arm1020e_set_pte(ptep, pte)
  355. *
  356. * Set a PTE and flush it out
  357. */
  358. .align 5
  359. ENTRY(cpu_arm1020e_set_pte_ext)
  360. #ifdef CONFIG_MMU
  361. str r1, [r0], #-2048 @ linux version
  362. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  363. bic r2, r1, #PTE_SMALL_AP_MASK
  364. bic r2, r2, #PTE_TYPE_MASK
  365. orr r2, r2, #PTE_TYPE_SMALL
  366. tst r1, #L_PTE_USER @ User?
  367. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  368. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  369. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  370. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  371. movne r2, #0
  372. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  373. eor r3, r1, #0x0a @ C & small page?
  374. tst r3, #0x0b
  375. biceq r2, r2, #4
  376. #endif
  377. str r2, [r0] @ hardware version
  378. mov r0, r0
  379. #ifndef CONFIG_CPU_DCACHE_DISABLE
  380. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  381. #endif
  382. #endif /* CONFIG_MMU */
  383. mov pc, lr
  384. __INIT
  385. .type __arm1020e_setup, #function
  386. __arm1020e_setup:
  387. mov r0, #0
  388. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  389. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  390. #ifdef CONFIG_MMU
  391. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  392. #endif
  393. adr r5, arm1020e_crval
  394. ldmia r5, {r5, r6}
  395. mrc p15, 0, r0, c1, c0 @ get control register v4
  396. bic r0, r0, r5
  397. orr r0, r0, r6
  398. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  399. orr r0, r0, #0x4000 @ .R.. .... .... ....
  400. #endif
  401. mov pc, lr
  402. .size __arm1020e_setup, . - __arm1020e_setup
  403. /*
  404. * R
  405. * .RVI ZFRS BLDP WCAM
  406. * .011 1001 ..11 0101
  407. */
  408. .type arm1020e_crval, #object
  409. arm1020e_crval:
  410. crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
  411. __INITDATA
  412. /*
  413. * Purpose : Function pointers used to access above functions - all calls
  414. * come through these
  415. */
  416. .type arm1020e_processor_functions, #object
  417. arm1020e_processor_functions:
  418. .word v4t_early_abort
  419. .word cpu_arm1020e_proc_init
  420. .word cpu_arm1020e_proc_fin
  421. .word cpu_arm1020e_reset
  422. .word cpu_arm1020e_do_idle
  423. .word cpu_arm1020e_dcache_clean_area
  424. .word cpu_arm1020e_switch_mm
  425. .word cpu_arm1020e_set_pte_ext
  426. .size arm1020e_processor_functions, . - arm1020e_processor_functions
  427. .section ".rodata"
  428. .type cpu_arch_name, #object
  429. cpu_arch_name:
  430. .asciz "armv5te"
  431. .size cpu_arch_name, . - cpu_arch_name
  432. .type cpu_elf_name, #object
  433. cpu_elf_name:
  434. .asciz "v5"
  435. .size cpu_elf_name, . - cpu_elf_name
  436. .type cpu_arm1020e_name, #object
  437. cpu_arm1020e_name:
  438. .asciz "ARM1020E"
  439. .size cpu_arm1020e_name, . - cpu_arm1020e_name
  440. .align
  441. .section ".proc.info.init", #alloc, #execinstr
  442. .type __arm1020e_proc_info,#object
  443. __arm1020e_proc_info:
  444. .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
  445. .long 0xff0ffff0
  446. .long PMD_TYPE_SECT | \
  447. PMD_BIT4 | \
  448. PMD_SECT_AP_WRITE | \
  449. PMD_SECT_AP_READ
  450. .long PMD_TYPE_SECT | \
  451. PMD_BIT4 | \
  452. PMD_SECT_AP_WRITE | \
  453. PMD_SECT_AP_READ
  454. b __arm1020e_setup
  455. .long cpu_arch_name
  456. .long cpu_elf_name
  457. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
  458. .long cpu_arm1020e_name
  459. .long arm1020e_processor_functions
  460. .long v4wbi_tlb_fns
  461. .long v4wb_user_fns
  462. .long arm1020e_cache_fns
  463. .size __arm1020e_proc_info, . - __arm1020e_proc_info