proc-arm1020.S 13 KB

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  1. /*
  2. * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
  3. *
  4. * Copyright (C) 2000 ARM Limited
  5. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. *
  23. * These are the low level assembler for performing cache and TLB
  24. * functions on the arm1020.
  25. *
  26. * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
  27. */
  28. #include <linux/linkage.h>
  29. #include <linux/init.h>
  30. #include <asm/assembler.h>
  31. #include <asm/asm-offsets.h>
  32. #include <asm/elf.h>
  33. #include <asm/pgtable-hwdef.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/ptrace.h>
  36. #include "proc-macros.S"
  37. /*
  38. * This is the maximum size of an area which will be invalidated
  39. * using the single invalidate entry instructions. Anything larger
  40. * than this, and we go for the whole cache.
  41. *
  42. * This value should be chosen such that we choose the cheapest
  43. * alternative.
  44. */
  45. #define MAX_AREA_SIZE 32768
  46. /*
  47. * The size of one data cache line.
  48. */
  49. #define CACHE_DLINESIZE 32
  50. /*
  51. * The number of data cache segments.
  52. */
  53. #define CACHE_DSEGMENTS 16
  54. /*
  55. * The number of lines in a cache segment.
  56. */
  57. #define CACHE_DENTRIES 64
  58. /*
  59. * This is the size at which it becomes more efficient to
  60. * clean the whole cache, rather than using the individual
  61. * cache line maintainence instructions.
  62. */
  63. #define CACHE_DLIMIT 32768
  64. .text
  65. /*
  66. * cpu_arm1020_proc_init()
  67. */
  68. ENTRY(cpu_arm1020_proc_init)
  69. mov pc, lr
  70. /*
  71. * cpu_arm1020_proc_fin()
  72. */
  73. ENTRY(cpu_arm1020_proc_fin)
  74. stmfd sp!, {lr}
  75. mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  76. msr cpsr_c, ip
  77. bl arm1020_flush_kern_cache_all
  78. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  79. bic r0, r0, #0x1000 @ ...i............
  80. bic r0, r0, #0x000e @ ............wca.
  81. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  82. ldmfd sp!, {pc}
  83. /*
  84. * cpu_arm1020_reset(loc)
  85. *
  86. * Perform a soft reset of the system. Put the CPU into the
  87. * same state as it would be if it had been reset, and branch
  88. * to what would be the reset vector.
  89. *
  90. * loc: location to jump to for soft reset
  91. */
  92. .align 5
  93. ENTRY(cpu_arm1020_reset)
  94. mov ip, #0
  95. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  96. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  97. #ifdef CONFIG_MMU
  98. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  99. #endif
  100. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  101. bic ip, ip, #0x000f @ ............wcam
  102. bic ip, ip, #0x1100 @ ...i...s........
  103. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  104. mov pc, r0
  105. /*
  106. * cpu_arm1020_do_idle()
  107. */
  108. .align 5
  109. ENTRY(cpu_arm1020_do_idle)
  110. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  111. mov pc, lr
  112. /* ================================= CACHE ================================ */
  113. .align 5
  114. /*
  115. * flush_user_cache_all()
  116. *
  117. * Invalidate all cache entries in a particular address
  118. * space.
  119. */
  120. ENTRY(arm1020_flush_user_cache_all)
  121. /* FALLTHROUGH */
  122. /*
  123. * flush_kern_cache_all()
  124. *
  125. * Clean and invalidate the entire cache.
  126. */
  127. ENTRY(arm1020_flush_kern_cache_all)
  128. mov r2, #VM_EXEC
  129. mov ip, #0
  130. __flush_whole_cache:
  131. #ifndef CONFIG_CPU_DCACHE_DISABLE
  132. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  133. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
  134. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  135. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  136. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  137. subs r3, r3, #1 << 26
  138. bcs 2b @ entries 63 to 0
  139. subs r1, r1, #1 << 5
  140. bcs 1b @ segments 15 to 0
  141. #endif
  142. tst r2, #VM_EXEC
  143. #ifndef CONFIG_CPU_ICACHE_DISABLE
  144. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  145. #endif
  146. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  147. mov pc, lr
  148. /*
  149. * flush_user_cache_range(start, end, flags)
  150. *
  151. * Invalidate a range of cache entries in the specified
  152. * address space.
  153. *
  154. * - start - start address (inclusive)
  155. * - end - end address (exclusive)
  156. * - flags - vm_flags for this space
  157. */
  158. ENTRY(arm1020_flush_user_cache_range)
  159. mov ip, #0
  160. sub r3, r1, r0 @ calculate total size
  161. cmp r3, #CACHE_DLIMIT
  162. bhs __flush_whole_cache
  163. #ifndef CONFIG_CPU_DCACHE_DISABLE
  164. mcr p15, 0, ip, c7, c10, 4
  165. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  166. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  167. add r0, r0, #CACHE_DLINESIZE
  168. cmp r0, r1
  169. blo 1b
  170. #endif
  171. tst r2, #VM_EXEC
  172. #ifndef CONFIG_CPU_ICACHE_DISABLE
  173. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  174. #endif
  175. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  176. mov pc, lr
  177. /*
  178. * coherent_kern_range(start, end)
  179. *
  180. * Ensure coherency between the Icache and the Dcache in the
  181. * region described by start. If you have non-snooping
  182. * Harvard caches, you need to implement this function.
  183. *
  184. * - start - virtual start address
  185. * - end - virtual end address
  186. */
  187. ENTRY(arm1020_coherent_kern_range)
  188. /* FALLTRHOUGH */
  189. /*
  190. * coherent_user_range(start, end)
  191. *
  192. * Ensure coherency between the Icache and the Dcache in the
  193. * region described by start. If you have non-snooping
  194. * Harvard caches, you need to implement this function.
  195. *
  196. * - start - virtual start address
  197. * - end - virtual end address
  198. */
  199. ENTRY(arm1020_coherent_user_range)
  200. mov ip, #0
  201. bic r0, r0, #CACHE_DLINESIZE - 1
  202. mcr p15, 0, ip, c7, c10, 4
  203. 1:
  204. #ifndef CONFIG_CPU_DCACHE_DISABLE
  205. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  206. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  207. #endif
  208. #ifndef CONFIG_CPU_ICACHE_DISABLE
  209. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  210. #endif
  211. add r0, r0, #CACHE_DLINESIZE
  212. cmp r0, r1
  213. blo 1b
  214. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  215. mov pc, lr
  216. /*
  217. * flush_kern_dcache_page(void *page)
  218. *
  219. * Ensure no D cache aliasing occurs, either with itself or
  220. * the I cache
  221. *
  222. * - page - page aligned address
  223. */
  224. ENTRY(arm1020_flush_kern_dcache_page)
  225. mov ip, #0
  226. #ifndef CONFIG_CPU_DCACHE_DISABLE
  227. add r1, r0, #PAGE_SZ
  228. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  229. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  230. add r0, r0, #CACHE_DLINESIZE
  231. cmp r0, r1
  232. blo 1b
  233. #endif
  234. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  235. mov pc, lr
  236. /*
  237. * dma_inv_range(start, end)
  238. *
  239. * Invalidate (discard) the specified virtual address range.
  240. * May not write back any entries. If 'start' or 'end'
  241. * are not cache line aligned, those lines must be written
  242. * back.
  243. *
  244. * - start - virtual start address
  245. * - end - virtual end address
  246. *
  247. * (same as v4wb)
  248. */
  249. ENTRY(arm1020_dma_inv_range)
  250. mov ip, #0
  251. #ifndef CONFIG_CPU_DCACHE_DISABLE
  252. tst r0, #CACHE_DLINESIZE - 1
  253. bic r0, r0, #CACHE_DLINESIZE - 1
  254. mcrne p15, 0, ip, c7, c10, 4
  255. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  256. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  257. tst r1, #CACHE_DLINESIZE - 1
  258. mcrne p15, 0, ip, c7, c10, 4
  259. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  260. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  261. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  262. add r0, r0, #CACHE_DLINESIZE
  263. cmp r0, r1
  264. blo 1b
  265. #endif
  266. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  267. mov pc, lr
  268. /*
  269. * dma_clean_range(start, end)
  270. *
  271. * Clean the specified virtual address range.
  272. *
  273. * - start - virtual start address
  274. * - end - virtual end address
  275. *
  276. * (same as v4wb)
  277. */
  278. ENTRY(arm1020_dma_clean_range)
  279. mov ip, #0
  280. #ifndef CONFIG_CPU_DCACHE_DISABLE
  281. bic r0, r0, #CACHE_DLINESIZE - 1
  282. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  283. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  284. add r0, r0, #CACHE_DLINESIZE
  285. cmp r0, r1
  286. blo 1b
  287. #endif
  288. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  289. mov pc, lr
  290. /*
  291. * dma_flush_range(start, end)
  292. *
  293. * Clean and invalidate the specified virtual address range.
  294. *
  295. * - start - virtual start address
  296. * - end - virtual end address
  297. */
  298. ENTRY(arm1020_dma_flush_range)
  299. mov ip, #0
  300. #ifndef CONFIG_CPU_DCACHE_DISABLE
  301. bic r0, r0, #CACHE_DLINESIZE - 1
  302. mcr p15, 0, ip, c7, c10, 4
  303. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  304. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  305. add r0, r0, #CACHE_DLINESIZE
  306. cmp r0, r1
  307. blo 1b
  308. #endif
  309. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  310. mov pc, lr
  311. ENTRY(arm1020_cache_fns)
  312. .long arm1020_flush_kern_cache_all
  313. .long arm1020_flush_user_cache_all
  314. .long arm1020_flush_user_cache_range
  315. .long arm1020_coherent_kern_range
  316. .long arm1020_coherent_user_range
  317. .long arm1020_flush_kern_dcache_page
  318. .long arm1020_dma_inv_range
  319. .long arm1020_dma_clean_range
  320. .long arm1020_dma_flush_range
  321. .align 5
  322. ENTRY(cpu_arm1020_dcache_clean_area)
  323. #ifndef CONFIG_CPU_DCACHE_DISABLE
  324. mov ip, #0
  325. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  326. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  327. add r0, r0, #CACHE_DLINESIZE
  328. subs r1, r1, #CACHE_DLINESIZE
  329. bhi 1b
  330. #endif
  331. mov pc, lr
  332. /* =============================== PageTable ============================== */
  333. /*
  334. * cpu_arm1020_switch_mm(pgd)
  335. *
  336. * Set the translation base pointer to be as described by pgd.
  337. *
  338. * pgd: new page tables
  339. */
  340. .align 5
  341. ENTRY(cpu_arm1020_switch_mm)
  342. #ifdef CONFIG_MMU
  343. #ifndef CONFIG_CPU_DCACHE_DISABLE
  344. mcr p15, 0, r3, c7, c10, 4
  345. mov r1, #0xF @ 16 segments
  346. 1: mov r3, #0x3F @ 64 entries
  347. 2: mov ip, r3, LSL #26 @ shift up entry
  348. orr ip, ip, r1, LSL #5 @ shift in/up index
  349. mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
  350. mov ip, #0
  351. mcr p15, 0, ip, c7, c10, 4
  352. subs r3, r3, #1
  353. cmp r3, #0
  354. bge 2b @ entries 3F to 0
  355. subs r1, r1, #1
  356. cmp r1, #0
  357. bge 1b @ segments 15 to 0
  358. #endif
  359. mov r1, #0
  360. #ifndef CONFIG_CPU_ICACHE_DISABLE
  361. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  362. #endif
  363. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  364. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  365. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  366. #endif /* CONFIG_MMU */
  367. mov pc, lr
  368. /*
  369. * cpu_arm1020_set_pte(ptep, pte)
  370. *
  371. * Set a PTE and flush it out
  372. */
  373. .align 5
  374. ENTRY(cpu_arm1020_set_pte_ext)
  375. #ifdef CONFIG_MMU
  376. str r1, [r0], #-2048 @ linux version
  377. eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
  378. bic r2, r1, #PTE_SMALL_AP_MASK
  379. bic r2, r2, #PTE_TYPE_MASK
  380. orr r2, r2, #PTE_TYPE_SMALL
  381. tst r1, #L_PTE_USER @ User?
  382. orrne r2, r2, #PTE_SMALL_AP_URO_SRW
  383. tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
  384. orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
  385. tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
  386. movne r2, #0
  387. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  388. eor r3, r1, #0x0a @ C & small page?
  389. tst r3, #0x0b
  390. biceq r2, r2, #4
  391. #endif
  392. str r2, [r0] @ hardware version
  393. mov r0, r0
  394. #ifndef CONFIG_CPU_DCACHE_DISABLE
  395. mcr p15, 0, r0, c7, c10, 4
  396. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  397. #endif
  398. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  399. #endif /* CONFIG_MMU */
  400. mov pc, lr
  401. __INIT
  402. .type __arm1020_setup, #function
  403. __arm1020_setup:
  404. mov r0, #0
  405. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  406. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  407. #ifdef CONFIG_MMU
  408. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  409. #endif
  410. adr r5, arm1020_crval
  411. ldmia r5, {r5, r6}
  412. mrc p15, 0, r0, c1, c0 @ get control register v4
  413. bic r0, r0, r5
  414. orr r0, r0, r6
  415. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  416. orr r0, r0, #0x4000 @ .R.. .... .... ....
  417. #endif
  418. mov pc, lr
  419. .size __arm1020_setup, . - __arm1020_setup
  420. /*
  421. * R
  422. * .RVI ZFRS BLDP WCAM
  423. * .011 1001 ..11 0101
  424. */
  425. .type arm1020_crval, #object
  426. arm1020_crval:
  427. crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
  428. __INITDATA
  429. /*
  430. * Purpose : Function pointers used to access above functions - all calls
  431. * come through these
  432. */
  433. .type arm1020_processor_functions, #object
  434. arm1020_processor_functions:
  435. .word v4t_early_abort
  436. .word cpu_arm1020_proc_init
  437. .word cpu_arm1020_proc_fin
  438. .word cpu_arm1020_reset
  439. .word cpu_arm1020_do_idle
  440. .word cpu_arm1020_dcache_clean_area
  441. .word cpu_arm1020_switch_mm
  442. .word cpu_arm1020_set_pte_ext
  443. .size arm1020_processor_functions, . - arm1020_processor_functions
  444. .section ".rodata"
  445. .type cpu_arch_name, #object
  446. cpu_arch_name:
  447. .asciz "armv5t"
  448. .size cpu_arch_name, . - cpu_arch_name
  449. .type cpu_elf_name, #object
  450. cpu_elf_name:
  451. .asciz "v5"
  452. .size cpu_elf_name, . - cpu_elf_name
  453. .type cpu_arm1020_name, #object
  454. cpu_arm1020_name:
  455. .ascii "ARM1020"
  456. #ifndef CONFIG_CPU_ICACHE_DISABLE
  457. .ascii "i"
  458. #endif
  459. #ifndef CONFIG_CPU_DCACHE_DISABLE
  460. .ascii "d"
  461. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  462. .ascii "(wt)"
  463. #else
  464. .ascii "(wb)"
  465. #endif
  466. #endif
  467. #ifndef CONFIG_CPU_BPREDICT_DISABLE
  468. .ascii "B"
  469. #endif
  470. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  471. .ascii "RR"
  472. #endif
  473. .ascii "\0"
  474. .size cpu_arm1020_name, . - cpu_arm1020_name
  475. .align
  476. .section ".proc.info.init", #alloc, #execinstr
  477. .type __arm1020_proc_info,#object
  478. __arm1020_proc_info:
  479. .long 0x4104a200 @ ARM 1020T (Architecture v5T)
  480. .long 0xff0ffff0
  481. .long PMD_TYPE_SECT | \
  482. PMD_SECT_AP_WRITE | \
  483. PMD_SECT_AP_READ
  484. .long PMD_TYPE_SECT | \
  485. PMD_SECT_AP_WRITE | \
  486. PMD_SECT_AP_READ
  487. b __arm1020_setup
  488. .long cpu_arch_name
  489. .long cpu_elf_name
  490. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  491. .long cpu_arm1020_name
  492. .long arm1020_processor_functions
  493. .long v4wbi_tlb_fns
  494. .long v4wb_user_fns
  495. .long arm1020_cache_fns
  496. .size __arm1020_proc_info, . - __arm1020_proc_info