mmu.c 20 KB

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  1. /*
  2. * linux/arch/arm/mm/mmu.c
  3. *
  4. * Copyright (C) 1995-2005 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/init.h>
  14. #include <linux/bootmem.h>
  15. #include <linux/mman.h>
  16. #include <linux/nodemask.h>
  17. #include <asm/mach-types.h>
  18. #include <asm/setup.h>
  19. #include <asm/sizes.h>
  20. #include <asm/tlb.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include "mm.h"
  24. DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  25. extern void _stext, _etext, __data_start, _end;
  26. extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  27. /*
  28. * empty_zero_page is a special page that is used for
  29. * zero-initialized data and COW.
  30. */
  31. struct page *empty_zero_page;
  32. /*
  33. * The pmd table for the upper-most set of pages.
  34. */
  35. pmd_t *top_pmd;
  36. #define CPOLICY_UNCACHED 0
  37. #define CPOLICY_BUFFERED 1
  38. #define CPOLICY_WRITETHROUGH 2
  39. #define CPOLICY_WRITEBACK 3
  40. #define CPOLICY_WRITEALLOC 4
  41. static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  42. static unsigned int ecc_mask __initdata = 0;
  43. pgprot_t pgprot_user;
  44. pgprot_t pgprot_kernel;
  45. EXPORT_SYMBOL(pgprot_user);
  46. EXPORT_SYMBOL(pgprot_kernel);
  47. struct cachepolicy {
  48. const char policy[16];
  49. unsigned int cr_mask;
  50. unsigned int pmd;
  51. unsigned int pte;
  52. };
  53. static struct cachepolicy cache_policies[] __initdata = {
  54. {
  55. .policy = "uncached",
  56. .cr_mask = CR_W|CR_C,
  57. .pmd = PMD_SECT_UNCACHED,
  58. .pte = 0,
  59. }, {
  60. .policy = "buffered",
  61. .cr_mask = CR_C,
  62. .pmd = PMD_SECT_BUFFERED,
  63. .pte = PTE_BUFFERABLE,
  64. }, {
  65. .policy = "writethrough",
  66. .cr_mask = 0,
  67. .pmd = PMD_SECT_WT,
  68. .pte = PTE_CACHEABLE,
  69. }, {
  70. .policy = "writeback",
  71. .cr_mask = 0,
  72. .pmd = PMD_SECT_WB,
  73. .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
  74. }, {
  75. .policy = "writealloc",
  76. .cr_mask = 0,
  77. .pmd = PMD_SECT_WBWA,
  78. .pte = PTE_BUFFERABLE|PTE_CACHEABLE,
  79. }
  80. };
  81. /*
  82. * These are useful for identifing cache coherency
  83. * problems by allowing the cache or the cache and
  84. * writebuffer to be turned off. (Note: the write
  85. * buffer should not be on and the cache off).
  86. */
  87. static void __init early_cachepolicy(char **p)
  88. {
  89. int i;
  90. for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  91. int len = strlen(cache_policies[i].policy);
  92. if (memcmp(*p, cache_policies[i].policy, len) == 0) {
  93. cachepolicy = i;
  94. cr_alignment &= ~cache_policies[i].cr_mask;
  95. cr_no_alignment &= ~cache_policies[i].cr_mask;
  96. *p += len;
  97. break;
  98. }
  99. }
  100. if (i == ARRAY_SIZE(cache_policies))
  101. printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
  102. flush_cache_all();
  103. set_cr(cr_alignment);
  104. }
  105. __early_param("cachepolicy=", early_cachepolicy);
  106. static void __init early_nocache(char **__unused)
  107. {
  108. char *p = "buffered";
  109. printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
  110. early_cachepolicy(&p);
  111. }
  112. __early_param("nocache", early_nocache);
  113. static void __init early_nowrite(char **__unused)
  114. {
  115. char *p = "uncached";
  116. printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
  117. early_cachepolicy(&p);
  118. }
  119. __early_param("nowb", early_nowrite);
  120. static void __init early_ecc(char **p)
  121. {
  122. if (memcmp(*p, "on", 2) == 0) {
  123. ecc_mask = PMD_PROTECTION;
  124. *p += 2;
  125. } else if (memcmp(*p, "off", 3) == 0) {
  126. ecc_mask = 0;
  127. *p += 3;
  128. }
  129. }
  130. __early_param("ecc=", early_ecc);
  131. static int __init noalign_setup(char *__unused)
  132. {
  133. cr_alignment &= ~CR_A;
  134. cr_no_alignment &= ~CR_A;
  135. set_cr(cr_alignment);
  136. return 1;
  137. }
  138. __setup("noalign", noalign_setup);
  139. #ifndef CONFIG_SMP
  140. void adjust_cr(unsigned long mask, unsigned long set)
  141. {
  142. unsigned long flags;
  143. mask &= ~CR_A;
  144. set &= mask;
  145. local_irq_save(flags);
  146. cr_no_alignment = (cr_no_alignment & ~mask) | set;
  147. cr_alignment = (cr_alignment & ~mask) | set;
  148. set_cr((get_cr() & ~mask) | set);
  149. local_irq_restore(flags);
  150. }
  151. #endif
  152. struct mem_types {
  153. unsigned int prot_pte;
  154. unsigned int prot_l1;
  155. unsigned int prot_sect;
  156. unsigned int domain;
  157. };
  158. static struct mem_types mem_types[] __initdata = {
  159. [MT_DEVICE] = {
  160. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  161. L_PTE_WRITE,
  162. .prot_l1 = PMD_TYPE_TABLE,
  163. .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
  164. PMD_SECT_AP_WRITE,
  165. .domain = DOMAIN_IO,
  166. },
  167. [MT_CACHECLEAN] = {
  168. .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
  169. .domain = DOMAIN_KERNEL,
  170. },
  171. [MT_MINICLEAN] = {
  172. .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_MINICACHE,
  173. .domain = DOMAIN_KERNEL,
  174. },
  175. [MT_LOW_VECTORS] = {
  176. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  177. L_PTE_EXEC,
  178. .prot_l1 = PMD_TYPE_TABLE,
  179. .domain = DOMAIN_USER,
  180. },
  181. [MT_HIGH_VECTORS] = {
  182. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  183. L_PTE_USER | L_PTE_EXEC,
  184. .prot_l1 = PMD_TYPE_TABLE,
  185. .domain = DOMAIN_USER,
  186. },
  187. [MT_MEMORY] = {
  188. .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_AP_WRITE,
  189. .domain = DOMAIN_KERNEL,
  190. },
  191. [MT_ROM] = {
  192. .prot_sect = PMD_TYPE_SECT | PMD_BIT4,
  193. .domain = DOMAIN_KERNEL,
  194. },
  195. [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
  196. .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
  197. L_PTE_WRITE,
  198. .prot_l1 = PMD_TYPE_TABLE,
  199. .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_UNCACHED |
  200. PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
  201. PMD_SECT_TEX(1),
  202. .domain = DOMAIN_IO,
  203. },
  204. [MT_NONSHARED_DEVICE] = {
  205. .prot_l1 = PMD_TYPE_TABLE,
  206. .prot_sect = PMD_TYPE_SECT | PMD_BIT4 | PMD_SECT_NONSHARED_DEV |
  207. PMD_SECT_AP_WRITE,
  208. .domain = DOMAIN_IO,
  209. }
  210. };
  211. /*
  212. * Adjust the PMD section entries according to the CPU in use.
  213. */
  214. static void __init build_mem_type_table(void)
  215. {
  216. struct cachepolicy *cp;
  217. unsigned int cr = get_cr();
  218. unsigned int user_pgprot, kern_pgprot;
  219. int cpu_arch = cpu_architecture();
  220. int i;
  221. #if defined(CONFIG_CPU_DCACHE_DISABLE)
  222. if (cachepolicy > CPOLICY_BUFFERED)
  223. cachepolicy = CPOLICY_BUFFERED;
  224. #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
  225. if (cachepolicy > CPOLICY_WRITETHROUGH)
  226. cachepolicy = CPOLICY_WRITETHROUGH;
  227. #endif
  228. if (cpu_arch < CPU_ARCH_ARMv5) {
  229. if (cachepolicy >= CPOLICY_WRITEALLOC)
  230. cachepolicy = CPOLICY_WRITEBACK;
  231. ecc_mask = 0;
  232. }
  233. /*
  234. * Xscale must not have PMD bit 4 set for section mappings.
  235. */
  236. if (cpu_is_xscale())
  237. for (i = 0; i < ARRAY_SIZE(mem_types); i++)
  238. mem_types[i].prot_sect &= ~PMD_BIT4;
  239. /*
  240. * ARMv5 and lower, excluding Xscale, bit 4 must be set for
  241. * page tables.
  242. */
  243. if (cpu_arch < CPU_ARCH_ARMv6 && !cpu_is_xscale())
  244. for (i = 0; i < ARRAY_SIZE(mem_types); i++)
  245. if (mem_types[i].prot_l1)
  246. mem_types[i].prot_l1 |= PMD_BIT4;
  247. cp = &cache_policies[cachepolicy];
  248. kern_pgprot = user_pgprot = cp->pte;
  249. /*
  250. * Enable CPU-specific coherency if supported.
  251. * (Only available on XSC3 at the moment.)
  252. */
  253. if (arch_is_coherent()) {
  254. if (cpu_is_xsc3()) {
  255. mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
  256. mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
  257. }
  258. }
  259. /*
  260. * ARMv6 and above have extended page tables.
  261. */
  262. if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
  263. /*
  264. * bit 4 becomes XN which we must clear for the
  265. * kernel memory mapping.
  266. */
  267. mem_types[MT_MEMORY].prot_sect &= ~PMD_SECT_XN;
  268. mem_types[MT_ROM].prot_sect &= ~PMD_SECT_XN;
  269. /*
  270. * Mark cache clean areas and XIP ROM read only
  271. * from SVC mode and no access from userspace.
  272. */
  273. mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  274. mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  275. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
  276. /*
  277. * Mark the device area as "shared device"
  278. */
  279. mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
  280. mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
  281. #ifdef CONFIG_SMP
  282. /*
  283. * Mark memory with the "shared" attribute for SMP systems
  284. */
  285. user_pgprot |= L_PTE_SHARED;
  286. kern_pgprot |= L_PTE_SHARED;
  287. mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
  288. #endif
  289. }
  290. for (i = 0; i < 16; i++) {
  291. unsigned long v = pgprot_val(protection_map[i]);
  292. v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
  293. protection_map[i] = __pgprot(v);
  294. }
  295. mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
  296. mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
  297. if (cpu_arch >= CPU_ARCH_ARMv5) {
  298. #ifndef CONFIG_SMP
  299. /*
  300. * Only use write-through for non-SMP systems
  301. */
  302. mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
  303. mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
  304. #endif
  305. } else {
  306. mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
  307. }
  308. pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
  309. pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
  310. L_PTE_DIRTY | L_PTE_WRITE |
  311. L_PTE_EXEC | kern_pgprot);
  312. mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
  313. mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
  314. mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
  315. mem_types[MT_ROM].prot_sect |= cp->pmd;
  316. switch (cp->pmd) {
  317. case PMD_SECT_WT:
  318. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
  319. break;
  320. case PMD_SECT_WB:
  321. case PMD_SECT_WBWA:
  322. mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
  323. break;
  324. }
  325. printk("Memory policy: ECC %sabled, Data cache %s\n",
  326. ecc_mask ? "en" : "dis", cp->policy);
  327. }
  328. #define vectors_base() (vectors_high() ? 0xffff0000 : 0)
  329. /*
  330. * Create a SECTION PGD between VIRT and PHYS in domain
  331. * DOMAIN with protection PROT. This operates on half-
  332. * pgdir entry increments.
  333. */
  334. static inline void
  335. alloc_init_section(unsigned long virt, unsigned long phys, int prot)
  336. {
  337. pmd_t *pmdp = pmd_off_k(virt);
  338. if (virt & (1 << 20))
  339. pmdp++;
  340. *pmdp = __pmd(phys | prot);
  341. flush_pmd_entry(pmdp);
  342. }
  343. /*
  344. * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
  345. */
  346. static inline void
  347. alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
  348. {
  349. int i;
  350. for (i = 0; i < 16; i += 1) {
  351. alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
  352. virt += (PGDIR_SIZE / 2);
  353. }
  354. }
  355. /*
  356. * Add a PAGE mapping between VIRT and PHYS in domain
  357. * DOMAIN with protection PROT. Note that due to the
  358. * way we map the PTEs, we must allocate two PTE_SIZE'd
  359. * blocks - one for the Linux pte table, and one for
  360. * the hardware pte table.
  361. */
  362. static inline void
  363. alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
  364. {
  365. pmd_t *pmdp = pmd_off_k(virt);
  366. pte_t *ptep;
  367. if (pmd_none(*pmdp)) {
  368. ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
  369. sizeof(pte_t));
  370. __pmd_populate(pmdp, __pa(ptep) | prot_l1);
  371. }
  372. ptep = pte_offset_kernel(pmdp, virt);
  373. set_pte_ext(ptep, pfn_pte(phys >> PAGE_SHIFT, prot), 0);
  374. }
  375. /*
  376. * Create the page directory entries and any necessary
  377. * page tables for the mapping specified by `md'. We
  378. * are able to cope here with varying sizes and address
  379. * offsets, and we take full advantage of sections and
  380. * supersections.
  381. */
  382. void __init create_mapping(struct map_desc *md)
  383. {
  384. unsigned long virt, length;
  385. int prot_sect, prot_l1, domain;
  386. pgprot_t prot_pte;
  387. unsigned long off = (u32)__pfn_to_phys(md->pfn);
  388. if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
  389. printk(KERN_WARNING "BUG: not creating mapping for "
  390. "0x%08llx at 0x%08lx in user region\n",
  391. __pfn_to_phys((u64)md->pfn), md->virtual);
  392. return;
  393. }
  394. if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
  395. md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
  396. printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
  397. "overlaps vmalloc space\n",
  398. __pfn_to_phys((u64)md->pfn), md->virtual);
  399. }
  400. domain = mem_types[md->type].domain;
  401. prot_pte = __pgprot(mem_types[md->type].prot_pte);
  402. prot_l1 = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
  403. prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
  404. /*
  405. * Catch 36-bit addresses
  406. */
  407. if(md->pfn >= 0x100000) {
  408. if(domain) {
  409. printk(KERN_ERR "MM: invalid domain in supersection "
  410. "mapping for 0x%08llx at 0x%08lx\n",
  411. __pfn_to_phys((u64)md->pfn), md->virtual);
  412. return;
  413. }
  414. if((md->virtual | md->length | __pfn_to_phys(md->pfn))
  415. & ~SUPERSECTION_MASK) {
  416. printk(KERN_ERR "MM: cannot create mapping for "
  417. "0x%08llx at 0x%08lx invalid alignment\n",
  418. __pfn_to_phys((u64)md->pfn), md->virtual);
  419. return;
  420. }
  421. /*
  422. * Shift bits [35:32] of address into bits [23:20] of PMD
  423. * (See ARMv6 spec).
  424. */
  425. off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
  426. }
  427. virt = md->virtual;
  428. off -= virt;
  429. length = md->length;
  430. if (mem_types[md->type].prot_l1 == 0 &&
  431. (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
  432. printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
  433. "be mapped using pages, ignoring.\n",
  434. __pfn_to_phys(md->pfn), md->virtual);
  435. return;
  436. }
  437. while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
  438. alloc_init_page(virt, virt + off, prot_l1, prot_pte);
  439. virt += PAGE_SIZE;
  440. length -= PAGE_SIZE;
  441. }
  442. /* N.B. ARMv6 supersections are only defined to work with domain 0.
  443. * Since domain assignments can in fact be arbitrary, the
  444. * 'domain == 0' check below is required to insure that ARMv6
  445. * supersections are only allocated for domain 0 regardless
  446. * of the actual domain assignments in use.
  447. */
  448. if ((cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())
  449. && domain == 0) {
  450. /*
  451. * Align to supersection boundary if !high pages.
  452. * High pages have already been checked for proper
  453. * alignment above and they will fail the SUPSERSECTION_MASK
  454. * check because of the way the address is encoded into
  455. * offset.
  456. */
  457. if (md->pfn <= 0x100000) {
  458. while ((virt & ~SUPERSECTION_MASK ||
  459. (virt + off) & ~SUPERSECTION_MASK) &&
  460. length >= (PGDIR_SIZE / 2)) {
  461. alloc_init_section(virt, virt + off, prot_sect);
  462. virt += (PGDIR_SIZE / 2);
  463. length -= (PGDIR_SIZE / 2);
  464. }
  465. }
  466. while (length >= SUPERSECTION_SIZE) {
  467. alloc_init_supersection(virt, virt + off, prot_sect);
  468. virt += SUPERSECTION_SIZE;
  469. length -= SUPERSECTION_SIZE;
  470. }
  471. }
  472. /*
  473. * A section mapping covers half a "pgdir" entry.
  474. */
  475. while (length >= (PGDIR_SIZE / 2)) {
  476. alloc_init_section(virt, virt + off, prot_sect);
  477. virt += (PGDIR_SIZE / 2);
  478. length -= (PGDIR_SIZE / 2);
  479. }
  480. while (length >= PAGE_SIZE) {
  481. alloc_init_page(virt, virt + off, prot_l1, prot_pte);
  482. virt += PAGE_SIZE;
  483. length -= PAGE_SIZE;
  484. }
  485. }
  486. /*
  487. * Create the architecture specific mappings
  488. */
  489. void __init iotable_init(struct map_desc *io_desc, int nr)
  490. {
  491. int i;
  492. for (i = 0; i < nr; i++)
  493. create_mapping(io_desc + i);
  494. }
  495. static inline void prepare_page_table(struct meminfo *mi)
  496. {
  497. unsigned long addr;
  498. /*
  499. * Clear out all the mappings below the kernel image.
  500. */
  501. for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE)
  502. pmd_clear(pmd_off_k(addr));
  503. #ifdef CONFIG_XIP_KERNEL
  504. /* The XIP kernel is mapped in the module area -- skip over it */
  505. addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
  506. #endif
  507. for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
  508. pmd_clear(pmd_off_k(addr));
  509. /*
  510. * Clear out all the kernel space mappings, except for the first
  511. * memory bank, up to the end of the vmalloc region.
  512. */
  513. for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size);
  514. addr < VMALLOC_END; addr += PGDIR_SIZE)
  515. pmd_clear(pmd_off_k(addr));
  516. }
  517. /*
  518. * Reserve the various regions of node 0
  519. */
  520. void __init reserve_node_zero(pg_data_t *pgdat)
  521. {
  522. unsigned long res_size = 0;
  523. /*
  524. * Register the kernel text and data with bootmem.
  525. * Note that this can only be in node 0.
  526. */
  527. #ifdef CONFIG_XIP_KERNEL
  528. reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start);
  529. #else
  530. reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext);
  531. #endif
  532. /*
  533. * Reserve the page tables. These are already in use,
  534. * and can only be in node 0.
  535. */
  536. reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
  537. PTRS_PER_PGD * sizeof(pgd_t));
  538. /*
  539. * Hmm... This should go elsewhere, but we really really need to
  540. * stop things allocating the low memory; ideally we need a better
  541. * implementation of GFP_DMA which does not assume that DMA-able
  542. * memory starts at zero.
  543. */
  544. if (machine_is_integrator() || machine_is_cintegrator())
  545. res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
  546. /*
  547. * These should likewise go elsewhere. They pre-reserve the
  548. * screen memory region at the start of main system memory.
  549. */
  550. if (machine_is_edb7211())
  551. res_size = 0x00020000;
  552. if (machine_is_p720t())
  553. res_size = 0x00014000;
  554. /* H1940 and RX3715 need to reserve this for suspend */
  555. if (machine_is_h1940() || machine_is_rx3715()) {
  556. reserve_bootmem_node(pgdat, 0x30003000, 0x1000);
  557. reserve_bootmem_node(pgdat, 0x30081000, 0x1000);
  558. }
  559. #ifdef CONFIG_SA1111
  560. /*
  561. * Because of the SA1111 DMA bug, we want to preserve our
  562. * precious DMA-able memory...
  563. */
  564. res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
  565. #endif
  566. if (res_size)
  567. reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size);
  568. }
  569. /*
  570. * Set up device the mappings. Since we clear out the page tables for all
  571. * mappings above VMALLOC_END, we will remove any debug device mappings.
  572. * This means you have to be careful how you debug this function, or any
  573. * called function. This means you can't use any function or debugging
  574. * method which may touch any device, otherwise the kernel _will_ crash.
  575. */
  576. static void __init devicemaps_init(struct machine_desc *mdesc)
  577. {
  578. struct map_desc map;
  579. unsigned long addr;
  580. void *vectors;
  581. /*
  582. * Allocate the vector page early.
  583. */
  584. vectors = alloc_bootmem_low_pages(PAGE_SIZE);
  585. BUG_ON(!vectors);
  586. for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
  587. pmd_clear(pmd_off_k(addr));
  588. /*
  589. * Map the kernel if it is XIP.
  590. * It is always first in the modulearea.
  591. */
  592. #ifdef CONFIG_XIP_KERNEL
  593. map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
  594. map.virtual = MODULE_START;
  595. map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
  596. map.type = MT_ROM;
  597. create_mapping(&map);
  598. #endif
  599. /*
  600. * Map the cache flushing regions.
  601. */
  602. #ifdef FLUSH_BASE
  603. map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
  604. map.virtual = FLUSH_BASE;
  605. map.length = SZ_1M;
  606. map.type = MT_CACHECLEAN;
  607. create_mapping(&map);
  608. #endif
  609. #ifdef FLUSH_BASE_MINICACHE
  610. map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
  611. map.virtual = FLUSH_BASE_MINICACHE;
  612. map.length = SZ_1M;
  613. map.type = MT_MINICLEAN;
  614. create_mapping(&map);
  615. #endif
  616. /*
  617. * Create a mapping for the machine vectors at the high-vectors
  618. * location (0xffff0000). If we aren't using high-vectors, also
  619. * create a mapping at the low-vectors virtual address.
  620. */
  621. map.pfn = __phys_to_pfn(virt_to_phys(vectors));
  622. map.virtual = 0xffff0000;
  623. map.length = PAGE_SIZE;
  624. map.type = MT_HIGH_VECTORS;
  625. create_mapping(&map);
  626. if (!vectors_high()) {
  627. map.virtual = 0;
  628. map.type = MT_LOW_VECTORS;
  629. create_mapping(&map);
  630. }
  631. /*
  632. * Ask the machine support to map in the statically mapped devices.
  633. */
  634. if (mdesc->map_io)
  635. mdesc->map_io();
  636. /*
  637. * Finally flush the caches and tlb to ensure that we're in a
  638. * consistent state wrt the writebuffer. This also ensures that
  639. * any write-allocated cache lines in the vector page are written
  640. * back. After this point, we can start to touch devices again.
  641. */
  642. local_flush_tlb_all();
  643. flush_cache_all();
  644. }
  645. /*
  646. * paging_init() sets up the page tables, initialises the zone memory
  647. * maps, and sets up the zero page, bad page and bad page tables.
  648. */
  649. void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc)
  650. {
  651. void *zero_page;
  652. build_mem_type_table();
  653. prepare_page_table(mi);
  654. bootmem_init(mi);
  655. devicemaps_init(mdesc);
  656. top_pmd = pmd_off_k(0xffff0000);
  657. /*
  658. * allocate the zero page. Note that we count on this going ok.
  659. */
  660. zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
  661. memzero(zero_page, PAGE_SIZE);
  662. empty_zero_page = virt_to_page(zero_page);
  663. flush_dcache_page(empty_zero_page);
  664. }
  665. /*
  666. * In order to soft-boot, we need to insert a 1:1 mapping in place of
  667. * the user-mode pages. This will then ensure that we have predictable
  668. * results when turning the mmu off
  669. */
  670. void setup_mm_for_reboot(char mode)
  671. {
  672. unsigned long base_pmdval;
  673. pgd_t *pgd;
  674. int i;
  675. if (current->mm && current->mm->pgd)
  676. pgd = current->mm->pgd;
  677. else
  678. pgd = init_mm.pgd;
  679. base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
  680. if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
  681. base_pmdval |= PMD_BIT4;
  682. for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
  683. unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
  684. pmd_t *pmd;
  685. pmd = pmd_off(pgd, i << PGDIR_SHIFT);
  686. pmd[0] = __pmd(pmdval);
  687. pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
  688. flush_pmd_entry(pmd);
  689. }
  690. }