copypage-v4mc.c 3.4 KB

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  1. /*
  2. * linux/arch/arm/lib/copypage-armv4mc.S
  3. *
  4. * Copyright (C) 1995-2005 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This handles the mini data cache, as found on SA11x0 and XScale
  11. * processors. When we copy a user page page, we map it in such a way
  12. * that accesses to this page will not touch the main data cache, but
  13. * will be cached in the mini data cache. This prevents us thrashing
  14. * the main data cache on page faults.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/mm.h>
  18. #include <asm/page.h>
  19. #include <asm/pgtable.h>
  20. #include <asm/tlbflush.h>
  21. #include <asm/cacheflush.h>
  22. #include "mm.h"
  23. /*
  24. * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
  25. * specific hacks for copying pages efficiently.
  26. */
  27. #define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
  28. L_PTE_CACHEABLE)
  29. static DEFINE_SPINLOCK(minicache_lock);
  30. /*
  31. * ARMv4 mini-dcache optimised copy_user_page
  32. *
  33. * We flush the destination cache lines just before we write the data into the
  34. * corresponding address. Since the Dcache is read-allocate, this removes the
  35. * Dcache aliasing issue. The writes will be forwarded to the write buffer,
  36. * and merged as appropriate.
  37. *
  38. * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
  39. * instruction. If your processor does not supply this, you have to write your
  40. * own copy_user_page that does the right thing.
  41. */
  42. static void __attribute__((naked))
  43. mc_copy_user_page(void *from, void *to)
  44. {
  45. asm volatile(
  46. "stmfd sp!, {r4, lr} @ 2\n\
  47. mov r4, %2 @ 1\n\
  48. ldmia %0!, {r2, r3, ip, lr} @ 4\n\
  49. 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
  50. stmia %1!, {r2, r3, ip, lr} @ 4\n\
  51. ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\
  52. stmia %1!, {r2, r3, ip, lr} @ 4\n\
  53. ldmia %0!, {r2, r3, ip, lr} @ 4\n\
  54. mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
  55. stmia %1!, {r2, r3, ip, lr} @ 4\n\
  56. ldmia %0!, {r2, r3, ip, lr} @ 4\n\
  57. subs r4, r4, #1 @ 1\n\
  58. stmia %1!, {r2, r3, ip, lr} @ 4\n\
  59. ldmneia %0!, {r2, r3, ip, lr} @ 4\n\
  60. bne 1b @ 1\n\
  61. ldmfd sp!, {r4, pc} @ 3"
  62. :
  63. : "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
  64. }
  65. void v4_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
  66. {
  67. struct page *page = virt_to_page(kfrom);
  68. if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
  69. __flush_dcache_page(page_mapping(page), page);
  70. spin_lock(&minicache_lock);
  71. set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot), 0);
  72. flush_tlb_kernel_page(0xffff8000);
  73. mc_copy_user_page((void *)0xffff8000, kto);
  74. spin_unlock(&minicache_lock);
  75. }
  76. /*
  77. * ARMv4 optimised clear_user_page
  78. */
  79. void __attribute__((naked))
  80. v4_mc_clear_user_page(void *kaddr, unsigned long vaddr)
  81. {
  82. asm volatile(
  83. "str lr, [sp, #-4]!\n\
  84. mov r1, %0 @ 1\n\
  85. mov r2, #0 @ 1\n\
  86. mov r3, #0 @ 1\n\
  87. mov ip, #0 @ 1\n\
  88. mov lr, #0 @ 1\n\
  89. 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
  90. stmia r0!, {r2, r3, ip, lr} @ 4\n\
  91. stmia r0!, {r2, r3, ip, lr} @ 4\n\
  92. mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\
  93. stmia r0!, {r2, r3, ip, lr} @ 4\n\
  94. stmia r0!, {r2, r3, ip, lr} @ 4\n\
  95. subs r1, r1, #1 @ 1\n\
  96. bne 1b @ 1\n\
  97. ldr pc, [sp], #4"
  98. :
  99. : "I" (PAGE_SIZE / 64));
  100. }
  101. struct cpu_user_fns v4_mc_user_fns __initdata = {
  102. .cpu_clear_user_page = v4_mc_clear_user_page,
  103. .cpu_copy_user_page = v4_mc_copy_user_page,
  104. };