cache-v6.S 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. /*
  2. * linux/arch/arm/mm/cache-v6.S
  3. *
  4. * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This is the "shell" of the ARMv6 processor support.
  11. */
  12. #include <linux/linkage.h>
  13. #include <linux/init.h>
  14. #include <asm/assembler.h>
  15. #include "proc-macros.S"
  16. #define HARVARD_CACHE
  17. #define CACHE_LINE_SIZE 32
  18. #define D_CACHE_LINE_SIZE 32
  19. #define BTB_FLUSH_SIZE 8
  20. /*
  21. * v6_flush_cache_all()
  22. *
  23. * Flush the entire cache.
  24. *
  25. * It is assumed that:
  26. */
  27. ENTRY(v6_flush_kern_cache_all)
  28. mov r0, #0
  29. #ifdef HARVARD_CACHE
  30. mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
  31. mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
  32. #else
  33. mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
  34. #endif
  35. mov pc, lr
  36. /*
  37. * v6_flush_cache_all()
  38. *
  39. * Flush all TLB entries in a particular address space
  40. *
  41. * - mm - mm_struct describing address space
  42. */
  43. ENTRY(v6_flush_user_cache_all)
  44. /*FALLTHROUGH*/
  45. /*
  46. * v6_flush_cache_range(start, end, flags)
  47. *
  48. * Flush a range of TLB entries in the specified address space.
  49. *
  50. * - start - start address (may not be aligned)
  51. * - end - end address (exclusive, may not be aligned)
  52. * - flags - vm_area_struct flags describing address space
  53. *
  54. * It is assumed that:
  55. * - we have a VIPT cache.
  56. */
  57. ENTRY(v6_flush_user_cache_range)
  58. mov pc, lr
  59. /*
  60. * v6_coherent_kern_range(start,end)
  61. *
  62. * Ensure that the I and D caches are coherent within specified
  63. * region. This is typically used when code has been written to
  64. * a memory region, and will be executed.
  65. *
  66. * - start - virtual start address of region
  67. * - end - virtual end address of region
  68. *
  69. * It is assumed that:
  70. * - the Icache does not read data from the write buffer
  71. */
  72. ENTRY(v6_coherent_kern_range)
  73. /* FALLTHROUGH */
  74. /*
  75. * v6_coherent_user_range(start,end)
  76. *
  77. * Ensure that the I and D caches are coherent within specified
  78. * region. This is typically used when code has been written to
  79. * a memory region, and will be executed.
  80. *
  81. * - start - virtual start address of region
  82. * - end - virtual end address of region
  83. *
  84. * It is assumed that:
  85. * - the Icache does not read data from the write buffer
  86. */
  87. ENTRY(v6_coherent_user_range)
  88. #ifdef HARVARD_CACHE
  89. bic r0, r0, #CACHE_LINE_SIZE - 1
  90. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line
  91. add r0, r0, #CACHE_LINE_SIZE
  92. cmp r0, r1
  93. blo 1b
  94. #endif
  95. mov r0, #0
  96. #ifdef HARVARD_CACHE
  97. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  98. mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
  99. #else
  100. mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
  101. #endif
  102. mov pc, lr
  103. /*
  104. * v6_flush_kern_dcache_page(kaddr)
  105. *
  106. * Ensure that the data held in the page kaddr is written back
  107. * to the page in question.
  108. *
  109. * - kaddr - kernel address (guaranteed to be page aligned)
  110. */
  111. ENTRY(v6_flush_kern_dcache_page)
  112. add r1, r0, #PAGE_SZ
  113. 1:
  114. #ifdef HARVARD_CACHE
  115. mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
  116. #else
  117. mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
  118. #endif
  119. add r0, r0, #D_CACHE_LINE_SIZE
  120. cmp r0, r1
  121. blo 1b
  122. #ifdef HARVARD_CACHE
  123. mov r0, #0
  124. mcr p15, 0, r0, c7, c10, 4
  125. #endif
  126. mov pc, lr
  127. /*
  128. * v6_dma_inv_range(start,end)
  129. *
  130. * Invalidate the data cache within the specified region; we will
  131. * be performing a DMA operation in this region and we want to
  132. * purge old data in the cache.
  133. *
  134. * - start - virtual start address of region
  135. * - end - virtual end address of region
  136. */
  137. ENTRY(v6_dma_inv_range)
  138. tst r0, #D_CACHE_LINE_SIZE - 1
  139. bic r0, r0, #D_CACHE_LINE_SIZE - 1
  140. #ifdef HARVARD_CACHE
  141. mcrne p15, 0, r0, c7, c10, 1 @ clean D line
  142. #else
  143. mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
  144. #endif
  145. tst r1, #D_CACHE_LINE_SIZE - 1
  146. bic r1, r1, #D_CACHE_LINE_SIZE - 1
  147. #ifdef HARVARD_CACHE
  148. mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
  149. #else
  150. mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
  151. #endif
  152. 1:
  153. #ifdef HARVARD_CACHE
  154. mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
  155. #else
  156. mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
  157. #endif
  158. add r0, r0, #D_CACHE_LINE_SIZE
  159. cmp r0, r1
  160. blo 1b
  161. mov r0, #0
  162. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  163. mov pc, lr
  164. /*
  165. * v6_dma_clean_range(start,end)
  166. * - start - virtual start address of region
  167. * - end - virtual end address of region
  168. */
  169. ENTRY(v6_dma_clean_range)
  170. bic r0, r0, #D_CACHE_LINE_SIZE - 1
  171. 1:
  172. #ifdef HARVARD_CACHE
  173. mcr p15, 0, r0, c7, c10, 1 @ clean D line
  174. #else
  175. mcr p15, 0, r0, c7, c11, 1 @ clean unified line
  176. #endif
  177. add r0, r0, #D_CACHE_LINE_SIZE
  178. cmp r0, r1
  179. blo 1b
  180. mov r0, #0
  181. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  182. mov pc, lr
  183. /*
  184. * v6_dma_flush_range(start,end)
  185. * - start - virtual start address of region
  186. * - end - virtual end address of region
  187. */
  188. ENTRY(v6_dma_flush_range)
  189. bic r0, r0, #D_CACHE_LINE_SIZE - 1
  190. 1:
  191. #ifdef HARVARD_CACHE
  192. mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
  193. #else
  194. mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
  195. #endif
  196. add r0, r0, #D_CACHE_LINE_SIZE
  197. cmp r0, r1
  198. blo 1b
  199. mov r0, #0
  200. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  201. mov pc, lr
  202. __INITDATA
  203. .type v6_cache_fns, #object
  204. ENTRY(v6_cache_fns)
  205. .long v6_flush_kern_cache_all
  206. .long v6_flush_user_cache_all
  207. .long v6_flush_user_cache_range
  208. .long v6_coherent_kern_range
  209. .long v6_coherent_user_range
  210. .long v6_flush_kern_dcache_page
  211. .long v6_dma_inv_range
  212. .long v6_dma_clean_range
  213. .long v6_dma_flush_range
  214. .size v6_cache_fns, . - v6_cache_fns