cache-v3.S 3.1 KB

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  1. /*
  2. * linux/arch/arm/mm/cache-v3.S
  3. *
  4. * Copyright (C) 1997-2002 Russell king
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/linkage.h>
  11. #include <linux/init.h>
  12. #include <asm/hardware.h>
  13. #include <asm/page.h>
  14. #include "proc-macros.S"
  15. /*
  16. * flush_user_cache_all()
  17. *
  18. * Invalidate all cache entries in a particular address
  19. * space.
  20. *
  21. * - mm - mm_struct describing address space
  22. */
  23. ENTRY(v3_flush_user_cache_all)
  24. /* FALLTHROUGH */
  25. /*
  26. * flush_kern_cache_all()
  27. *
  28. * Clean and invalidate the entire cache.
  29. */
  30. ENTRY(v3_flush_kern_cache_all)
  31. /* FALLTHROUGH */
  32. /*
  33. * flush_user_cache_range(start, end, flags)
  34. *
  35. * Invalidate a range of cache entries in the specified
  36. * address space.
  37. *
  38. * - start - start address (may not be aligned)
  39. * - end - end address (exclusive, may not be aligned)
  40. * - flags - vma_area_struct flags describing address space
  41. */
  42. ENTRY(v3_flush_user_cache_range)
  43. mov ip, #0
  44. mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
  45. mov pc, lr
  46. /*
  47. * coherent_kern_range(start, end)
  48. *
  49. * Ensure coherency between the Icache and the Dcache in the
  50. * region described by start. If you have non-snooping
  51. * Harvard caches, you need to implement this function.
  52. *
  53. * - start - virtual start address
  54. * - end - virtual end address
  55. */
  56. ENTRY(v3_coherent_kern_range)
  57. /* FALLTHROUGH */
  58. /*
  59. * coherent_user_range(start, end)
  60. *
  61. * Ensure coherency between the Icache and the Dcache in the
  62. * region described by start. If you have non-snooping
  63. * Harvard caches, you need to implement this function.
  64. *
  65. * - start - virtual start address
  66. * - end - virtual end address
  67. */
  68. ENTRY(v3_coherent_user_range)
  69. mov pc, lr
  70. /*
  71. * flush_kern_dcache_page(void *page)
  72. *
  73. * Ensure no D cache aliasing occurs, either with itself or
  74. * the I cache
  75. *
  76. * - addr - page aligned address
  77. */
  78. ENTRY(v3_flush_kern_dcache_page)
  79. /* FALLTHROUGH */
  80. /*
  81. * dma_inv_range(start, end)
  82. *
  83. * Invalidate (discard) the specified virtual address range.
  84. * May not write back any entries. If 'start' or 'end'
  85. * are not cache line aligned, those lines must be written
  86. * back.
  87. *
  88. * - start - virtual start address
  89. * - end - virtual end address
  90. */
  91. ENTRY(v3_dma_inv_range)
  92. /* FALLTHROUGH */
  93. /*
  94. * dma_flush_range(start, end)
  95. *
  96. * Clean and invalidate the specified virtual address range.
  97. *
  98. * - start - virtual start address
  99. * - end - virtual end address
  100. */
  101. ENTRY(v3_dma_flush_range)
  102. mov r0, #0
  103. mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
  104. /* FALLTHROUGH */
  105. /*
  106. * dma_clean_range(start, end)
  107. *
  108. * Clean (write back) the specified virtual address range.
  109. *
  110. * - start - virtual start address
  111. * - end - virtual end address
  112. */
  113. ENTRY(v3_dma_clean_range)
  114. mov pc, lr
  115. __INITDATA
  116. .type v3_cache_fns, #object
  117. ENTRY(v3_cache_fns)
  118. .long v3_flush_kern_cache_all
  119. .long v3_flush_user_cache_all
  120. .long v3_flush_user_cache_range
  121. .long v3_coherent_kern_range
  122. .long v3_coherent_user_range
  123. .long v3_flush_kern_dcache_page
  124. .long v3_dma_inv_range
  125. .long v3_dma_clean_range
  126. .long v3_dma_flush_range
  127. .size v3_cache_fns, . - v3_cache_fns