cache-l2x0.c 2.6 KB

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  1. /*
  2. * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
  3. *
  4. * Copyright (C) 2007 ARM Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <asm/cacheflush.h>
  21. #include <asm/io.h>
  22. #include <asm/hardware/cache-l2x0.h>
  23. #define CACHE_LINE_SIZE 32
  24. static void __iomem *l2x0_base;
  25. static inline void sync_writel(unsigned long val, unsigned long reg,
  26. unsigned long complete_mask)
  27. {
  28. writel(val, l2x0_base + reg);
  29. /* wait for the operation to complete */
  30. while (readl(l2x0_base + reg) & complete_mask)
  31. ;
  32. }
  33. static inline void cache_sync(void)
  34. {
  35. sync_writel(0, L2X0_CACHE_SYNC, 1);
  36. }
  37. static inline void l2x0_inv_all(void)
  38. {
  39. /* invalidate all ways */
  40. sync_writel(0xff, L2X0_INV_WAY, 0xff);
  41. cache_sync();
  42. }
  43. static void l2x0_inv_range(unsigned long start, unsigned long end)
  44. {
  45. unsigned long addr;
  46. start &= ~(CACHE_LINE_SIZE - 1);
  47. for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
  48. sync_writel(addr, L2X0_INV_LINE_PA, 1);
  49. cache_sync();
  50. }
  51. static void l2x0_clean_range(unsigned long start, unsigned long end)
  52. {
  53. unsigned long addr;
  54. start &= ~(CACHE_LINE_SIZE - 1);
  55. for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
  56. sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
  57. cache_sync();
  58. }
  59. static void l2x0_flush_range(unsigned long start, unsigned long end)
  60. {
  61. unsigned long addr;
  62. start &= ~(CACHE_LINE_SIZE - 1);
  63. for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
  64. sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
  65. cache_sync();
  66. }
  67. void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
  68. {
  69. __u32 aux;
  70. l2x0_base = base;
  71. /* disable L2X0 */
  72. writel(0, l2x0_base + L2X0_CTRL);
  73. aux = readl(l2x0_base + L2X0_AUX_CTRL);
  74. aux &= aux_mask;
  75. aux |= aux_val;
  76. writel(aux, l2x0_base + L2X0_AUX_CTRL);
  77. l2x0_inv_all();
  78. /* enable L2X0 */
  79. writel(1, l2x0_base + L2X0_CTRL);
  80. outer_cache.inv_range = l2x0_inv_range;
  81. outer_cache.clean_range = l2x0_clean_range;
  82. outer_cache.flush_range = l2x0_flush_range;
  83. printk(KERN_INFO "L2X0 cache controller enabled\n");
  84. }