abort-lv4t.S 6.4 KB

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  1. #include <linux/linkage.h>
  2. #include <asm/assembler.h>
  3. /*
  4. * Function: v4t_late_abort
  5. *
  6. * Params : r2 = address of aborted instruction
  7. * : r3 = saved SPSR
  8. *
  9. * Returns : r0 = address of abort
  10. * : r1 = FSR, bit 11 = write
  11. * : r2-r8 = corrupted
  12. * : r9 = preserved
  13. * : sp = pointer to registers
  14. *
  15. * Purpose : obtain information about current aborted instruction.
  16. * Note: we read user space. This means we might cause a data
  17. * abort here if the I-TLB and D-TLB aren't seeing the same
  18. * picture. Unfortunately, this does happen. We live with it.
  19. */
  20. ENTRY(v4t_late_abort)
  21. tst r3, #PSR_T_BIT @ check for thumb mode
  22. #ifdef CONFIG_CPU_CP15_MMU
  23. mrc p15, 0, r1, c5, c0, 0 @ get FSR
  24. mrc p15, 0, r0, c6, c0, 0 @ get FAR
  25. bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
  26. #else
  27. mov r0, #0 @ clear r0, r1 (no FSR/FAR)
  28. mov r1, #0
  29. #endif
  30. bne .data_thumb_abort
  31. ldr r8, [r2] @ read arm instruction
  32. tst r8, #1 << 20 @ L = 1 -> write?
  33. orreq r1, r1, #1 << 11 @ yes.
  34. and r7, r8, #15 << 24
  35. add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
  36. nop
  37. /* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm
  38. /* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm]
  39. /* 2 */ b .data_unknown
  40. /* 3 */ b .data_unknown
  41. /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
  42. /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
  43. /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
  44. /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
  45. /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
  46. /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
  47. /* a */ b .data_unknown
  48. /* b */ b .data_unknown
  49. /* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
  50. /* d */ mov pc, lr @ ldc rd, [rn, #m]
  51. /* e */ b .data_unknown
  52. /* f */
  53. .data_unknown: @ Part of jumptable
  54. mov r0, r2
  55. mov r1, r8
  56. mov r2, sp
  57. bl baddataabort
  58. b ret_from_exception
  59. .data_arm_ldmstm:
  60. tst r8, #1 << 21 @ check writeback bit
  61. moveq pc, lr @ no writeback -> no fixup
  62. mov r7, #0x11
  63. orr r7, r7, #0x1100
  64. and r6, r8, r7
  65. and r2, r8, r7, lsl #1
  66. add r6, r6, r2, lsr #1
  67. and r2, r8, r7, lsl #2
  68. add r6, r6, r2, lsr #2
  69. and r2, r8, r7, lsl #3
  70. add r6, r6, r2, lsr #3
  71. add r6, r6, r6, lsr #8
  72. add r6, r6, r6, lsr #4
  73. and r6, r6, #15 @ r6 = no. of registers to transfer.
  74. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  75. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  76. tst r8, #1 << 23 @ Check U bit
  77. subne r7, r7, r6, lsl #2 @ Undo increment
  78. addeq r7, r7, r6, lsl #2 @ Undo decrement
  79. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  80. mov pc, lr
  81. .data_arm_lateldrhpre:
  82. tst r8, #1 << 21 @ Check writeback bit
  83. moveq pc, lr @ No writeback -> no fixup
  84. .data_arm_lateldrhpost:
  85. and r5, r8, #0x00f @ get Rm / low nibble of immediate value
  86. tst r8, #1 << 22 @ if (immediate offset)
  87. andne r6, r8, #0xf00 @ { immediate high nibble
  88. orrne r6, r5, r6, lsr #4 @ combine nibbles } else
  89. ldreq r6, [sp, r5, lsl #2] @ { load Rm value }
  90. .data_arm_apply_r6_and_rn:
  91. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  92. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  93. tst r8, #1 << 23 @ Check U bit
  94. subne r7, r7, r6 @ Undo incrmenet
  95. addeq r7, r7, r6 @ Undo decrement
  96. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  97. mov pc, lr
  98. .data_arm_lateldrpreconst:
  99. tst r8, #1 << 21 @ check writeback bit
  100. moveq pc, lr @ no writeback -> no fixup
  101. .data_arm_lateldrpostconst:
  102. movs r2, r8, lsl #20 @ Get offset
  103. moveq pc, lr @ zero -> no fixup
  104. and r5, r8, #15 << 16 @ Extract 'n' from instruction
  105. ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
  106. tst r8, #1 << 23 @ Check U bit
  107. subne r7, r7, r2, lsr #20 @ Undo increment
  108. addeq r7, r7, r2, lsr #20 @ Undo decrement
  109. str r7, [sp, r5, lsr #14] @ Put register 'Rn'
  110. mov pc, lr
  111. .data_arm_lateldrprereg:
  112. tst r8, #1 << 21 @ check writeback bit
  113. moveq pc, lr @ no writeback -> no fixup
  114. .data_arm_lateldrpostreg:
  115. and r7, r8, #15 @ Extract 'm' from instruction
  116. ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
  117. mov r5, r8, lsr #7 @ get shift count
  118. ands r5, r5, #31
  119. and r7, r8, #0x70 @ get shift type
  120. orreq r7, r7, #8 @ shift count = 0
  121. add pc, pc, r7
  122. nop
  123. mov r6, r6, lsl r5 @ 0: LSL #!0
  124. b .data_arm_apply_r6_and_rn
  125. b .data_arm_apply_r6_and_rn @ 1: LSL #0
  126. nop
  127. b .data_unknown @ 2: MUL?
  128. nop
  129. b .data_unknown @ 3: MUL?
  130. nop
  131. mov r6, r6, lsr r5 @ 4: LSR #!0
  132. b .data_arm_apply_r6_and_rn
  133. mov r6, r6, lsr #32 @ 5: LSR #32
  134. b .data_arm_apply_r6_and_rn
  135. b .data_unknown @ 6: MUL?
  136. nop
  137. b .data_unknown @ 7: MUL?
  138. nop
  139. mov r6, r6, asr r5 @ 8: ASR #!0
  140. b .data_arm_apply_r6_and_rn
  141. mov r6, r6, asr #32 @ 9: ASR #32
  142. b .data_arm_apply_r6_and_rn
  143. b .data_unknown @ A: MUL?
  144. nop
  145. b .data_unknown @ B: MUL?
  146. nop
  147. mov r6, r6, ror r5 @ C: ROR #!0
  148. b .data_arm_apply_r6_and_rn
  149. mov r6, r6, rrx @ D: RRX
  150. b .data_arm_apply_r6_and_rn
  151. b .data_unknown @ E: MUL?
  152. nop
  153. b .data_unknown @ F: MUL?
  154. .data_thumb_abort:
  155. ldrh r8, [r2] @ read instruction
  156. tst r8, #1 << 11 @ L = 1 -> write?
  157. orreq r1, r1, #1 << 8 @ yes
  158. and r7, r8, #15 << 12
  159. add pc, pc, r7, lsr #10 @ lookup in table
  160. nop
  161. /* 0 */ b .data_unknown
  162. /* 1 */ b .data_unknown
  163. /* 2 */ b .data_unknown
  164. /* 3 */ b .data_unknown
  165. /* 4 */ b .data_unknown
  166. /* 5 */ b .data_thumb_reg
  167. /* 6 */ mov pc, lr
  168. /* 7 */ mov pc, lr
  169. /* 8 */ mov pc, lr
  170. /* 9 */ mov pc, lr
  171. /* A */ b .data_unknown
  172. /* B */ b .data_thumb_pushpop
  173. /* C */ b .data_thumb_ldmstm
  174. /* D */ b .data_unknown
  175. /* E */ b .data_unknown
  176. /* F */ b .data_unknown
  177. .data_thumb_reg:
  178. tst r8, #1 << 9
  179. moveq pc, lr
  180. tst r8, #1 << 10 @ If 'S' (signed) bit is set
  181. movne r1, #0 @ it must be a load instr
  182. mov pc, lr
  183. .data_thumb_pushpop:
  184. tst r8, #1 << 10
  185. beq .data_unknown
  186. and r6, r8, #0x55 @ hweight8(r8) + R bit
  187. and r2, r8, #0xaa
  188. add r6, r6, r2, lsr #1
  189. and r2, r6, #0xcc
  190. and r6, r6, #0x33
  191. add r6, r6, r2, lsr #2
  192. movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
  193. adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
  194. and r6, r6, #15 @ number of regs to transfer
  195. ldr r7, [sp, #13 << 2]
  196. tst r8, #1 << 11
  197. addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
  198. subne r7, r7, r6, lsl #2 @ decrement SP if POP
  199. str r7, [sp, #13 << 2]
  200. mov pc, lr
  201. .data_thumb_ldmstm:
  202. and r6, r8, #0x55 @ hweight8(r8)
  203. and r2, r8, #0xaa
  204. add r6, r6, r2, lsr #1
  205. and r2, r6, #0xcc
  206. and r6, r6, #0x33
  207. add r6, r6, r2, lsr #2
  208. add r6, r6, r6, lsr #4
  209. and r5, r8, #7 << 8
  210. ldr r7, [sp, r5, lsr #6]
  211. and r6, r6, #15 @ number of regs to transfer
  212. sub r7, r7, r6, lsl #2 @ always decrement
  213. str r7, [sp, r5, lsr #6]
  214. mov pc, lr