Kconfig 16 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor"
  11. depends on ARCH_RPC
  12. select CPU_32v3
  13. select CPU_CACHE_V3
  14. select CPU_CACHE_VIVT
  15. select CPU_CP15_MMU
  16. select CPU_COPY_V3 if MMU
  17. select CPU_TLB_V3 if MMU
  18. help
  19. The ARM610 is the successor to the ARM3 processor
  20. and was produced by VLSI Technology Inc.
  21. Say Y if you want support for the ARM610 processor.
  22. Otherwise, say N.
  23. # ARM7TDMI
  24. config CPU_ARM7TDMI
  25. bool "Support ARM7TDMI processor"
  26. depends on !MMU
  27. select CPU_32v4T
  28. select CPU_ABRT_LV4T
  29. select CPU_CACHE_V4
  30. help
  31. A 32-bit RISC microprocessor based on the ARM7 processor core
  32. which has no memory control unit and cache.
  33. Say Y if you want support for the ARM7TDMI processor.
  34. Otherwise, say N.
  35. # ARM710
  36. config CPU_ARM710
  37. bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  38. default y if ARCH_CLPS7500
  39. select CPU_32v3
  40. select CPU_CACHE_V3
  41. select CPU_CACHE_VIVT
  42. select CPU_CP15_MMU
  43. select CPU_COPY_V3 if MMU
  44. select CPU_TLB_V3 if MMU
  45. help
  46. A 32-bit RISC microprocessor based on the ARM7 processor core
  47. designed by Advanced RISC Machines Ltd. The ARM710 is the
  48. successor to the ARM610 processor. It was released in
  49. July 1994 by VLSI Technology Inc.
  50. Say Y if you want support for the ARM710 processor.
  51. Otherwise, say N.
  52. # ARM720T
  53. config CPU_ARM720T
  54. bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  55. default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  56. select CPU_32v4T
  57. select CPU_ABRT_LV4T
  58. select CPU_CACHE_V4
  59. select CPU_CACHE_VIVT
  60. select CPU_CP15_MMU
  61. select CPU_COPY_V4WT if MMU
  62. select CPU_TLB_V4WT if MMU
  63. help
  64. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  65. MMU built around an ARM7TDMI core.
  66. Say Y if you want support for the ARM720T processor.
  67. Otherwise, say N.
  68. # ARM740T
  69. config CPU_ARM740T
  70. bool "Support ARM740T processor" if ARCH_INTEGRATOR
  71. depends on !MMU
  72. select CPU_32v4T
  73. select CPU_ABRT_LV4T
  74. select CPU_CACHE_V3 # although the core is v4t
  75. select CPU_CP15_MPU
  76. help
  77. A 32-bit RISC processor with 8KB cache or 4KB variants,
  78. write buffer and MPU(Protection Unit) built around
  79. an ARM7TDMI core.
  80. Say Y if you want support for the ARM740T processor.
  81. Otherwise, say N.
  82. # ARM9TDMI
  83. config CPU_ARM9TDMI
  84. bool "Support ARM9TDMI processor"
  85. depends on !MMU
  86. select CPU_32v4T
  87. select CPU_ABRT_NOMMU
  88. select CPU_CACHE_V4
  89. help
  90. A 32-bit RISC microprocessor based on the ARM9 processor core
  91. which has no memory control unit and cache.
  92. Say Y if you want support for the ARM9TDMI processor.
  93. Otherwise, say N.
  94. # ARM920T
  95. config CPU_ARM920T
  96. bool "Support ARM920T processor"
  97. depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
  98. default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
  99. select CPU_32v4T
  100. select CPU_ABRT_EV4T
  101. select CPU_CACHE_V4WT
  102. select CPU_CACHE_VIVT
  103. select CPU_CP15_MMU
  104. select CPU_COPY_V4WB if MMU
  105. select CPU_TLB_V4WBI if MMU
  106. help
  107. The ARM920T is licensed to be produced by numerous vendors,
  108. and is used in the Maverick EP9312 and the Samsung S3C2410.
  109. More information on the Maverick EP9312 at
  110. <http://linuxdevices.com/products/PD2382866068.html>.
  111. Say Y if you want support for the ARM920T processor.
  112. Otherwise, say N.
  113. # ARM922T
  114. config CPU_ARM922T
  115. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  116. depends on ARCH_LH7A40X || ARCH_INTEGRATOR
  117. default y if ARCH_LH7A40X
  118. select CPU_32v4T
  119. select CPU_ABRT_EV4T
  120. select CPU_CACHE_V4WT
  121. select CPU_CACHE_VIVT
  122. select CPU_CP15_MMU
  123. select CPU_COPY_V4WB if MMU
  124. select CPU_TLB_V4WBI if MMU
  125. help
  126. The ARM922T is a version of the ARM920T, but with smaller
  127. instruction and data caches. It is used in Altera's
  128. Excalibur XA device family.
  129. Say Y if you want support for the ARM922T processor.
  130. Otherwise, say N.
  131. # ARM925T
  132. config CPU_ARM925T
  133. bool "Support ARM925T processor" if ARCH_OMAP1
  134. depends on ARCH_OMAP15XX
  135. default y if ARCH_OMAP15XX
  136. select CPU_32v4T
  137. select CPU_ABRT_EV4T
  138. select CPU_CACHE_V4WT
  139. select CPU_CACHE_VIVT
  140. select CPU_CP15_MMU
  141. select CPU_COPY_V4WB if MMU
  142. select CPU_TLB_V4WBI if MMU
  143. help
  144. The ARM925T is a mix between the ARM920T and ARM926T, but with
  145. different instruction and data caches. It is used in TI's OMAP
  146. device family.
  147. Say Y if you want support for the ARM925T processor.
  148. Otherwise, say N.
  149. # ARM926T
  150. config CPU_ARM926T
  151. bool "Support ARM926T processor"
  152. depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || CPU_S3C2450 || CPU_S3C2416
  153. default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || CPU_S3C2450 || CPU_S3C2416
  154. select CPU_32v5
  155. select CPU_ABRT_EV5TJ
  156. select CPU_CACHE_VIVT
  157. select CPU_CP15_MMU
  158. select CPU_COPY_V4WB if MMU
  159. select CPU_TLB_V4WBI if MMU
  160. help
  161. This is a variant of the ARM920. It has slightly different
  162. instruction sequences for cache and TLB operations. Curiously,
  163. there is no documentation on it at the ARM corporate website.
  164. Say Y if you want support for the ARM926T processor.
  165. Otherwise, say N.
  166. # ARM940T
  167. config CPU_ARM940T
  168. bool "Support ARM940T processor" if ARCH_INTEGRATOR
  169. depends on !MMU
  170. select CPU_32v4T
  171. select CPU_ABRT_NOMMU
  172. select CPU_CACHE_VIVT
  173. select CPU_CP15_MPU
  174. help
  175. ARM940T is a member of the ARM9TDMI family of general-
  176. purpose microprocessors with MPU and separate 4KB
  177. instruction and 4KB data cases, each with a 4-word line
  178. length.
  179. Say Y if you want support for the ARM940T processor.
  180. Otherwise, say N.
  181. # ARM946E-S
  182. config CPU_ARM946E
  183. bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
  184. depends on !MMU
  185. select CPU_32v5
  186. select CPU_ABRT_NOMMU
  187. select CPU_CACHE_VIVT
  188. select CPU_CP15_MPU
  189. help
  190. ARM946E-S is a member of the ARM9E-S family of high-
  191. performance, 32-bit system-on-chip processor solutions.
  192. The TCM and ARMv5TE 32-bit instruction set is supported.
  193. Say Y if you want support for the ARM946E-S processor.
  194. Otherwise, say N.
  195. # ARM1020 - needs validating
  196. config CPU_ARM1020
  197. bool "Support ARM1020T (rev 0) processor"
  198. depends on ARCH_INTEGRATOR
  199. select CPU_32v5
  200. select CPU_ABRT_EV4T
  201. select CPU_CACHE_V4WT
  202. select CPU_CACHE_VIVT
  203. select CPU_CP15_MMU
  204. select CPU_COPY_V4WB if MMU
  205. select CPU_TLB_V4WBI if MMU
  206. help
  207. The ARM1020 is the 32K cached version of the ARM10 processor,
  208. with an addition of a floating-point unit.
  209. Say Y if you want support for the ARM1020 processor.
  210. Otherwise, say N.
  211. # ARM1020E - needs validating
  212. config CPU_ARM1020E
  213. bool "Support ARM1020E processor"
  214. depends on ARCH_INTEGRATOR
  215. select CPU_32v5
  216. select CPU_ABRT_EV4T
  217. select CPU_CACHE_V4WT
  218. select CPU_CACHE_VIVT
  219. select CPU_CP15_MMU
  220. select CPU_COPY_V4WB if MMU
  221. select CPU_TLB_V4WBI if MMU
  222. depends on n
  223. # ARM1022E
  224. config CPU_ARM1022
  225. bool "Support ARM1022E processor"
  226. depends on ARCH_INTEGRATOR
  227. select CPU_32v5
  228. select CPU_ABRT_EV4T
  229. select CPU_CACHE_VIVT
  230. select CPU_CP15_MMU
  231. select CPU_COPY_V4WB if MMU # can probably do better
  232. select CPU_TLB_V4WBI if MMU
  233. help
  234. The ARM1022E is an implementation of the ARMv5TE architecture
  235. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  236. embedded trace macrocell, and a floating-point unit.
  237. Say Y if you want support for the ARM1022E processor.
  238. Otherwise, say N.
  239. # ARM1026EJ-S
  240. config CPU_ARM1026
  241. bool "Support ARM1026EJ-S processor"
  242. depends on ARCH_INTEGRATOR
  243. select CPU_32v5
  244. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  245. select CPU_CACHE_VIVT
  246. select CPU_CP15_MMU
  247. select CPU_COPY_V4WB if MMU # can probably do better
  248. select CPU_TLB_V4WBI if MMU
  249. help
  250. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  251. based upon the ARM10 integer core.
  252. Say Y if you want support for the ARM1026EJ-S processor.
  253. Otherwise, say N.
  254. # SA110
  255. config CPU_SA110
  256. bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
  257. default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
  258. select CPU_32v3 if ARCH_RPC
  259. select CPU_32v4 if !ARCH_RPC
  260. select CPU_ABRT_EV4
  261. select CPU_CACHE_V4WB
  262. select CPU_CACHE_VIVT
  263. select CPU_CP15_MMU
  264. select CPU_COPY_V4WB if MMU
  265. select CPU_TLB_V4WB if MMU
  266. help
  267. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  268. is available at five speeds ranging from 100 MHz to 233 MHz.
  269. More information is available at
  270. <http://developer.intel.com/design/strong/sa110.htm>.
  271. Say Y if you want support for the SA-110 processor.
  272. Otherwise, say N.
  273. # SA1100
  274. config CPU_SA1100
  275. bool
  276. depends on ARCH_SA1100
  277. default y
  278. select CPU_32v4
  279. select CPU_ABRT_EV4
  280. select CPU_CACHE_V4WB
  281. select CPU_CACHE_VIVT
  282. select CPU_CP15_MMU
  283. select CPU_TLB_V4WB if MMU
  284. # XScale
  285. config CPU_XSCALE
  286. bool
  287. depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
  288. default y
  289. select CPU_32v5
  290. select CPU_ABRT_EV5T
  291. select CPU_CACHE_VIVT
  292. select CPU_CP15_MMU
  293. select CPU_TLB_V4WBI if MMU
  294. # XScale Core Version 3
  295. config CPU_XSC3
  296. bool
  297. depends on ARCH_IXP23XX || ARCH_IOP13XX
  298. default y
  299. select CPU_32v5
  300. select CPU_ABRT_EV5T
  301. select CPU_CACHE_VIVT
  302. select CPU_CP15_MMU
  303. select CPU_TLB_V4WBI if MMU
  304. select IO_36
  305. # ARMv6
  306. config CPU_V6
  307. bool "Support ARM V6 processor"
  308. depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || CPU_S3C6400 || CPU_S3C6410
  309. select CPU_32v6
  310. select CPU_ABRT_EV6
  311. select CPU_CACHE_V6
  312. select CPU_CACHE_VIPT
  313. select CPU_CP15_MMU
  314. select CPU_COPY_V6 if MMU
  315. select CPU_TLB_V6 if MMU
  316. # ARMv6k
  317. config CPU_32v6K
  318. bool "Support ARM V6K processor extensions" if !SMP
  319. depends on CPU_V6
  320. default y if SMP
  321. help
  322. Say Y here if your ARMv6 processor supports the 'K' extension.
  323. This enables the kernel to use some instructions not present
  324. on previous processors, and as such a kernel build with this
  325. enabled will not boot on processors with do not support these
  326. instructions.
  327. # Figure out what processor architecture version we should be using.
  328. # This defines the compiler instruction set which depends on the machine type.
  329. config CPU_32v3
  330. bool
  331. select TLS_REG_EMUL if SMP || !MMU
  332. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  333. config CPU_32v4
  334. bool
  335. select TLS_REG_EMUL if SMP || !MMU
  336. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  337. config CPU_32v4T
  338. bool
  339. select TLS_REG_EMUL if SMP || !MMU
  340. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  341. config CPU_32v5
  342. bool
  343. select TLS_REG_EMUL if SMP || !MMU
  344. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  345. config CPU_32v6
  346. bool
  347. # The abort model
  348. config CPU_ABRT_NOMMU
  349. bool
  350. config CPU_ABRT_EV4
  351. bool
  352. config CPU_ABRT_EV4T
  353. bool
  354. config CPU_ABRT_LV4T
  355. bool
  356. config CPU_ABRT_EV5T
  357. bool
  358. config CPU_ABRT_EV5TJ
  359. bool
  360. config CPU_ABRT_EV6
  361. bool
  362. # The cache model
  363. config CPU_CACHE_V3
  364. bool
  365. config CPU_CACHE_V4
  366. bool
  367. config CPU_CACHE_V4WT
  368. bool
  369. config CPU_CACHE_V4WB
  370. bool
  371. config CPU_CACHE_V6
  372. bool
  373. config CPU_CACHE_VIVT
  374. bool
  375. config CPU_CACHE_VIPT
  376. bool
  377. if MMU
  378. # The copy-page model
  379. config CPU_COPY_V3
  380. bool
  381. config CPU_COPY_V4WT
  382. bool
  383. config CPU_COPY_V4WB
  384. bool
  385. config CPU_COPY_V6
  386. bool
  387. # This selects the TLB model
  388. config CPU_TLB_V3
  389. bool
  390. help
  391. ARM Architecture Version 3 TLB.
  392. config CPU_TLB_V4WT
  393. bool
  394. help
  395. ARM Architecture Version 4 TLB with writethrough cache.
  396. config CPU_TLB_V4WB
  397. bool
  398. help
  399. ARM Architecture Version 4 TLB with writeback cache.
  400. config CPU_TLB_V4WBI
  401. bool
  402. help
  403. ARM Architecture Version 4 TLB with writeback cache and invalidate
  404. instruction cache entry.
  405. config CPU_TLB_V6
  406. bool
  407. endif
  408. config CPU_CP15
  409. bool
  410. help
  411. Processor has the CP15 register.
  412. config CPU_CP15_MMU
  413. bool
  414. select CPU_CP15
  415. help
  416. Processor has the CP15 register, which has MMU related registers.
  417. config CPU_CP15_MPU
  418. bool
  419. select CPU_CP15
  420. help
  421. Processor has the CP15 register, which has MPU related registers.
  422. #
  423. # CPU supports 36-bit I/O
  424. #
  425. config IO_36
  426. bool
  427. comment "Processor Features"
  428. config ARM_THUMB
  429. bool "Support Thumb user binaries"
  430. depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
  431. default y
  432. help
  433. Say Y if you want to include kernel support for running user space
  434. Thumb binaries.
  435. The Thumb instruction set is a compressed form of the standard ARM
  436. instruction set resulting in smaller binaries at the expense of
  437. slightly less efficient code.
  438. If you don't know what this all is, saying Y is a safe choice.
  439. config CPU_BIG_ENDIAN
  440. bool "Build big-endian kernel"
  441. depends on ARCH_SUPPORTS_BIG_ENDIAN
  442. help
  443. Say Y if you plan on running a kernel in big-endian mode.
  444. Note that your board must be properly built and your board
  445. port must properly enable any big-endian related features
  446. of your chipset/board/processor.
  447. config CPU_HIGH_VECTOR
  448. depends on !MMU && CPU_CP15 && !CPU_ARM740T
  449. bool "Select the High exception vector"
  450. default n
  451. help
  452. Say Y here to select high exception vector(0xFFFF0000~).
  453. The exception vector can be vary depending on the platform
  454. design in nommu mode. If your platform needs to select
  455. high exception vector, say Y.
  456. Otherwise or if you are unsure, say N, and the low exception
  457. vector (0x00000000~) will be used.
  458. config CPU_ICACHE_DISABLE
  459. bool "Disable I-Cache (I-bit)"
  460. depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
  461. help
  462. Say Y here to disable the processor instruction cache. Unless
  463. you have a reason not to or are unsure, say N.
  464. config CPU_DCACHE_DISABLE
  465. bool "Disable D-Cache (C-bit)"
  466. depends on CPU_CP15
  467. help
  468. Say Y here to disable the processor data cache. Unless
  469. you have a reason not to or are unsure, say N.
  470. config CPU_DCACHE_SIZE
  471. hex
  472. depends on CPU_ARM740T || CPU_ARM946E
  473. default 0x00001000 if CPU_ARM740T
  474. default 0x00002000 # default size for ARM946E-S
  475. help
  476. Some cores are synthesizable to have various sized cache. For
  477. ARM946E-S case, it can vary from 0KB to 1MB.
  478. To support such cache operations, it is efficient to know the size
  479. before compile time.
  480. If your SoC is configured to have a different size, define the value
  481. here with proper conditions.
  482. config CPU_DCACHE_WRITETHROUGH
  483. bool "Force write through D-cache"
  484. depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
  485. default y if CPU_ARM925T
  486. help
  487. Say Y here to use the data cache in writethrough mode. Unless you
  488. specifically require this or are unsure, say N.
  489. config CPU_CACHE_ROUND_ROBIN
  490. bool "Round robin I and D cache replacement algorithm"
  491. depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  492. help
  493. Say Y here to use the predictable round-robin cache replacement
  494. policy. Unless you specifically require this or are unsure, say N.
  495. config CPU_BPREDICT_DISABLE
  496. bool "Disable branch prediction"
  497. depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
  498. help
  499. Say Y here to disable branch prediction. If unsure, say N.
  500. config TLS_REG_EMUL
  501. bool
  502. help
  503. An SMP system using a pre-ARMv6 processor (there are apparently
  504. a few prototypes like that in existence) and therefore access to
  505. that required register must be emulated.
  506. config HAS_TLS_REG
  507. bool
  508. depends on !TLS_REG_EMUL
  509. default y if SMP || CPU_32v7
  510. help
  511. This selects support for the CP15 thread register.
  512. It is defined to be available on some ARMv6 processors (including
  513. all SMP capable ARMv6's) or later processors. User space may
  514. assume directly accessing that register and always obtain the
  515. expected value only on ARMv7 and above.
  516. config NEEDS_SYSCALL_FOR_CMPXCHG
  517. bool
  518. help
  519. SMP on a pre-ARMv6 processor? Well OK then.
  520. Forget about fast user space cmpxchg support.
  521. It is just not possible.
  522. config OUTER_CACHE
  523. bool
  524. default n
  525. config CACHE_L2X0
  526. bool
  527. select OUTER_CACHE